Convert the Texas Instruments DA850/AM18x Video Port Interface (VPIF)
device tree binding from text format to YAML dt-schema.
Add power-domains property missing from text.
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Link: https://patch.msgid.link/20260813-ti-da850-vpif-v2-1-80ba62ca53d0@gmail.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
The "{,N}" regex syntax is non-standard, but happens to be supported by
python re module. It is equivalent to "{0,N}" which is more commonly
supported. This fixes using a rust implementation of the DT schema
tools.
Link: https://patch.msgid.link/20260813174037.2263884-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
The $ref "arm,gic.yaml#/properties/#interrupt-cells" doesn't work when
used with another json-schema implementation (rust). The issue is it not
a valid URI due to the 2nd "#" character in the JSON pointer. Though a
"#" is supposed to be valid within a JSON pointer. A possible solution
is to encode the "#" as "%23" instead, but the dtschema tools don't
handle that.
Just avoid all these issues as the $ref only resolves to a "const: 3"
schema and specify it directly.
Link: https://patch.msgid.link/20260813145453.1919998-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
The A733 has six SPI controllers with the same IP as the A523.
Like the A523, one of them (spi1) also supports DBI mode.
Add SoC specific compatible strings, falling back to the A523 ones.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patch.msgid.link/20260812-allwinner-a733-spi-support-v2-1-937bff0fa78e@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The Loongson-2K0300 SoC exposes its chip ID registers through a syscon
interface. Add the specific compatible `loongson,ls2k0300-chipid-syscon`
to the allowed list of syscon bindings so that it can be referenced from
the thermal node via a phandle.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/b76405a88b0cded91ba370139d7223fe2d6953df.1785829933.git.zhoubinbin@loongson.cn
Signed-off-by: Lee Jones <lee@kernel.org>
The ES8316 has separate AVDD, CPVDD, DVDD and PVDD supply inputs for
its analog, charge pump, digital core and digital I/O domains. Describe
all four inputs so boards can model the codec power topology.
The binding also covers ES8311 and ES8323, whose supply inputs differ,
so restrict these properties to the ES8316 compatible. Keep them
optional for compatibility with existing descriptions.
Signed-off-by: Hongyang Zhao <hongyang.zhao@thundersoft.com>
Link: https://patch.msgid.link/20260812-es8316-regulator-next-20260722-v2-1-e7078bc9bc9c@thundersoft.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add global, TCSR, RPMh, and video clock controller support for Maili.
Add global, RPM, GPU, display, and audio core clock controller support for
Shikra. Add display and graphics clock controllers for Nord.
Add Glymur camera and EVA clock controllers, the IPQ9650 REFGEN clocks, and
Hawi video clock controller support. Extend the IPQ5210 APSS PLL and RPM
clock support for Agatti.
Enable runtime PM and regulator-backed reference clock handling where needed.
Update QCM2290 clock and power-domain handling, critical clock definitions,
and arm architecture Kconfig defaults.
Correct MDM9607, MSM8916, MSM8939, SM6115, QCS8300, Kaanapali, and Glymur
clock and power-domain handling. Improve GDSC error propagation and teardown.
Update bindings for the added controllers and required power and OPP
properties.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmp2AIsOHGJqb3JuQGty
eW8uc2UACgkQCx85Pw2ZrcVp1Q/8DSFhshwLJ7BxaKUyYcoL0oCzRRMoH5U3UEw6
9iYM+bGbeNSguZW5d3fKQhOX4EHULk/nOHuP3nril1jeOUCMZlF6BaZcFaWxQN8I
E26T3STNS1JYyQDGzUMAc9mL44nV/XfurA6w0BCkwGHZ4kFmgBJHWn8ns9jaxW6z
jlTg9aUwm/omId3pkuB6LY0A7oTBOX8Vul/i+6CAh5JXr7JL2M+gU9rnqnNVJ2ug
PX+m7phzZNaflVK6GsUP4TI/CPqgPWyeeccA/POQ4xkREwivZb8VpaV9LKPqqSmY
3SJ3bNaBd0nadsHoJiEbBflCWx88eMAXuXhMGHsxveA1KoTaxBJVDK3nzEqulobN
xdLd9XXA+OJ9fMT3rVxmupldbkPlfxH1NIIxtSlAZlMb10SBo0O7S4EyzWisHSfP
S5wFTprc3NLnqfHa+14inleIOqRGLRbHe2hb2dJRxv8Nxv0u82VGe0xEOk0oHgjS
i60Sm8Hl81svH+sxICVBPDZ7JEH9FY3mHNav/DDcBbX9Bukg7xybgOonP5Y4K3E4
fAGU8T1SMRe3u+dsZmjR07ZFmEQgevefE8diDA8Z/bpND/HOWsjBILMUcz87aaYt
YVu9BE+mOzIektehQcLsRkgmP15xLuCOEfpeL46I8mNEWPgfl1jfVyjEdFs2BFcn
Rkj+acY=
=1e93
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8Dc4UHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSUQihAAwkz9Uc6w+wI4IuD1aGOcnj1/SQOe
vFaylCwhUDb85ryx2TrwmXDAorxt1kPxVYGSNCmwTUP3KamDxtDIdqdxdB7AsKnq
SNFe2JOx0pFDtGOKRqG3hCiml3GlIMzQQmbXCXKxPLK6NaVxNZwaJzrqhfMiJqji
tGNWxllEMws82jWJ8N20+OLkpPcfV9CGxPwWFU6G+IrZpbmhCuzXqbaHOExQy2vz
xMdcYRkVTZy4elI1ab6OTc3wQyu3zPL5dwBpTuWdbxLIvVbQChcgn9VGb9BITlBG
+H8M9f5fzBkEkbI8m1l0wUm5mBfLiD+b4E72Y0UYMKsGp7oiJZCz/Tdm2eTdile7
IjhbOksiqJA824iN1AKtS1pqImmDkKJHHQcSHh7tANceFz+BkL4av4/pkrE3e6mu
WZ7SoMQuWdXQuhnwzqnr0IOttKMmlBYvzdH+7tJ5IseM5kihXD/JugqqEA0lC7Rs
4BUbmV09Snrx/06EmIs7E4MNprPAiN//AjstmJOJli2eZYKBnccpXCWG/VQ7GkJ+
k5pkcGVjFMKtXUFwd4cgnTB8PQTdeF9f6nde6jjX42sD72qESLqqRpykj5UCg+D1
zfZMvBQMbgdjVVx0IbsgkFWtO6rDn6cbNjluAjPTIiXcnE2ckCv5wSpDlxIE3K28
dBIq1TQFxXKgLlk=
=Ge5l
-----END PGP SIGNATURE-----
Merge tag 'qcom-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
Add global, TCSR, RPMh, and video clock controller support for Maili.
Add global, RPM, GPU, display, and audio core clock controller support for
Shikra. Add display and graphics clock controllers for Nord.
Add Glymur camera and EVA clock controllers, the IPQ9650 REFGEN clocks, and
Hawi video clock controller support. Extend the IPQ5210 APSS PLL and RPM
clock support for Agatti.
Enable runtime PM and regulator-backed reference clock handling where needed.
Update QCM2290 clock and power-domain handling, critical clock definitions,
and arm architecture Kconfig defaults.
Correct MDM9607, MSM8916, MSM8939, SM6115, QCS8300, Kaanapali, and Glymur
clock and power-domain handling. Improve GDSC error propagation and teardown.
Update bindings for the added controllers and required power and OPP
properties.
* tag 'qcom-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (94 commits)
clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra
clk: qcom: Return expected ENOMEM error on dynamic allocation failure
clk: qcom: apss-ipq-pll: Add IPQ5210 support
dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible
clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller
dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller
dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller
clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable
clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe
clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
clk: qcom: gpucc-qcm2290: Drop pm_clk handling
clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values
clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs
clk: qcom: dispcc-qcm2290: Enable runtime PM support
clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model
clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property
clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
...
fractional PLL coefficients and a fix for the dclk of the 3rd video-port to
not affect other compoents when its rate gets changed.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmpzqVIQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgTYRB/9lSKLStQtLlreGs6zY5F2fVLN6qUgimFuz
t7MFxUTJp/J8dArPK/PST78s+dbFcI2U2d+4K24zuDtNJm7Zsw3sEEcNjFRNqcnN
FRyXdT1Yc1EhTFlwg8rSeVC/sCznm1b59BMBPRP2u11kDtPtS1HxpEPACFBg4rIg
Bul89omf3Iyq//W5wweb69IK0GxAw3fldjgONOd9D1yd+GvO/HW/V03bXbX71T9Z
RkSSyQ3E8bdxJzdEMUgaSSFVAxSCji0v8H30Kp5hlWm4JX3yhZzyTHcvv/QwxgNk
F+irFyG5GfFzVg1wN+E55bdcL8o6OthIocVd9ae+OtKs5GFotzsi
=6iqM
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8DQIUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSV6Pw/9Fgw7gZRPS0KFJ/MXUgc/AZikVlpU
r8GjmpcmpnjiZOIOKM2dvmBV7f1iB3xxNS0c9QDQ+HGa3G/+WWKsoHePumRVuJMf
Mq7Zds7TP4DOSrxQGmrGA8B7YAthPV3iSUxjnxd5di0KXf0958HWVdNuYUNuS2x2
3qHGpqt24zGG1PV/59QKHK+fzrMt6dMOLOscYwhoaaQrnxXt0nQjslwew7W2QSlF
5F/2g8KHg3ezZU0S0AWsZ2+b2yhEojGxjjYwBjEgFysiOABAd2EfilgSG3EU7l5f
41uf3eJKfbocz7Lw0ZoHo1TBc9OAvA9mPLwoj/eFEc1oIH//2ODsvsd4spOSimJz
RTWH2C9XJxlZKnBN/ZFRZtaghsdmF74iIumweekXXidsVP0+BsQyp6f6aKNOABiU
8RAEpL50vHFBt9RCNvV8dBghav6TWmR8oHkRlNoYzqZ9NX3L4wVQn8rhSNwwQcGw
mvs7ginmTQX+uC9qgHuIV4kP4WasYCfTzFQlPlFMoAtpgtggtuXzxqeJJEfTpRiW
080t0XVS5kMIFPgbd51xdpBe+BJTLKUq+k8wZuP0XazfENP/fgAj1sw2DXdkD3NU
IfknpUcBtywx5AIdXGWP7qNTWSJ+YAkSz/KTPd9f76UY1ToXgMMH2VAc42FD3rsf
Qe1OM6jN7BB4CW8=
=jLWg
-----END PGP SIGNATURE-----
Merge tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Clock driver for Rockchip RV1106
- Fix for Rockchip rk3576 spi source mux
- Better representing fractional PLL coefficients in Rockchip
clk driver
- Fix for the Rockchip dclk of the 3rd video-port to not affect
other compoents when its rate gets changed
* tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
clk: rockchip: Add clock controller for the RV1106
dt-bindings: clock: rockchip: Add RV1106 CRU support
clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement
clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs
clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs
clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src
* Fix the incorrect parent number of the 32k clock on GXBB
* Add the AO and peripheral clock controllers for the new A9 chip
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmpspMEACgkQ5vwPHDfy
2oUc2BAAr4p6ygDoxRof6N/NjNlJebaYWviWhwaKDdM9a8UaKKtYeqQP1ye/1Nzv
qIUcLCMDqQP1UU4xsErIDcuOLBEZ9l9WWUvL8aMJwNWyZ+l1BFdxROhnHTqfUj+i
j636C+7/t9/c7PVu5C+v7i7cAMPCQQx48p1KQskmWiEJBfOt8fgIbfpdIpy9HM4V
FprCnyMZdqx9DjUB1n9LWFwAN2skEwplZp3Vg0UZCtKLxdW6RGJ9ALYlknrWTkKL
hqWMMQFofNBlBlMaXKrNKAlZfaegn/0pNrAeIpX3rSk8a/bdjQ7FVPtFfSfIHcw+
Z8uoxef3yuLI+c8x/SrRCPSLe83ZalOGtontmuWGT6prE7E89HqS1IqUbVoiMlDD
EwbPUEGxLMMJUa3IP5WMGOCqTtnbiI/8gQVC4EgxPxWHiMr8qYHNRwVCfZhzZIic
iinEU4UqehOoySapEZum/neBCbl9eJbr5bxxt2aKl60fQcXBJDEDUcju5JG56zuT
m3OQAcAcKQoPcA4Fggdvyzc1eZMiEGjdYepT1WFNFq8aAA/qct0nse5GWyvZ9ZU8
tWDFKGwBfI1BfvGnFV7r1CN+wwF77I8d0Yf/6tx64iLYG+OVoGT1764fq+xOp/wu
33BNxGNfW6+tPrHrQp6QHPaC/lTAGVKimGe7usDSomLjDpyZBfU=
=pzDk
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp7/0AUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSU0QhAAhtpaF2R3Dnp2+rNaCBEnqmdEqU8f
LgK48CXz/a97wJi1QIXfVihajkEBrxi1+j01TJNzEQcFuW2UkXoRbn97ZaPathd+
GoOv+da5IU6e1FwctdHCWXff8Y6tkdkYTP7bAC6/n7m146muNt99MSO1Htkb3x5i
0klXsu+fHQQ+EYcUo31secuMJbC1R94JhF1Oz+MOsSygNbe64e6aJJS3XkZ1x1py
2TeP+/AF53AwYtUx1z0zdHP/xLsyIJnsPmt5Jfzbt3UtKTBOP/IAoyvDSjGRa9kb
E7wWnJ7z5GRwZAk4L7kbtrs7nruNSQT8QbHERw87b1uFA2N+gl5k7M+j3pEXdQgo
K63uzCoNPyoIsghgg0f5fXBz28eE2UsG9W4JkNfEGcjJK7cSAX7/68dsY4is/tJs
Rjy+uLRcBCLtcHOgMZQNTSISAqWt1RBdU6AElKviFNR1nw05xCN9jDRB9xEwYNo/
ZEW9hwjAVfjeD/Yrzs8vqBRYZqyD6lgZkGcM5cNUGTClPbrK+QmVQZXhuDH1HT4o
aw1mwFX6FFUrfYKm5nHUWIelh6hETFt2T6L8L3edxRAzC/NYVcrx7KFzTq5387eV
HXy/Y4xSimaaCR32tgkeUyv6ZRd8M/m7G4BW6q4ObJq/mKFYsv5VcQYgpAXHRxa8
mW1136cLsgBTRpk=
=Dxt8
-----END PGP SIGNATURE-----
Merge tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- Fix the incorrect parent number of the 32k clock on Amlogic GXBB
- Add the AO and peripheral clock controllers for the new Amlogic A9 chip
* tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson:
clk: amlogic: Add A9 peripherals clock controller driver
dt-bindings: clock: Add Amlogic A9 peripherals clock controller
clk: amlogic: Add A9 AO clock controller driver
dt-bindings: clock: Add Amlogic A9 AO clock controller
clk: meson: align gxbb_32k_clk_sel number of parents with actual count
This patchset brings the support of the Other Logic Blocks (OLB)
found in the first Mobileye SoC based on the RISC-V architecture, the
EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks
provide similar clock and reset functions to the controllers of the
chip. This series introduces the device tree bindings of the SoC and
the necessary changes to the clock and reset eyeq drivers.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEy6c1E9KFcNpKUem2OLE8WZ9QiKgFAmpZ6HEbFIAAAAAABAAO
bWFudTIsMi41KzEuMTIsMiwyAAoJEDixPFmfUIioZPEP/3m6axQcd5jsnpGnIsjf
mR/5MbWEJFHjs4rxtWD9xeIqu2NEW1rz1lbw4wWr1Tp4KgrtOTFlkt7hRVzW7QV9
BHOMM85Ssaolk50iMSSDhINkBQtWBd4Xg+fVE18ZrZbMW781lnOsp5wlQK81KUy1
BST5QCIuEssJZkI2sDaI1DSf1hQkUPZmIgfA8i+QlQUq16u/e6mu9Y4eR4CWT0gr
VBSiFACjPnucSSVu9vxYvcrrq5QqKsvtsfAUucmI23JmuA65OTUuJLwdHqQod+6n
R99om1zc7z2CQITuTDrSQVO9yGmxpDaAu6jVl4SKTax+KJBVt05CWOle8kyO2Mew
2k+yGb2PgW87HwompCU6y1R7BcuStjxs11dWs9XP75rhzxD8/wluOr1Mah7w7Z/P
mkBoB0KLwtPZsfeEQwFTOWK6ox+joGGAN/7VoGSgQvzbK4rJbfVh+AEa81aV6MxV
J9kMZLC+Y7b/QqM1KG5p57IyVVeY7XWRQe/VPK/Uqvm1B8QwhGRPVI4ihnB+MLkp
WDli4KVlaWmXmS1jT29nVqWxjvCS0AnWe6hNgVIIFg+jwRtMhoQZx8xxRIEVcFai
YvjgX+0eG49f2MKtLssaQ6DyttqSGFMT6OTrMfWw/xM4Y0ehic+1oTz9APUow1WX
0RNW9PRZv9ylFpxAE8XfJ0FR
=w3Sh
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp782EUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSVoWxAAmsUHIZEsHi+O+oKY5WIxBWzKk4d3
WarkDQcYYnL/YCK6N4luG35yVj52hAdrGT5sFERaNgq1dlfKrSvCOO3Tzwn8ZFzf
LMawqnQ5hdPigHQTiU9rj+ET77s9w/dXZ5NRP28+oX3Zs8uNszgrJqDKVuYyC3zJ
fzXJbhrL8W/JK1VSmX3IkEy9bAutX+Ct+CBF4dQfbwiEQZut6KZubPjWS78acu56
VL4hC0I4X/b3z4W8D3yAGPdH9asiUuKyghQTYjUF5xi68V+hTlMxMI2W8daLbdAQ
8chl96p5OARNzukNbM7rGf0SNywmHhWWaQYBNaVtj8gb1FjPv8lLyM1eEDaBrn8H
U3eVobyLtPsy6oAioN+qWU4a8npKqQvHL9Dmn2XyRq3kcLxDy8/8z3tbeAiwVMa4
v51PsPNnogfnefgrTKsPmOsLr+5Cg/d5mnTkqxIQYYYxliCERXquS3IoWB5iPHVD
uMfxpCaFRKqMEEtMmrBFPSPCwdhhHGHQDkKDcfEpCFCjC27BXWorcERruedrVMrZ
NM6TrYEYu69FFpWfpiGYy/ruuS6lRoqpBylH8aczyqNTwuIsUgq3FHhz3qLKD2iY
8eN25pu4C2D3O9FRr1lDEVuwVaH9JRY3Eq7izEUCQWq8pQ4kUf+aJ/3W3RE82bIW
BEdrCQp3pdv3EcU=
=izC9
-----END PGP SIGNATURE-----
Merge tag 'clk-eyeq7h-7.3' of ssh://github.com/benoitmonin/linux into clk-mobileye
Pull Mobileye clk driver updates from Benoît Monin:
- Add support for Mobileye EyeQ7H
This patchset brings the support of the Other Logic Blocks (OLB)
found in the first Mobileye SoC based on the RISC-V architecture, the
EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks
provide similar clock and reset functions to the controllers of the
chip. This series introduces the device tree bindings of the SoC and
the necessary changes to the clock and reset eyeq drivers.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
* tag 'clk-eyeq7h-7.3' of ssh://github.com/benoitmonin/linux:
clk: eyeq: Add EyeQ7H compatibles
clk: eyeq: Drop PLL, dividers, and fixed factors structs
clk: eyeq: Convert clocks declaration to eqc_clock
clk: eyeq: Introduce a generic clock type
clk: eyeq: Prefix the PLL registers with the PLL type
clk: fixed-factor: Export __clk_hw_register_fixed_factor()
clk: fixed-factor: Rework initialization with parent clocks
reset: eyeq: Add EyeQ7H compatibles
dt-bindings: soc: mobileye: Add EyeQ7H OLB
Convert the Texas Instruments OMAP L4 interconnect bus bindings
to DT schema.
During the conversion, several updates were made:
- Defined the compatible property as an array to require
the TI-specific string first, followed by either 'simple-bus' or
'simple-pm-bus'.
- Added a 'select' block to ensure this schema is only
applied to TI-specific nodes, preventing duplicate
schema warnings against the core simple-pm-bus.yaml.
- Added the L4 compatible strings used by the boards but missing from
the text binding, and corrected the 'ti,am3-l4-wkup' typo to
'ti,am33xx-l4-wkup'.
- Made 'reg' and 'reg-names' optional.
Signed-off-by: Eduard Bostina <egbostina@gmail.com>
Link: https://patch.msgid.link/20260810134051.380538-1-egbostina@gmail.com
[robh: move to bindings/bus/]
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Add qcom,glymur-qmp-gen5x8-pcie-phy.yaml as a standalone binding for the
Glymur Gen5 PCIe PHY hardware block. This block supports two link modes,
selected at runtime via a TCSR syscon register:
1. x8 - a single 8-lane PHY instance is exposed
2. x4+x4 - two independent 4-lane PHY instances are exposed
Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml rather
than folding it into the shared compatible list there, since the two PHY
instances active in x8 mode require twice as many clocks, resets, and
power-domains as any other entry in that file, and adding Glymur-specific
properties like qcom,link-mode and reg-names there would only apply to
this one compatible.
Document the required clocks, resets, and power-domains for both PHY
instances, and use #phy-cells = <1>, where the cell value is the PHY
index within the active link mode.
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-1-dd1c7e236e29@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Correct a few white-space issues, like double space after '=' or before
bracket '{' characters, which will be flagged by dt-check-style. No
functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260801195517.235161-2-krzysztof.kozlowski@oss.qualcomm.com
Add device tree binding documentation for the DAPU Telecom DAP8211R(I)
Gigabit Ethernet PHY.
The PHY supports TX and RX clock delays in 150 ps steps from 0 to 2250 ps,
with a default of 1950 ps if not specified.
Signed-off-by: Artem Shimko <a.shimko.dev@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260805085540.452260-3-a.shimko.dev@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Add vendor prefix for Guangdong Dapu Telecom Co., Ltd. [1], a manufacturer
of Ethernet PHYs, networking and other equipment. The prefix will be
used in the DAP8211R(I) Gigabit Ethernet PHY binding.
[1] https://www.dptel.com/
Signed-off-by: Artem Shimko <a.shimko.dev@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260805085540.452260-2-a.shimko.dev@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Add the compatible for the pin controller of the Rockchip RV1106 and
its RV1103 package variant.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Fix the Eliza display clock controller to avoid RCG stall. Revert the
rework of the "PHY mux" clock, as this broke PCIe on several different
targets.
Drop (and correct one) bouncing maintainer email addresses in DeviceTree
bindings.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmpnlToOHGJqb3JuQGty
eW8uc2UACgkQCx85Pw2ZrcWNXg//RN1nAKFwKalihovDtpk6wlkxdUEJl53E1dcU
t5BWTTPWqlSmlc/FWvIqe7EccWRkm/3/rzt1KKaTw6mqupm2pmvtHa/A1dIfzNuw
EMwcFZQssb4m56rS+hO8fvGTxSE8MEd+gl4UXet+neXGvmM7mLu+LotMIH0EbELT
QZetojCYtZQVezkiNy/BKiXLCER/FnuQU0S37cpOR6bEWiS0rzptPKAFX3qgoKZ/
I1ff7iCJ5DJSkIYgAZhFXvMk4V6GGP+HXBp5LnWyzxTt+J5+YER+L5Zmv0po8NFh
NzFxfC9nH+kihD9716FouII64QbwbmKdTc0qS1tLhH9u5OQmhTZEQ283kadpZIdc
nwIglsdmibgFixRDM6sI7CR3aYuFZVbaMCMKWRC9aE7Vxpf0KuRzJnmqxCOwqa1u
5E6+Ps5wb93+mDtYAdx+qRXzLh8ZGUZksoVOE2gC6aZGFkDHEAkQewww6nEQ5ikT
9dZlgnesgMux78Yn1H+PhTFtNXgJXFjWGgBm2YgVXOCvDyXaTF6LE3wlpSIeo9SV
mGAExhPm0OrBmxyN15ynQhVXrn4cKv5sY3rBRKPWtVi3pzWmp1y7KVBf/AL6UONj
c6VmCq1hFBPrV6IUPM8kHJK50Ju+yIrcqS2P6quEaEIT8RKCyunvurwHHjhUz7Ya
uUM7ZxI=
=yj29
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp6GioUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSW9bA//SYbI1Mj6q2gMJyFZEL0Fz8P5pfWI
LAPPAFK+xhTQDl0POkv2/zzRYmXhuQFTD/v2asRmCyu/C9b+GMKVBTuAQWnybSy3
Mp6HjYRrAVpMbZE56lLGkgZXi6a3bZOh9K5m6wdd5frMQt131slBaiiK/U3ZyFKR
TQEIpNsbNa5mx614yCqobEDlGBIO0o4r2Z4iQD05ni2MH+ZYhVUKo+8gisEJledR
GK7ter1b04MCMaxLuW6GAj46DNUhXdXTaEunmgdimjhtSTCy09AulTZO477heQQj
PGXXxjuh7bxY0z8xorbWeqgz1nhr1L/nSDXPxTOyydBJ4FESqEtx8H4SaYiqdqxI
AGNMH7KQPPJTf9nB8lJWFW8tlUi71a/LlQHH8Gu55+N28nkTceQ02dR1eUSue43I
o2g6PMDUayX5SQRyQyEmO4Geusm5yENNHSxL7myDOsw3XIJbt9fjCTdulA50azK2
3QsFkXHy+fBOHxLa2njELKpga/AkUmmmfdj8u3nSe7z60Rjo0ZqUgPd61zO6HTf+
ncDjKlWHnihb7TnEQWyYSLZr9t/BOALDQXS8UFoxaNYu1ReNrV9OqxZFKN/igX77
HzYEmYURM5XeS3I/W8ignbxAXk6VBGvd91tv3By8o7fhlPfPQNCCcOJ9VvhdBkFb
Vrf6zvBdavldz3U=
=RZDP
-----END PGP SIGNATURE-----
Merge tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes
Pull Qualcomm clock driver fixes from Bjorn Andersson:
- Fix the Eliza display clock controller to avoid RCG stall.
Revert the rework of the "PHY mux" clock, as this broke PCIe
on several different targets
- Drop (and correct one) bouncing maintainer email addresses in
Qualcomm clk DeviceTree bindings
* tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
dt-bindings: clock: Replace bouncing emails
Revert "clk: qcom: regmap-phy-mux: Rework the implementation"
clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK
- Initial M3 Pro, Max and Ultra device trees, which are responsible for
the majority of the diffstat. These include CPU cores, interrupt
controller, power state, watchdog, serial pin/gpio controller, i2c and
the boot framebuffer. They are now on par with the base M3 device
trees.
- HWMON sensors for M1/M2
- "pmgr-misc" nodes for M1/2 Pro/Max/Ultra which saves about 1W of power
on these machines. The corresponding driver and dt-binding are part of
the Apple SoC driver changes tag for this cycle.
Signed-off-by: Sven Peter <sven@kernel.org>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQS3vz815OHsEaWy0u9EEX0kKnUe6QUCanYC3AAKCRBEEX0kKnUe
6TjhAP48U0pnqD5rIzUKiXvrsf0kYgbUg4fuvxYTKAfTU2WXvgEApHwB/aS9W+EC
AzBgYldnbJlVg5MhsBqG49l8+B7rPwo=
=odXF
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5/PkACgkQmmx57+YA
GNnWORAAlI7DAtGIPtoHaJNSQGVCyylEPgY23ZpIB6vraFnsBhHDdNY+sBEd1jI1
2M388XJmJ9dAbKf51pAAWiOtmW7TuuKclZWxekAZ37i+LBeL2E4034l/jLAR8ZHJ
P37ogQlOpR7C/YOV2Ro4wQ3qST2OjjANOIYCzCp390ujzqsvBPPVo5U9sF+pVSCQ
vHtXiPFck9CmxQAEfkg8XULhwc7NYLWg2aNtJ9YPmHI7+IGSjJgiXaX6JsZdPJwz
tjCrOtCWJ3RVOT18vdD1TnDBQdrpk1yquGQkk/LMEZhqXAplprKdasqegdIvgUyC
qXGZ62wiWKAg6QRlIQDCOw4Uj7mgjOeay83XgIOA+H4vRYd11SM0cMqaXlfn8DeH
n0Wqt35X0/pNVIEUEIvCmPRdMw+qSAjr4JN005eEoG76Q4Ouaf9xvqvvbtnWWgql
VYV5vSFKbkhhWuJcIwifB7d3eEk321dJHvdwuSpexLlFdM8nVu+1gHHeUn+VHBYC
xXgv9K5ou8qvIeGHXqxFYoj6lvm1jwGijgc51ROHEfPuZmBDhr3Cin2H+I+imv6q
+fc/aAX0MPoTgkdx9W/+qPZql73W+vmhlu0eYGbhSAOmtm68prrdDu6ckOaXVRbF
w8lvAFd7Wa/RBulDZxieMzU/W6Z+FZ3BSBj4H1EqqfHrp7CoaPg=
=azbS
-----END PGP SIGNATURE-----
Merge tag 'apple-soc-dt-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
Apple SoC DTS changes for 7.3
- Initial M3 Pro, Max and Ultra device trees, which are responsible for
the majority of the diffstat. These include CPU cores, interrupt
controller, power state, watchdog, serial pin/gpio controller, i2c and
the boot framebuffer. They are now on par with the base M3 device
trees.
- HWMON sensors for M1/M2
- "pmgr-misc" nodes for M1/2 Pro/Max/Ultra which saves about 1W of power
on these machines. The corresponding driver and dt-binding are part of
the Apple SoC driver changes tag for this cycle.
Signed-off-by: Sven Peter <sven@kernel.org>
* tag 'apple-soc-dt-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: (22 commits)
arm64: dts: apple: Initial T6030 (M3 Pro) device trees
arm64: dts: apple: Initial T603[124] (M3 Max and Ultra) device trees
dt-bindings: pwm: apple,s5l-fpwm: Add t6030 and t6031 compatibles
dt-bindings: i2c: apple,i2c: Add t6030 and t6031 compatibles
dt-bindings: power: apple,pmgr-pwrstate: Add t6030 and t6031 compatibles
dt-bindings: arm: apple: apple,pmgr: Add t6030 and t6031 compatibles
dt-bindings: interrupt-controller: apple,aic2: Add apple,t6031-aic3 compatible
dt-bindings: interrupt-controller: apple,aic2: Invert #interrupt-cells condition
dt-bindings: arm: apple: Add M3 Pro/Max/Ultra devices (T603x)
arm64: dts: apple: t60xx: jxxx: Add device-specific SMC hwmon sensors
arm64: dts: apple: t8112: jxxx: Add device-specific SMC hwmon sensors
arm64: dts: apple: t8103: jxxx: Add device-specific SMC hwmon sensors
arm64: dts: apple: t602x: Add common SMC hwmon sensors
arm64: dts: apple: t600x: Add common SMC hwmon sensors
arm64: dts: apple: t8112: Add common SMC hwmon sensors
arm64: dts: apple: t8103: Add common SMC hwmon sensors
arm64: dts: apple: Add common SMC hwmon infrastructure
arm64: dts: apple: t602x: Add SMC hwmon node
arm64: dts: apple: t600x: Add SMC hwmon node
arm64: dts: apple: t8103: Add SMC hwmon node
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device tree binding documentation for the watchdog timer (WDT)
controller found on Nuvoton MA35D1 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Zi-Yu Chen <zychennvt@gmail.com>
Link: https://lore.kernel.org/r/20260804070351.1846165-2-zychennvt@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add the compatible for the watchdog of the Rockchip RV1106, which is
compatible with the Synopsys DesignWare watchdog.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20260714131856.v2.1.b5339e64b3fe4338b3924ebd9dc0096904699744@changeid
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
NPCM750 and NPCM845 latch watchdog reset indications in the SoC
GCR block rather than in the watchdog block itself.
Add the optional nuvoton,sysgcr phandle so watchdog nodes can
reference the shared GCR reset-status registers that hold those
latched watchdog reset indications.
This is needed by the following reset-status support, which reads
those latches and reports watchdog-caused resets through bootstatus.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260706144828.3517631-2-tmaimon77@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The watchdog on Apple silicon M3 Pro, Max and Ultra SoCs is compatible
with the t8103 (M1) one. Add "apple,t6030-wdt" for M3 Pro and
"apple,t6031-wdt" for M3 Max and Ultra as per-SoC compatibles.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Janne Grunau <j@jannau.net>
Link: https://lore.kernel.org/r/20260715-apple-t603x-initial-devices-v2-6-df65b2485710@jannau.net
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The watchdog on the Apple silicon t8132 (M4) SoC is compatible with the
existing driver. Add "apple,t8132-wdt" as SoC specific compatible under
"apple,t8103-wdt" used by the driver.
The M4 wdt block additionally has a secondary watchdog, which is
disabled by m1n1 and can safely be ignored by Linux.
Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260705-apple-m4-initial-devicetrees-v1-3-e5655ee56523@cyberchaos.dev
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The Analog Devices ADT7470 is a multichannel temperature sensor and
PWM fan controller. It supports monitoring up to 10 external
temperature sensors and controlling up to 4 fans.
Add the device tree binding documentation for it. This includes
support for the thermal framework by defining the "#thermal-sensor-cells"
property, and models the fan control lines as PWM channels by
defining the "#pwm-cells" property.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Link: https://lore.kernel.org/r/20260805-adt7470_thermalzone-v6-1-5605a5f95467@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The MPS MPQ8646 PMBus step-down converter uses the same
mps,vout-fb-divider-ratio-permille property with the same constraints
(maximum 2047, default 706) as the mps,mpq8785, so add its compatible
to the existing schema.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260730-mpq8646_v0-v7-2-e7c7ad768d5d@free.fr
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add compatible strings for variants of MAX20830 which are MAX20830C
and MAX20840C. These devices have the same register functionality with
MAX20830 but with a longer IC_DEVICE_ID.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
Link: https://lore.kernel.org/r/20260730-dev-max20830c-v5-3-a7553f84ee74@analog.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add adi,vout-rfb1-ohms and adi,vout-rfb2-ohms properties to support
external voltage divider configuration for VOUT sensing. When the
desired output voltage is higher than VREF, a resistor divider (RFB1
and RFB2) is required to reach the intended value.
The properties use a dependency constraint to ensure both resistors
are specified together, or neither. This prevents misconfiguration
where only one resistor value is provided.
This patch also adds missing entries in the examples.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
Link: https://lore.kernel.org/r/20260730-dev-max20830c-v5-1-a7553f84ee74@analog.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add device tree binding documentation for the Analog Devices MAX16545 and
MAX16550, and the Volterra VT7505 PMBus controllers.
Signed-off-by: Sanman Pradhan <psanman@juniper.net>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260725211945.288415-2-sanman.pradhan@hpe.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The Kandou KB9002 is an 8-lane PCIe 5.0 retimer exposing an SMBus target
that reports an aggregated die temperature. It needs no device-specific
device tree properties beyond its address, so add it to trivial-devices.
Signed-off-by: Andy Chung <Andy.Chung@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-kb9002-upstream-v5-2-9523c3ffe83a@amd.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reduce the hpe,gxp-fan-ctrl register references from 3 to 1. The
function2 (fn2) and programmable logic (pl) references are removed.
The purpose of removal being their functionality will be consumed by a
new GPIO driver.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230705194544.100370-4-nick.hawkins@hpe.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add a YAML devicetree binding for the Sensirion SHT3x/STS3x sensor
family and the compatible GXCAS GXHT30, with the ALERT interrupt,
nRESET GPIO and VDD supply as optional properties.
The SHT30, SHT31, SHT35 and SHT85 measure humidity and temperature
and differ only in accuracy and packaging, while the STS30, STS31,
STS32 and STS35 are temperature-only parts. Within each group the
parts share the same software interface, so model them with a
fallback to the base part of their group: "sensirion,sht30" for the
SHT parts and "sensirion,sts30" for the STS parts.
The GXCAS GXHT30 is a drop-in replacement for the SHT30 and uses it
as fallback as well.
Signed-off-by: Zaixiang Xu <zaixiang.xu.dev@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260713074559.12196-3-zaixiang.xu.dev@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add device tree binding documentation for ESWIN EIC7700 Voltage and
Temperature sensor.
The EIC7700 SoC integrates two PVT instances for monitoring SoC and DDR
power domains respectively.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Signed-off-by: Huan He <hehuan1@eswincomputing.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Link: https://lore.kernel.org/r/20260630091122.1462-1-dongxuyang@eswincomputing.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Support ROHM BD12780 and BD12780A hot-swap controllers, which are largely
compatible with the Analog Devices adm1278. Main difference between
the BD12780 and the BD12780A is, that the BD12780 has one I2C address
configuration pin more (ADDR3) than the BD12780A.
Introduce own compatibles for both variants but require the BD12780A to
always have the BD12780 as a fall-back.
Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/2b7d5bb8cba773d0bba1d6779f0e6daa6a40eed4.1782458224.git.mazziesaccount@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add support for an optional label property similar to other hwmon devices.
This allows, in case of boards with multiple CHIPCAP2 sensors, to assign
distinct names to each instance.
Signed-off-by: Flaviu Nistor <flaviu.nistor@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260625160423.17882-1-flaviu.nistor@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add a 'ti,current-range' string property to configure the device's Current
Limit (CL) behavior to "high" or "low" via the register, overriding the
physical CL pin setting.
This configuration is supported on LM25066, LM5064, LM5066, and LM5066i.
LM25056 is excluded because it does not support configuring the current
limit via the DEVICE_SETUP register (bit 2 of DEVICE_SETUP is reserved).
The values "low" and "high" map to the respective low/high threshold
voltages of the chips:
- LM25066: low = 25 mV, high = 46 mV
- LM5064, LM5066, LM5066i: low = 26 mV, high = 50 mV
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260615-lm25066-cl-config-v3-1-decb4f5b0b77@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Add devicetree binding documentation for the Silergy SQ24860 eFuse.
The device is a PMBus hardware monitoring device which reports voltage,
current, power, and temperature telemetry. The board-specific IMON
resistor value is described with silergy,rimon-micro-ohms.
Signed-off-by: Ziming Zhu <ziming.zhu@silergycorp.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260612030304.5165-2-zmzhu0630@163.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The INA232 is a current/power monitor from Texas Instruments sharing
the same register map as the other INA2xx.
Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-1-e4375ce652d0@oss.qualcomm.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Sophgo:
The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCanKEvQAKCRCHG95Quc97
dn44AP9HHp2ut8rY0UnmS/s+rCAbWX/2YkhGWdWPPk1o4VkSdQEArt9F9RpXg/Mp
RfmT/LEx81g7zR7wqpGlpy1a5F+TBw4=
=SAg0
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp57JAACgkQmmx57+YA
GNla7xAAqMRFdMgCOH74zaNtohonnSgbmJi4dL6RakzJHCjZO+VWMnxavg/A8qTb
DrSugeW0SV1pe/NbOKaJbqZ6xa/gJJitivPNJIgn8uM3WauetzE55isGPb+smR1r
soqTG/3AYocT88fy7FgLL3GmvY9yd1dAOHA/CFdTpmBdrqfV5fSSmed08wM0lVQe
O1EgjHe7eNk+v3DYo80buRxwljiW0gpbhFFsz84hbdFoL/Cf/GAXWP1xhZjCTKo1
9/Zex3J7SsdNAaZjDzMyF0S0eolyAPJW0SzToDkMniE/tSYc2lkjW7R1I55iuQvi
BJ+kKK1k2/TrSbmvjuvqCEnwfOh9BzXPf4UWuLrUrEVTpdEBtpe0otFGRBqzg0lO
RkgUPdHWR8uhL57Oos8HM4WH2VN4s0jqP0FN1sUp46fnnQFCEi/nO4vRTnOt+ppy
HxNjJyQRrP97OH7s7zpUTyCVVJBZPL3EF3NuNCzioooXK3LHI4MSApTtDIt9bPBi
yS5U1SaUaNm4RwCaFH9QZSQHXdoEXKe0DPX/P9cROr62T6eSyDhZnIIcucveMw+6
tJie38mJChficq8mCo3/S1P3gMELy5lmBw68XCg/UMBcdV76Mq4AgFq6o5Ow+oXp
KS/sO+RkxZPD7ImnGLKrSuurJnIsMpOR/69lLFBkZ0LBtdZY9W4=
=CrHg
-----END PGP SIGNATURE-----
Merge tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v7.3
Sophgo:
The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
* tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux:
riscv: dts: sophgo: Add Milk-V Duo 256M board support
riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
dt-bindings: soc: sophgo: add Milk-V Duo 256M board
riscv64: dts: sophgo: add initial Milk-V Duo S board support
riscv64: dts: sophgo: add SG2000 dtsi
riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Document support for Renesas R-Car X5H Module Controllers, and add
binding definitions for power domains not backed by registers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ulf Hansson <ulfh@kernel.org>
Some Rockchip SoCs, such as the RV1106, give each GPIO bank its own
IO control (IOC) register block rather than grouping the registers of
all banks into a shared GRF region. Add an optional rockchip,grf
property to the gpio-bank binding so that each bank node can reference
the syscon for its own IOC block.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729072727.v3.2.d04a89a3849323a0dcee2c701cba43adbb0523b2@changeid
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
prevent calling it if the thermal zone registration failed (Dan
Carpenter)
- Improve bitfield manipulations on Armada (Bryan B. Lima)
- Remove unneeded 'fast_io' on Sun8i and Armada (Wolfram Sang)
- Fix wrong boundary when clamping the low values in the set_trips()
callback and fix wrong mask when setting the temperature interval on
Airoha (Christian Marangi)
- Make use of the regmap API in order to support the Airoha AN7583
(Christian Marangi)
- Fix adc_tm5_get_temp() return check value on the QCom SPMI ADC
sensor (Rakesh Kota)
- Fix unbalanced clock enablement when the resume fails on the iMX
driver (Can Peng)
- Add Qualcomm Master BandGap thermal monitor support (Satya Priya
Kakitapalli)
- Add Maili Temperature bindings compatible (Haritha S K)
- Add a devm action to clean hardware interrupts, sampling, and
control registers on Spacemit K1 (Pei Xiao)
- Fix trivial typo in an OF code comment (Marek Vasut)
- Remove unecessary print on Qcom SPMI ADC driver when a call to
devm_request_threaded_irq() fails as this one already prints a
message (Jishnu Prakash)
- Add support for QCom PMIC5 Gen3 ADC by using auxialiary driver and
shared interrupt with the IIO driver (Jishnu Prakash)
- Make resets optional on MT8196 and add the corresponding property in
the DT bindings (AngeloGioacchino Del Regno)
- Fix clock staying enabled with the resume operation fails on Qoriq
(Can Peng)
- Fix wrong closing brace position in thermal library header (Andreas
Haufler)
- Fix low and high trip point validation by moving the check after the
clamp on the spacemit driver (surendra)
- Remove redundant error messages on IRQ request failure (Pan Chuang)
-----BEGIN PGP SIGNATURE-----
iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAmp2NLQACgkQqDIjiipP
6E98UAf/SqeabRuCefz1qn4zdjQHL4jiIEHrhRvXLSPb2ooVhzZYpOP5sUXFG1W5
XxncjSyo7ZJKhVXrCd7II7GW6+3TqujM+MWpcYBerGsrLH0YudcOkAl8gTkhSXfV
ZfuKbSYR+mrLyWbszIzbyknaGFFt4xdkusTldhWA80dHb1G5o055/unVtVEDDn65
ciLmZqHBW+r0ureVhu6FJ5FNozCKfX4hXZOsX95FvIJEBvlDORHZmCEsaxbD1bem
mMcs2tU74s2eJtRmKuq7A2ddw23dUTxTUciiCh6r5h/dI0MTxaEZUpF5TjXvfEQE
Ick0gsWEc77263AS/2WAoTodQfBP5A==
=8Vte
-----END PGP SIGNATURE-----
Merge tag 'thermal-v7.3-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
Pull thermal driver updates for 7.3-rc1 from Daniel Lezcano:
"- Move thermal_zone_device_enable() to the right place in order to
prevent calling it if the thermal zone registration failed (Dan
Carpenter)
- Improve bitfield manipulations on Armada (Bryan B. Lima)
- Remove unneeded 'fast_io' on Sun8i and Armada (Wolfram Sang)
- Fix wrong boundary when clamping the low values in the set_trips()
callback and fix wrong mask when setting the temperature interval on
Airoha (Christian Marangi)
- Make use of the regmap API in order to support the Airoha AN7583
(Christian Marangi)
- Fix adc_tm5_get_temp() return check value on the QCom SPMI ADC
sensor (Rakesh Kota)
- Fix unbalanced clock enablement when the resume fails on the iMX
driver (Can Peng)
- Add Qualcomm Master BandGap thermal monitor support (Satya Priya
Kakitapalli)
- Add Maili Temperature bindings compatible (Haritha S K)
- Add a devm action to clean hardware interrupts, sampling, and
control registers on Spacemit K1 (Pei Xiao)
- Fix trivial typo in an OF code comment (Marek Vasut)
- Remove unecessary print on Qcom SPMI ADC driver when a call to
devm_request_threaded_irq() fails as this one already prints a
message (Jishnu Prakash)
- Add support for QCom PMIC5 Gen3 ADC by using auxialiary driver and
shared interrupt with the IIO driver (Jishnu Prakash)
- Make resets optional on MT8196 and add the corresponding property in
the DT bindings (AngeloGioacchino Del Regno)
- Fix clock staying enabled with the resume operation fails on Qoriq
(Can Peng)
- Fix wrong closing brace position in thermal library header (Andreas
Haufler)
- Fix low and high trip point validation by moving the check after the
clamp on the spacemit driver (surendra)
- Remove redundant error messages on IRQ request failure (Pan Chuang)
* tag 'thermal-v7.3-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux: (26 commits)
thermal/drivers: Remove redundant error messages on IRQ request failure
thermal/drivers/spacemit: Validate clamped trip thresholds
tools/lib/thermal: Fix misplaced extern "C" closing brace
thermal/drivers/qoriq: Disable clock on resume failure
thermal/drivers/mediatek/lvts_thermal: Make reset optional for MT8196
dt-bindings: thermal: mediatek: Make resets optional for MT8196
thermal/drivers/qcom: add support for PMIC5 Gen3 ADC thermal monitoring
iio: adc: qcom-spmi-adc5-gen3: Share SDAM0 IRQ with ADC_TM auxiliary driver
iio: adc: qcom-spmi-adc5-gen3: Remove an unnecessary print
thermal/of: Fix trivial enabled typo
thermal/drivers/spacemit/k1: Add shutdown action and reorder registration order
dt-bindings: thermal: qcom-tsens: Document the Maili Temperature Sensor
thermal/drivers/qcom: Add support for Qualcomm MBG thermal monitoring
dt-bindings: thermal: Add Qualcomm MBG thermal monitor support
thermal/drivers/imx: Disable clock on runtime resume failure
thermal/drivers/qcom-spmi-adc-tm5: Drop IIO_VAL_INT check in adc_tm5_get_temp
thermal/drivers/airoha: Add support for AN7583 Thermal Sensor
dt-bindings: arm: airoha: Add the chip-scu node for AN7583 SoC
thermal/drivers/airoha: Generalize get_thermal_ADC and set_mux function
thermal/drivers/airoha: Generalize probe function
...
Document the compatible string for inline crypto engine found
on the Qualcomm X1E80100 SoC, used by the Hamoa IoT EVK board.
Signed-off-by: Wenjia Zhang <wenjia.zhang@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Freescale QUICC Engine:
- Use generic I/O helpers in interrupt controller for IO Ports
- Move CONFIG_QE_GPIO out of powerpc
- Fix DT scan for GPIO nodes
- Convert IO ports interrupt controller to generic IRQ chip
- Add support of IRQs in GPIO controller
- Implement get_direction() in GPIO controller
- Check platform_driver_register() in interrupt controller for IO Ports
Data Path I/O:
- Replace maintainer
- Remove redundant dev_err()
- Fix kernel-doc typos
Freescale Management Complex:
- Use strscpy() to copy strings into arrays
- Remove redundant dev_err()
- Drop unused assignment of acpi_device_id::driver_data
Other changes:
- Add kernel and device tree binding support for RCW override,
completing the SerDes PHY driver functionality
- Fix kernel-doc warnings and typos in DPAA header
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTH/wu6mIr0ZW+Vui/dkHAmvKvPUwUCanjJsQAKCRDdkHAmvKvP
UwszAQDD8kadgq4T9kUl7LO9TzCfPbG39oyjY5b1xrtEmqPa2QEA55gxY7ker9KC
GXDq12bKiI79q1C5acQOvvGtRzn50g4=
=gVuJ
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5jCwACgkQmmx57+YA
GNnQ1RAAoXeSmgQv7IV9lh9gxm/L5HaIHy8VZhOH++dWgNT7o4imnhg1v1Lf9wT9
cvIA17WlkcTDvF7yPpsli8BKpb3ohWlmiliuvkJBtFXMOawToOPA1JaMo3bwWdtV
UDqHJGvaQ3fY0nfJZHUn3F6m43X0fpl1X7jqMwRu0n59G9grSN0a1JzH5fcvhzLc
R3MZX8Xf0MkB7NnilSm6p9+NR7awFFOt+2F1MIaVJrTBCQsLQ7TZJ2PXznMGUqlZ
E/eubTe4l3H3Tvf9Ymeoqn+eD9DaV4/thqtWkZieRuQ7sRKgpLLjLVIMmEy4C50B
fVQBhRj3puj67qwxGbgfuQ0rO80e7Enx4rx4FP2wOEyz1srKMr5gaTAQfan8shW1
CZEAbx8OniBfFuLdOHueOjwyONYA2KWfvFcfhEaR1QXU5EFteUwOXKKQsA7A7j3i
9RhPkXukIoU/BG59ZspR9s5cegh4C54ATsrxkgnW2tCMSHPN27Zfn+UnTDQ0MGYj
PIlrftuqcFWUjgjn7vdASwVEsyoPr1/c79GwmW6/8Wna3rZsJEKwEX47FDNxan96
/cF244Ljrg6e3SRVhuyCNqGgbCi/v6TMe3L5niKoDBLnpQh+WU9HRFTWUPJ/bOBz
8CxrN1kZa2oZU8IhZSMI1O9T8Y77yPElt8wEIetpxJ+DKK5fPpw=
=76G2
-----END PGP SIGNATURE-----
Merge tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux into soc/drivers
FSL SOC Changes for 7.3
Freescale QUICC Engine:
- Use generic I/O helpers in interrupt controller for IO Ports
- Move CONFIG_QE_GPIO out of powerpc
- Fix DT scan for GPIO nodes
- Convert IO ports interrupt controller to generic IRQ chip
- Add support of IRQs in GPIO controller
- Implement get_direction() in GPIO controller
- Check platform_driver_register() in interrupt controller for IO Ports
Data Path I/O:
- Replace maintainer
- Remove redundant dev_err()
- Fix kernel-doc typos
Freescale Management Complex:
- Use strscpy() to copy strings into arrays
- Remove redundant dev_err()
- Drop unused assignment of acpi_device_id::driver_data
Other changes:
- Add kernel and device tree binding support for RCW override,
completing the SerDes PHY driver functionality
- Fix kernel-doc warnings and typos in DPAA header
* tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux: (31 commits)
bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data
soc: fsl: qe: check platform_driver_register() in qe_ic_of_init()
phy: lynx-10g: use RCW override procedure for dynamic protocol change
soc: fsl: guts: implement the RCW override procedure
dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
soc: fsl: guts: make fsl_soc_data available after fsl_guts_init()
soc: fsl: guts: make it easier to determine on which SoC we are running
soc: fsl: guts: add a central fsl_guts_read() function
soc: fsl: guts: add a global structure to hold state
soc: fsl: guts: use a macro to encode the DCFG CCSR space
soc: fsl: guts: perform fsl_guts_init() error teardown in reverse order of setup
soc: fsl: dpio: fix kernel-doc typos
soc: fsl: fix kernel-doc warnings and typos
bus: fsl-mc: Remove redundant dev_err()
soc: fsl: qe: Add support of IRQs in QE GPIO
soc: fsl: qe: Rename irq variable to parent_irq
soc: fsl: qe: Convert to generic IRQ chip
soc: fsl: qe: Handle spurious interrupts
soc: fsl: qe: Iterate over all pending interrupts in cascade handler
soc: fsl: qe: Use generic_handle_domain_irq()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New driver and dt-bindings for Apple PMGR misc controls, which tweaks
various global power related states and saves about 1W of power on M1
Pro/Max/Ultra during s2idle.
- A small fix for device links in SART
Signed-off-by: Sven Peter <sven@kernel.org>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQS3vz815OHsEaWy0u9EEX0kKnUe6QUCanYDQgAKCRBEEX0kKnUe
6ZuoAP98l5DFnC+mM8Hb58BKTNi0Aj4x+ZS6wUQQyEWGM/x9wAEAg4qGNtuaecIi
fZDfSWHUSZ4/mpf7q9OwAtbpbvn3Jw0=
=dNHf
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5hmEACgkQmmx57+YA
GNnDiw//bh8x/MOhIM9wObUEZLdO9vLMCI3jnnxeZ7T5FQDKBAnkK3IV0yPo+IJg
T2ypxkDkKYvlaN2nOXHIgH96N/K0YQwZMzea9M/ohIU6ftDdKm1YuOjfzAQaRjna
uFsY90TUncG/956YY+iamGom+sUFwlGx64zniYL5WXEfQ80wHGhwNCtz1lmrX/ng
9wSBAzPMy8mZ9GUEbq5z6R2Dz7zs/9vRosOkhPAO2EnFKWEsviiVz7RT0w6pIZ6s
VPtCTsC8re2Uu+UkqM/jg8xoH06Wb39HCHWLL655U34P6Bob0CCeYFmOK/Y9+9fC
ndVlEGx30sRmNqcGjwDGEkn4tysnyu3A7ahZCRHPUFJgkEn1LOjFBX/+mPwFDjIV
6DExTuDbdroOI4F4CEJa+knNF5jOiX4IgnUFq1AjF5au4ZT4kEHboQmK67NVD2iJ
A7aZqn0OR3da0+Bxa+BLGJd+ZB1mGoRQbf64I7mYRJsCO5iEGM5wuFPKmOZOfy7f
9J2l0lj7Yiw+WD2AnVrwApYVEpZBWvCNjCHpA1ctcgwqafY4psEkoJLt7pIcVaPa
zTEh/kRb6LtK4F6m13s9QaWMgoWsoa9TYUou2Aeof2X4Uyg8qNMPMalRnIDB16gf
eF/x9PBxRJ8JMDABzuR8TBcac+5ZZfjOuWMWMrvnAs57AqdO5C4=
=KWIH
-----END PGP SIGNATURE-----
Merge tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/drivers
Apple Soc driver updates for 7.3
- New driver and dt-bindings for Apple PMGR misc controls, which tweaks
various global power related states and saves about 1W of power on M1
Pro/Max/Ultra during s2idle.
- A small fix for device links in SART
Signed-off-by: Sven Peter <sven@kernel.org>
* tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux:
soc: apple: Add driver for Apple PMGR misc controls
dt-bindings: soc: apple: Add Apple PMGR misc controls
soc: apple: sart: require device link for consumers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add SMEM parsing for DDR configuration data and use its highest bank
address bit to select the appropriate UBWC configuration.
Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers.
Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler
NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16.
Correct GENI firmware-size validation using the hardware CFG RAM depth and
correct the PMIC GLINK Thunderbolt extradata layout.
Document the Nord AOSS side channel and the IMEM minidump SRAM property.
Clean up Qualcomm statistics macros and the WCNSS binding schema.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmp1/J8OHGJqb3JuQGty
eW8uc2UACgkQCx85Pw2ZrcXcZQ/9G3XLVoPBw7j1dyAfdDs1x16kZBoHxexXbPLQ
RgNZHrcz2voh4pXOF21nf5Pv9eC+i4rZU0PzIBJBzHiW/0C+QMegOzx70upIgoBM
V2Xsw/eqhfcPMl0xz/6LCYijGe1UXcdl1qD+blbe4qql+BFsZdG5skmqpEA2M6ZH
DiD9II5hW/XNAZOFRkV64nV+oaX3nlU9HyusPIebL5YV8ZHjBis/QQpbObLHNUQy
kL7UACS86U2PoR+womdoBcESArrEEpJzdezWwxjAS8nsOFoPUjzRaYxdlODm4rad
xw+fB/loedU8yLfZpcE0GdEE6qwrwt4tda3X3ZeSfOuYqq+XiRA33CeRwCDb+XNK
DlOpA3bRNTY8d3LZ+Worg329kRPB86fmvYTxsvurJ7/LTVSl1ZHotL0rdFOcL8BD
sR3FIRXSPt/RUE0QY7Xq38BahsgWAjKt2TFNrtq2PJdQES2kYLXpx8+xAzFWeg//
TxkM8UtA5dmt19svsAtELHyTGm8lWFBtbZSyHDbdGhDH6Wvf0PHNcsqY5lYIvwn+
5+bpT00Os2KdlgaBvWzUxM+FoWJ1QH9hYjEJZRFdcWmtbnNRABBLcyyGgtAOffot
mVjRrrRkgSBn+94eZTmqC25RPwZbkd1hog9ym5JUa2RLYfgsKDHW6rb1p/+Qp601
diAdn9s=
=hi1p
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5hSsACgkQmmx57+YA
GNk9Lw//d58iG3MEb2ttm1MTuUv1S5f3kaleALzaGJh7mXk7MrtdYd+nVEKsXJ4m
tmBQW2TmrjUdj36YkIhkyuiX0iE2Y6Gje+pm1v7axbqWGJ3Kr48Ytrc/QrlCS6Ji
nHz4aZx7Lm6HYiGkl9QVajkP3w/FDnlk+awLc0kN/0BqzEkyPKrJYTePz7FHnfhy
kRmpzMBZY05MG3MxxJU57bJHWntmKL4rCSpTUdVMP28lb8lIRLbrK7IEIoCR+Css
bciH++o8pBFrJv3ryexMlUmR5Ua38BjuoDXeK17PwqoB2My8CJUJAf8+dKVWGJ9h
efpSGJKfUjpDTUJKqKESx11jb900DPpFg773JwtJCRTP+7TZU1iv/6KxyfNgz6Qx
LGNUEehZ6nYRUo91v5FX4jBaafEHqpl/PLUQIPqvaCcYTQ1pw+TZKBhA/EZJucuv
RrE9fLt1ivn7+YaJSrEavzsPzMiXHs+Y61zbb1OEIGAg07uu9GUTjhaI+DfUIDNf
VT5v8Y4TopL8NEHsSekaJ4Zu4gGe/gOreZWlxDBtbtMWB7T4KmgRPJhAmrp40bQq
B6LcmsDw80YCa46MRbF9PnvM7YEOdZox4Riw8V5IcdHd2IjwfMGPD75TY56mMlIC
u0LBNKuaOtG+Y9m7TeJ/W8kElAib71dh4wZb5xmqrZcVLmRgtxo=
=TIvW
-----END PGP SIGNATURE-----
Merge tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
More Qualcomm driver updates for v7.3
Add SMEM parsing for DDR configuration data and use its highest bank
address bit to select the appropriate UBWC configuration.
Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers.
Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler
NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16.
Correct GENI firmware-size validation using the hardware CFG RAM depth and
correct the PMIC GLINK Thunderbolt extradata layout.
Document the Nord AOSS side channel and the IMEM minidump SRAM property.
Clean up Qualcomm statistics macros and the WCNSS binding schema.
* tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
media: qcom: Switch to generic PAS TZ APIs
dt-bindings: soc: qcom,aoss-qmp: Document Nord AOSS side channel
dt-bindings: sram: qcom,imem: Add minidump-sram pattern property
soc: qcom: qcom_stats: Replace CLIENT_VOTES_OFFSET macro with sizeof()
soc: qcom: qcom_stats: Remove unused macro definitions
soc: qcom: ubwc: Get HBB from SMEM
soc: qcom: smem: Expose DDR data from SMEM
soc: qcom: smem: Use 'unsigned int' instead of 'unsigned'
firmware: qcom: scm: Fix tzmem state on probe retry
firmware: qcom: scm: Fix reserved memory cleanup on probe failure
firmware: qcom: scm: Fix NULL dereference in IRQ handler before __scm is published
firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A16 (UX3607OA)
soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware size
soc: qcom: pmic_glink_altmode: Define the TBT extradata properly
dt-bindings: soc: qcom,wcnss: Drop redundant $ref of firmware-name property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a new device tree for the Lenove ThinkEdge SE70 Edge
Client device as well as a number of fixes and cleanups for Tegra234 and
Tegra194. Tegra264 sees a number of additions to enable more features.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmpvcb8ACgkQ3SOs138+
s6EVRg//e3keeg7ehCUFVA8mDnGfxtIR5ErkU0I5LkCaQucREvHveHuNSayiNSM0
DQVcqv3n/egea4Nnon+eH4ddpa0fosFUm0tW1agLdvhn41nKhiTg/vNcPUwqNE+p
qw43rl5ecChZslW8l8+4eln9sRoTnxBKKlydu5aKKVQtpLbn23uZTwtlSwMWcduO
0GjNOpvrjNyLWzGQ6lrO7uxRxrTHJPYm68Y/sVt38tZYHKC/Ksosy1/o0fKwJd4Q
kMfk2lu1DxY6LGihNmNgpoITva0EaxtwDN1I4IO+dWLNq+feOrwCdTIaanycQPSw
29COUfEcpblWvkRxd6ffWLwsAEk1ydR49FaJLgaAddb0ImEJfEeiaz8roAMqW24Q
QEEDtSwg8JeC4dhWSgOqPOin328hiz3gEG3qYkP/Bi9NgCq2a0eVRlWfBOkgPI8u
isGcVm1yfb2cxdgC26QWivLtuTxDNeHp/rcyGAinWrzd5FJFMvd/tn76inOS33X1
U4shiIvnYDMh0j1VkvHa2ZvN1lqOTmbAGqHOF0iuCC2fhHuu6VW3/7j7wYgtv4gP
Mp2dfVWEdj1Yp+iedS63XN+rFnEqMqw2733TkI1ThLzF3PXz0BO73QMvY+qAujlV
8eLPr5091lXQKYCKCLx8AGBpLtXOFHzS1BxR/tr+OPWAutGFoXA=
=qSTk
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-7.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v7.3-rc1
This contains a new device tree for the Lenove ThinkEdge SE70 Edge
Client device as well as a number of fixes and cleanups for Tegra234 and
Tegra194. Tegra264 sees a number of additions to enable more features.
* tag 'tegra-for-7.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (1469 commits)
arm64: tegra: Correct Tegra234 p3740 interrupt flags
arm64: tegra: Correct Tegra234 p3737 interrupt flags
arm64: tegra: Correct Tegra194 p2972 interrupt flags
arm64: tegra: Drop CPU masks from GICv3 PPI interrupts
arm64: tegra: Add Lenovo ThinkEdge SE70 device tree
arm64: tegra: Add pinctrl nodes for Tegra264
arm64: tegra: Fix CMDQV interrupt type on Tegra264
arm64: tegra: Properly sort devices on Tegra264
arm64: tegra: Add GTE nodes for Tegra264
arm64: tegra: Add Host1x and VIC on Tegra264
arm64: tegra: Populate CPU and L2 cache nodes on Tegra264
arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map
Linux 7.2-rc5
super: fix emergency thaw deadlock on frozen block devices
tracing: perf: Fix stale head for perf syscall tracing
ftrace: Add global mutex to serialize trace_parser access
tracing: Delay module ref count for "enable_event" trigger
tracing: Fix use-after-free freeing trigger private data
bpf, sockmap: Fix cork use-after-free in tcp_bpf_sendmsg()
tracing: Fix context switch counter truncation
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This contains a few fixes for interrupt types and email addresses as
well as the addition of a compatible string for the Lenovo ThinkEdge
SE70 Edge Client.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmpvcBUACgkQ3SOs138+
s6FsAg/+MbBZhYQm08PBRJAvwOuC+3Uny4nBxPDheAyqYmi0pa7a6Az36k1ub5B2
UgXrk32x+yfhGvmSkg/bKsiSvKo9SjKz0hUY4hWOMCeursbNDdv2BcYxLwx291wu
KETB3obUsGRhn3yqcQA6b/8iJOBluDDpdkZh85AT++Ss+akspCt4LeCQnXDxdtK3
aEG0lb8Q63TC0uW0a0Qg5+xh9HH7hNZN8S0giWP0OCi0+V9JNyPWEfVAFdqLaQbH
bcv1udPTKYhvXemNumerMzNXtxPJTBlOTJwugyCgv7rMGRsntk54UTDqc4w6yRen
T9Zf3v9ScMQ+OXpdhicdFffeNC2tky9fruTE8Vjs7Oeif2AtaqYI8wMndyMKvQl5
h4Q1uwAJeX2Wjj+5DxLQ/ets4OGb0GvXw8xdELfQ1R35YKd97eHMXqpgdwFtb5PW
UecGlSly515zL43a7z/ROF33aG4Cbr3DZJANRNfqlo5oDuHWyS53q+jNklq0nhid
t29eMhaB9sh8NGOgs4hHY67vMwvYHDDAUDSp66AcQFVuPkJdf8Mrw8MSaXhcqqW+
Tkn2w/ilrYTn7ZXr1CPqmSHezlr77ky/cmusBoSp2NX1LVCQPkonQAOrj1Pzd6mI
vTGy7U6zj6dbXw1yZTAtBzzBJY6WwTxHsKAxW98uvr7kupbC89Y=
=q7gO
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-7.3-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v7.3-rc1
This contains a few fixes for interrupt types and email addresses as
well as the addition of a compatible string for the Lenovo ThinkEdge
SE70 Edge Client.
* tag 'tegra-for-7.3-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string
dt-bindings: gpu: host1x: Fix email address
dt-bindings: iommu: Fix interrupt type in example
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmpupawbFIAAAAAABAAO
bWFudTIsMi41KzEuMTIsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z
Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz
REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtuDgP/0+IIPDo/U7U0IhT+dAx
Mxr1fWX1M4h5nEmirD8Zsx8TSfvZrpZr5MvazjrHxZ5U2U4ntkqrcoByhIqEy6Dn
wz3A8arOEe3BU1zXf4UAPAW0CZA3Bp9rEDgwbgsTfyelSLyeDqaMX8l/8XQLU8Sl
f28L5p+5AQota4Cutl36yE/KP6cK+7SBSgXA2Rnb9SXzvwC9cQGuOUq71zUsS7jI
FdpYcvyCbLFmUiq2XoeFAdGB04nYs28VWiFnHg7FNdrCqWH6pgi/zxd3QtlTxjd6
oIrp/NsBnx9WAyx9GDhckpqOLt+sA49BjMTArBHmytVBI0ku2kbueQXJIS2J2OEq
Cj4jkMD36Mbk21UP/3OOohARxPYWDDsRQ6NzvAMqNnmFdGa2lTCGA2pBsXF6pzYA
cgFoSQq3s37ArNWaFxeCgnAnzyUWtEUEA3wcp+04xh4s9a90khxuU/rpF+GuyZwp
5Bfppy9L9dI6BogmfAcMsVHcLd0UhDoC6nokx8QLCtrVKEnpvWHfAtWProzEINfX
k9K+f+fLtvL4aWGevKfZZfbMwFRrDaARI03HqW/flUjLBVggoC2FFo63WOfEmvZr
ldCmIWM2iDgr7gBTSy8FSX+3FNROyc2xDFhM189crVvK0+LCCMyqGhHFNnk6NYbU
NRf7S+rwIN9yrBSUgrX6GCXs
=WKqT
-----END PGP SIGNATURE-----
Merge tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into soc/dt
RISC-V SpacemiT DT changes for 7.3
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
* tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: (33 commits)
riscv: dts: spacemit: Add cpu scaling for Milk-V Jupiter
riscv: dts: spacemit: k1-bananapi-cm6: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-r2s: fix maximum CPU core voltage
riscv: dts: spacemit: k1-musepi-pro: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-rv2: fix maximum CPU core voltage
riscv: dts: spacemit: k1-milkv-jupiter: fix maximum CPU core voltage
riscv: dts: spacemit: k1-bananapi-f3: fix maximum CPU core voltage
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 com260 board
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 pico-itx board
riscv: dts: spacemit: k3: add i2s0-i2s5 nodes
riscv: dts: spacemit: k3: add USB controller and USB phy support
riscv: dts: spacemit: enable PCIe on OrangePi R2S
riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1
riscv: dts: spacemit: k3-com260: add eeprom on i2c2
riscv: dts: spacemit: add SPI controllers for K3
riscv: dts: spacemit: add K3 PDMA request numbers
riscv: dts: spacemit: Fix phy id check for the phy on com260 board
riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board
riscv: dts: spacemit: Add enough deassert time for the PHY on com260 board
riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Orange Pi 5 Pro, Vicharak Axon, Vicharak Vaaman2, Youyeetoo YY3588
New peripherals: eDP support on RK3576
And of course a number of board-fixes, style-fixes and some newly
enabled board-components.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmptHIQQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgc0AB/9BaMz8DtfWjjLRIQTBoIHDCeflNPO/deS0
Gea4KkofOsLapsflB4WvVs9HAxJfX43LE4xFFqQn947wiFVDA7xV9Z1T9V3DkxiE
5GnvrjYbfDGBtYeAJZmYm3Lq2AA7HeIVAQhgOXEow+6MH5GmG3SRWg8aBplNQC0K
pPvLc+AdFyQCLlVVf12iVOeViIZejIEXYGDuofa8euTEUjZxNSlqvxfX/YF5uE2K
1ycQX6MwNLA7x1Gx4GXCytgt+oKTtl42NAQLeIHYwJyinnMd2JY8RrDQBBozENZf
YQVWUE53W7W/9OWsLptfjLN5Jya9iMVxMXcsGRvtNe44SyyGnCT3
=0Vz9
-----END PGP SIGNATURE-----
Merge tag 'v7.3-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: Graperain G3568, HINLINK H28K, LCKFB Taishan Pi 3M,
Orange Pi 5 Pro, Vicharak Axon, Vicharak Vaaman2, Youyeetoo YY3588
New peripherals: eDP support on RK3576
And of course a number of board-fixes, style-fixes and some newly
enabled board-components.
* tag 'v7.3-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (39 commits)
arm64: dts: rockchip: Fix rk3566-bigtreetech-cb2 touchscreen property
arm64: dts: rockchip: fix label of sys_led for nanopi-r4s
arm64: dts: rockchip: Fix the rk3566-radxa-cm3 Wifi compatible
arm64: dts: rockchip: Fix Gru WLAN sideband interrupt
arm64: dts: rockchip: Add Vicharak Vaaman2 board
dt-bindings: arm: rockchip: Add Vicharak Vaaman2
arm64: dts: rockchip: add Vicharak Axon board
dt-bindings: arm: rockchip: add Vicharak Axon board
arm64: dts: rockchip: Add LCKFB Taishan Pi 3M
dt-bindings: arm: rockchip: Add LCKFB Taishan Pi 3M
arm64: dts: rockchip: Add Orange Pi 5 Pro board support
arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro
arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5
dt-bindings: arm: rockchip: Add Orange Pi 5 Pro
arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2
dt-bindings: arm: rockchip: Add Graperain G3568 series
dt-bindings: vendor-prefixes: Add graperain
Revert "arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro"
arm64: dts: rockchip: fix HDMI-RX signal detect GPIO on yy3588
arm64: dts: rockchip: Enable USB device mode on rk3588s-roc-pc
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.
Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.
Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.
Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.
Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmprfucOHGJqb3JuQGty
eW8uc2UACgkQCx85Pw2ZrcVSexAAkUYQzdf+LbI2LXMUwhASxt0BcCGFUMnBzi1G
B6QXIP/3H6ucb/QXhYAfghuSrd6SPWCmCueS+FiMJst+eEiuvSDPkPiGyMAWs3kM
fuQbxSWc1VcAgVCbjABrCHSptmJRU+poRent3raLqgCQJ3oip78mnn3p3SEcv4rg
HK4TyjF5EWjzZo6sQWYuS6F3zAeu5Az5ft83Qjd/87PnFYl3A5Y8ZJMleT1o9yi0
eqwBh2XlyMHVZB83Bm6kIRfDFQ+q6CjB/CNCjrjfdXQeKbkYNMnEF3NywIDckPDC
L6O1kTuld3L25koRRfMeHq8bWpOTEWLq4UCqvpEVpj352eZPAgFYfd0zudVhjLQP
CPmoq+5quRbltq7VxO2x7LWz6vzgrrRevC9n3Eyj6uBioCo+JpcMTns/zDGDrzm/
dl43YwGcOI0+U3m3GXJ9567T9zIEA8CzuOd3tHcmTxGmxMU2y313cwfHqgbqy6K6
NLzToYYPclB6aC44yqBPjOhkP653atqDc6qhhMCix7swoTEUqs780fH/G7X6ammY
9XgUM/pxB3dB37dqy8fBBha0TdQ6dQm25DAN2TULgKcolFzHo+O2vd4jR4KpU2eg
3L+pdMUZgF0bvrlqpR9Q8z2TYpIkL/Z5Tc/eEdI6WWF9YXF0TV+iI/7U6S/a+ZJi
gfrBpeo=
=ZLfL
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v7.3
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.
Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.
Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.
Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.
Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
* tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (244 commits)
arm64: dts: qcom: eliza: Describe the ADSP GPR node
arm64: dts: qcom: eliza-evk: Add support for USB and SD card
dt-bindings: arm: qcom-soc: Allow WSA88xx speaker compatible
dt-bindings: arm: qcom-soc: Validate nodes with fallbacks
dt-bindings: arm: qcom-soc: Document more of existing legacy style compatibles
dt-bindings: arm: qcom-soc: Include Eliza, Kaanapali and others in SoC names
arm64: dts: qcom: eliza: Enable cpufreq cooling devices
arm64: dts: qcom: glymur: add SoCCP DT node
arm64: dts: qcom: glymur: fix SoCCP memory mappings
arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR
arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
arm64: dts: qcom: glymur: Add CX power domain to GCC
arm64: dts: qcom: glymur: Drop fake PCIe phy 3B
arm64: dts: qcom: glymur: add TRNG node
arm64: dts: qcom: glymur: enable ETR and CTCU devices
arm64: dts: qcom: glymur: Add PCIe port compatibles and ports
arm64: dts: qcom: smb2370: Disable SMB2370_2 by default
arm64: dts: qcom: eliza-mtp: Enable touchscreen
arm64: dts: qcom: purwa-iot-som: enable video
arm64: dts: qcom: purwa: Override Iris clocks and operating points
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
UAPI Changes:
- Remove the default udmabuf size limit of 64MB.
Cross-subsystem Changes:
- Add dmemcg support for eviction, and hook it up for amdgpu and xe.
Core Changes:
- Changes to TTM to be more aggressive when allocating below protection limit!
- Improve dt binding documentation for renesas.
- Add helper to convert physical address back to buddy block,
add that to and improve its kunit test.
Driver Changes:
- Assorted small fixes to ti-sn65dsi86, panthor, imagination, omapdrm,
bridge/synopsys, panel-edp, ssd130x, panel/tdo-tl070wsh30.
- Add Sharp LQ120P1JX51 panel.
- Add dmemcg support to nouveau.
- Various updates and improvements to sun4i, among which YUV and 4k support.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEuXvWqAysSYEJGuVH/lWMcqZwE8MFAmp1AMkACgkQ/lWMcqZw
E8PASxAApPBUp2ArpFt9+gE33YWRb7sqn42AqCbQfbNgL7IZ4u0TkpnY/4SYyhkf
/6ksiS9UReSdtm+1sVEJQuwN7p8ujvfiugvU3uD6EdUxyNeE4u1CHCUex97HeNxn
JXdGJPoY6Mci6gC2fYU4xknGOH/sMlY+sDZ/cXSylVKt0/qJQ/HpiALnrwW+G2nm
p+wj57fp+gB4T9a0ojJ9WldFdR4e2/ilgj5f+ywGza2XZdegi/f/t+H+EVN+MRfx
OyhTO2LepvlYZo2ZEeFlX49dIEquLwEpva2apQE5YsYn/dB2GYtTnI3MGw/eqMFV
e1U4oK88cQQEKtQsBKYYUwuU3rNrFFJUAa0mlj168KHid+7kQHBCj8oSux8mSU7C
aoK8oK/puflJl+vPP/4FMmGuqEl7CvLkiB5xAyE8BJSM4F1fKfm+72SIRFbAnS5X
l5OWsjvXGmZFU4dwiNElh2OGi3COOyp4nc0BvJZh64p5+4Drj2eslCo9uZrOEKqZ
Pnuu/j9NnajvRNl6cwWa5DQ2nNn0jdwQjGYSvaiYwy5NFZLSAK4cKakm8ZPsjJS3
K1sHlAhKKcJzRdBB/iZTNFBwOq3l0+rFCWfMqeb4SGev8nsQaX4iFVOFU77MabAG
0W7+hGIr+76C6MX1rJJR9+GvSnNYYNti+4HdGmio3w+rlC19qHA=
=pXJR
-----END PGP SIGNATURE-----
Merge tag 'drm-misc-next-2026-08-06' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v7.3:
UAPI Changes:
- Remove the default udmabuf size limit of 64MB.
Cross-subsystem Changes:
- Add dmemcg support for eviction, and hook it up for amdgpu and xe.
Core Changes:
- Changes to TTM to be more aggressive when allocating below protection limit!
- Improve dt binding documentation for renesas.
- Add helper to convert physical address back to buddy block,
add that to and improve its kunit test.
Driver Changes:
- Assorted small fixes to ti-sn65dsi86, panthor, imagination, omapdrm,
bridge/synopsys, panel-edp, ssd130x, panel/tdo-tl070wsh30.
- Add Sharp LQ120P1JX51 panel.
- Add dmemcg support to nouveau.
- Various updates and improvements to sun4i, among which YUV and 4k support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patch.msgid.link/917d462a-8976-4a15-bec4-4513ec51c5c0@linux.intel.com
Add the S[m|s]csrind ISA extension description.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
[pjw@kernel.org: use official extension names in the patch description]
Link: https://patch.msgid.link/20260807-counter_delegation-v9-4-58658104e487@meta.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Some AN7583 pins have non-gpio default settings. This patch provides a way
to configure such pins as GPIO or PWM. Also add gpio-range property in the
dts example.
Please note that gpio52 pin can't be configured as PWM pin.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
In the an7581 case
* gpio47 and pcie_reset0 shares the same pin,
* gpio48 and pcie_reset1 shares the same pin,
* gpio49 and pcie_reset2 shares the same pin.
Let's define a way to configure these pins as gpio or pwm.
Also add gpio-range property in the dts example.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Linus Walleij <linusw@kernel.org>
An7583 device tree binding schema was more or less blinly copied from
corresponding en7581 schema. As result it's not correct.
There are following issues:
* i2s pin-function is not really defined for an7583
* i2s pin-function by mistake was replaced by i2c pin-function in the
functions/groups checks
* pcm_spi pin-function defined for less number of pin-groups
* pwm pin-function should have more pin-groups elements
* unexisting pins was defined
Fix an7583 schema, so it matches actual pinctrl driver.
Fixes: e6e47d31d3 ("dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Due to misprint i2s pin-function is missed, instead i2c pin-function defined
twice. The second of them operates with i2s pin-group.
Let's fix the typo so that the i2s function is defined correctly.
Fixes: d0c15cb96b ("dt-bindings: pinctrl: airoha: Add EN7581 pinctrl")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Both LVTS-AP and LVTS-MCU may be shared with SoC-internal MCUs
running some sort of firmware that checks thermals in order to
scale frequency, or to take action for critical SoC thermal
protection - and this is seen on most MT8196 boards.
Make resets optional, as doing a HW reset on such boards will
result in either an immediate thermal protect shutdown or in
a rather important and usually permanent system slowdown.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://patch.msgid.link/20260721105230.101906-2-angelogioacchino.delregno@collabora.com
Add bindings for the Qualcomm MBG (Master Bandgap) temperature alarm
peripheral found on the PM8775 PMIC. Unlike the existing SPMI temp alarm
peripheral, the MBG peripheral supports both hot and cold threshold
monitoring across two programmable levels (LVL1 and LVL2), with interrupt
status reported via a fault status register over SPMI.
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Co-developed-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
Signed-off-by: Sachin Gupta <sachin.gupta@oss.qualcomm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260722-spmi-mbg-driver-v3-1-ef73064f2789@oss.qualcomm.com
The A733 NMI controller is compatible with the A523 one. Add an
A733-specific compatible string, with the A523 as fallback.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260731-allwinner-a733-nmi-support-v1-1-61e4a0825b20@baylibre.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Correct a few white-space issues, like double space after '=' or before
bracket '{' characters, which will be flagged by dt-check-style. No
functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Jeff Johnson <jjohnson@kernel.org> # qcom,ath10k.yaml
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for Documentation/devicetree/bindings/pwm
Acked-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://patch.msgid.link/20260801195613.235430-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Any new DTS example in the binding should pass dt-check-style 'strict'
mode without warnings, although scripts does report some false positives.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803091758.232633-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Document already used rules about example DTS in the binding:
- All final device bindings (except sub-block of more complex devices)
should have an example.
- Phandles do not need to be resolvable - Sashiko already provided
incorrect review, so this might help it to understand the concept.
- Example should be complete, readable (use known defines), without
'status' property.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260722062240.19382-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> says:
This patch series adds a new `rpmh_read()` API to allow reading RPMH
addresses. Using this API enhances the RPMH regulator driver by adding
readback of the voltage/bypass/mode settings as they have been applied by
APPS during the bootloader stage, so regulator framework can get them
via `get_mode`, `get_bypass` & `get_voltage_selector` callbacks during
regulator registration.
This is needed because currently regulator framework does a unnecessary
write with `min-microvolt` DT setting for all the RPMH regulators during
regulator registration, because the first time after boot the value is
seen as -ENOTRECOVERABLE, as there is no option to read these regulator
settings.
With this change this unnecessary write can be avoided and regulator
framework gets a sense of the initial state set during the bootloader
stage for all regulator settings.
NOTE - During discussion on the v2 series - PATCH 3/4, reviewer had
inquired about possible need for the use of the sync_state() to handle the
"multiple" client case - for maintaining the regulator settings till all
the clients are probed.
This case was not covered in my previous series and had originally planned
to do that series separately. But after the discussion decided to merge
the 2 series as it seemed this would be a better approach. But after
working on sync_state change. I realized a basic issue with using
sync_state() for regulators - that its per-driver and not per-regulator
resource. But we needed a sync_state callback for each regulator separately.
I had been experimenting with few ideas but seems its going to need more
time for me to close on the equivalent solution that has per-regulator
sync_state or something to that effect. So I thought to close on this
series and attend to that separately.
Link: https://patch.msgid.link/20260801-b4-read-rpmh-v5-v6-0-9fcb54928523@oss.qualcomm.com
Convert TI IODELAY controller from text to DT schema. Document child
properties missing from text bindings for proper validation.
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
SM8450 init sequence for this PHY varies significantly and can't be reused
in SM8475.
Add bindings for the PHY found in this SoC.
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-1-48bd91a19abf@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The Qualcomm SGMII SerDes PHY has two distinct voltage supply rails,
vdda-0p9 and vdda-1p2. The binding incorrectly described only a single
generic supply via 'phy-supply'.
Deprecate 'phy-supply' and instead add two named supply properties. The
0.9V rail draws a peak current of 46 mA and the 1.2V rail draws 15 mA.
Fixes: 97b7951257 ("dt-bindings: phy: describe the Qualcomm SGMII PHY")
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260804-b4-sgmiieth_serdes_regulator-v2-1-c4bc688177dd@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
In Layerscape (Arm) and QorIQ (PowerPC) devices, hardware peripherals
are accessed by the CPU through a portion of the SoC address space
called CCSR ("Configuration, Control, and Status Registers"). All
hardware IP blocks have their registers mapped here, and the Device
Configuration block makes no exception.
However, there exists a secondary range of the address space named DCSR
("Debug Control and Status Registers") which, like CCSR, also holds
registers of hardware IP blocks, except the DCSR contents is hidden in
all public reference manuals.
The intention of the CCSR/DCSR split, to the best of my knowledge, was
to place the functionality that is too low level for normal use, and
which is necessary only for debug, in a completely separate address
space which can be hidden.
A use case has appeared where networking SerDes lanes need to be
reconfigured at runtime for a different protocol (example: 10GBase-R to
SGMII), and the architecture of the SoCs does not normally permit that.
The Reset Configuration Word (RCW) is a data structure read by the SoC
preboot loader (PBL) which contains stuff like pinmuxing and SerDes
protocol mapping for each lane.
The RCW that the PBL has loaded is visible in the DCFG block's normal
status registers (from CCSR), as read only. Turns out, the RCW is also
mapped in the DCFG's shadow register map (in DCSR), in a write-only
form. Writing to the RCW registers from the DCFG's DCSR space to change
what the PBL has loaded is called "RCW override".
It has been validated that the RCW override procedure is necessary to
reconfigure the networking data path when a SerDes lane performs a major
protocol change. It changes some internal muxes which connect the PCS to
either the 10G MAC or to the 1G MAC.
Defining the DCSR area of the DCFG as a secondary 'reg' array element
allows operating systems to perform RCW overrides. Since it is
introduced late in the binding's lifetime, it is optional. It can be
identified by name, but also by index (first 'reg' is CCSR).
Note that while all SoCs should have a DCFG register block in DCSR, we
only need to expose it for the SoCs where the RCW override procedure is
known to be needed and has been validated.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260721231603.67865-8-vladimir.oltean@nxp.com
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0
and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to
dap2_din_pw0 and dap2_dout_pv7.
Fixes: 30a9d5162f ("dt-bindings: pinctrl: Document Tegra264 pin controllers")
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Add support for the optional rockchip,clk-lane-phase device tree property
to allow board-specific tuning of the clock lane sampling phase for
improved signal integrity across supported data rates.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
SM8450 init sequence for this PHY varies significantly and can't be used in
SM8475.
Add bindings for the PHY found in this SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Link: https://patch.msgid.link/20260804-sm8475-bup-usbss-v3-1-9a5b9ebf62de@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add device tree binding support for the RZ/G3L (r9a08g046) USB2 PHY.
The RZ/G3L USB PHY is almost identical to the RZ/G3S USB PHY, the
difference being 2 OTG blocks on RZ/G3L compared to 1 on RZ/G3S.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260806102236.149159-7-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use
fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi
with that on the SM8750.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803091441.3040830-3-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document the Hawi compatible string for the QMP combo PHY.
Hawi uses a new QSERDES V10 register layout with a new COM AON module
and hardware-specific PHY init sequences compared to previous targets,
requiring a dedicated compatible string.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260803091441.3040830-2-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add support for grouping individual PCA963x channels into a multicolor
LED by introducing a multi-led@N node pattern. This follows the
convention established by other multicolor LED drivers such as
kinetic,ktd202x.
This is necessary to support and model hardware setups where multiple
PWM channels drive a single physical RGB LED.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Link: https://patch.msgid.link/20260727-monza-leds-v8-2-6e7e93d44dba@oss.qualcomm.com
Signed-off-by: Lee Jones <lee@kernel.org>
The pca9635 supports 16 LED channels, unlike the pca9634 which only
supports 8. The allOf conditional grouped both chips under a single
else branch capping reg at a maximum of 7.
Give pca9634 its own if/then block and set maximum: 15 unconditionally
in the top-level led@ node, making it the default for pca9635 and any
future compatible. Also tighten the node name regex from [0-9a-f]+ to
[0-9a-f] to match the single-digit hardware limit.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Link: https://patch.msgid.link/20260727-monza-leds-v8-1-6e7e93d44dba@oss.qualcomm.com
Signed-off-by: Lee Jones <lee@kernel.org>
Convert the Texas Instruments TPS65217 bindings to DT schema.
During the conversion, the following updates were made:
- Documented the 'regulators', 'charger' and 'pwrbutton' child nodes,
which are used by the boards but were missing from the old txt
binding.
- Documented the 'interrupts', 'interrupt-controller', '#interrupt-cells'
and 'ti,pmic-shutdown-controller' properties, which are used by the
am335x boards and read by the driver.
The regulator/tps65217.txt binding documented the same 'ti,tps65217'
compatible and is superseded by this schema, so remove it as well.
Signed-off-by: Eduard Bostina <egbostina@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260723100605.628882-5-egbostina@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
Some of the Qualcomm SPMI PMIC has haptics device in it, add it in the
device list.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260804-qcom-spmi-haptics-v5-2-77128ebbdd2d@oss.qualcomm.com
Signed-off-by: Lee Jones <lee@kernel.org>
The Axiado AX3005 SPI controller is software-compatible with the
Synopsys DesignWare APB SSI 1.01a programming interface.
Document the "axiado,ax3005-spi" SoC-specific compatible with
"snps,dwc-ssi-1.01a" as its fallback. This preserves identification of
the AX3005 integration while allowing the controller to use the
existing DesignWare APB SSI support.
Signed-off-by: Swark Yang <syang@axiado.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260805-upstrea-ax3005-spi-v4-v4-1-5b8bc11cb841@axiado.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add the compatible string for the APPS SMMU present on the Qualcomm
IPQ9650 SoC.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Will Deacon <will@kernel.org>
1. Improve (fix) ds2482 driver module autoloading, when probing from
Devicetree.
2. Convert HDQ One Wire devicetree bindings to DT schema format.
3. Fixes for handling incorrect data from potentially malicious
hardware, looking theoretical issues but still worth to fix.
Affected drivers: w1 core code, ds28e17 and ds2482.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmp0Ru0QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1zZTEACQuFIiWT/wlL1GFi2BtnS+3QuWxWsbQPL8
64kQa3c3QZu+d/wjKeJxv3dgfPNx3xeFOuKnIrQQqhZ0DCdKb07rKeZvhTmbTU6U
4Fde1o9sSm8k2ZkPyF54aes6K28xoexoOC+cyZ54YAeXGlmN/YZXNPBsLQEBWeMU
OkUUbylj2umcz0S2jYRDhVQQWPNVjSyEKtrq7PZKhorPBVEq/E9MvIM+7Sk6xoZ4
RtXMknYPGpc4rQMZhUGt4Ytkj1zrPX/nATD6H/WBjls+5H2r7EXeqevbbT8N35V0
ZwC5SLmNUZxVhKDvO70VvyLVDYSpPkfxcF4Bhzwndb87wOf+ntG2tAokYzWPIeE/
bRC4cGBVD7MEHUaChaCRFbCFRupoHQzitIlcjYzsBuRO9ZxIT02ch+91lCyxStNh
t8upB1/yF18dfPdCn4elim2IqUNZlRTIjuQVZc9mVDI+KkOelToNgIfubIFjD2a8
OvMjrZuTo5hE9ci6W0AtMV7PNepit7XLFRHNzIh6Q2e9dCIl+6E/FUldRyEQGVwE
Ti2wBqU/v31VxfiXwXNy4kiiDMIEFPUuni+VU5UgMljdKwD5cf583G1WrV7i/arC
JU5YzpYD8H32b0P0OHjX9n7yiWjvnqZA2Ywbc3UCSRMjY65YLP4jxbHkcUnlM1fn
8BFwXlY9dw==
=qYor
-----END PGP SIGNATURE-----
Merge tag 'w1-drv-7.3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next
Krzysztof writes:
1-Wire bus drivers for v7.3
1. Improve (fix) ds2482 driver module autoloading, when probing from
Devicetree.
2. Convert HDQ One Wire devicetree bindings to DT schema format.
3. Fixes for handling incorrect data from potentially malicious
hardware, looking theoretical issues but still worth to fix.
Affected drivers: w1 core code, ds28e17 and ds2482.
* tag 'w1-drv-7.3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1:
w1: ds2482: Fix signedness bug in ds2482_w1_triplet()
w1: validate slave string length before checking separator
w1: ds28e17: reject an oversize length on an I2C block read
dt-bindings: w1: Convert HDQ One Wire to DT schema
w1: ds2482: add OF device match table
The Microchip ZL30643 (chip ID 0x0E3B) is a member of the ZL3064x
line card timing family. It is register compatible with the 3-channel
ZL30733 (chip ID 0x0E95) of the ZL3073x family: both datasheets
describe the same register map and use the same chip-ID encoding.
Describe it with a fallback to microchip,zl30733 rather than a new
standalone compatible.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260730-for-upstream-zl30643-v2-1-0ea0bbd03755@free.fr
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Add the clock binding header and schema for the Rockchip RV1106 clock
and reset unit. The clock IDs are numbered continuously from 0, in the
same way as the RV1103B. The header also covers the MMC drive and
sample phase clocks, which the CRU provides using control registers in
the GRF region.
The RV1103 is a package variant of the RV1106 and uses the same CRU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260729133609.3465563-2-sjg@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Document support for the Renesas R-Car X5H Clock Pulse Generator, and
add binding definitions for a limited initial set of clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/7a33c99816c850faeec5c17532811faf78959a1d.1785941595.git.geert+renesas@glider.be
Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
single-link mode. LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be
used at the same time as MIPI-DSI.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729125516.230757-10-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
The DU block on the RZ/G3L SoC is identical to the one found on the RZ/G2L
SoC. However, it supports the DSI, DPI, and LVDS interfaces, while the
RZ/G2L supports only the DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string,
'renesas,r9a08g046-du', is added for the RZ/G3L SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729125516.230757-8-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY
timings and also the PLLCLK is ungateble clock. Add the compatible
string "renesas,r9a08g046-mipi-dsi" to handle these difference for the
Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729125516.230757-2-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
The Microchip MCP47A1 is a 6-bit volatile Digital-to-Analog converter
which communicates via I2C.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Joshua Crofts <joshua.crofts1@gmail.com>
Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
I'm transitioning to a new email, add mapping and update MAINTAINERS
entries to keep email up to date.
Signed-off-by: Maxwell Doose <maxwell@maxwelld.cc>
Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Document the bindings for the Sensirion SLF3S family of digital
liquid-flow sensors on I2C. The family currently covers the
SLF3S-0600F, SLF3S-1300F and SLF3S-4000B variants.
All variants share the same register map and differ only in the flow
scale factor and the calibrated measurement range, which the driver
reads back from the product-information register. Since that lookup
is needed in any case, a fallback compatible would buy nothing, so
each variant gets its own compatible without a fallback. A future
drop-in compatible part can then claim one of these compatibles and
work on kernels that do not know its product ID yet.
The active calibration medium (water / IPA) is runtime-switchable
via the in_volumeflow_medium sysfs attribute and therefore not a
DT property.
Signed-off-by: Wadim Mueller <wafgo01@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Add Maili platform bindings for SCM, IMEM, AOSS, and PMIC GLINK. Add
Shikra IMEM, RPM SMD, LLCC, and UBWC support, including handling for
firmware-configured LLCC ECC interrupts.
Add the generic Peripheral Authentication Service with SCM and OP-TEE
backends, and migrate the MSM DRM and IPA drivers to it.
Add SCM SMC-call tracepoints and configurable minidump delivery through
always-on SRAM. Correct SCM download-mode pointer ordering and improve
download-mode probe diagnostics.
Rework the UBWC configuration database and add Milos and Shikra
configuration. Add protection-domain mappings for SA8775P and QCS8300,
support newer ICE versions, Hawi subsystem statistics, and SDM850
identification.
Simplify Qualcomm SoC Kconfig selection and architecture dependencies.
Use managed resources in EBI2 and RPMh RSC probe paths to correct cleanup
on failures.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmprfkkOHGJqb3JuQGty
eW8uc2UACgkQCx85Pw2ZrcUUVQ/+NufSVHC2E2W/ZTTVGAWCoB9rvNhPaPCoYrFY
WsefQzhdCk54rzzb1DsVyj/Lh/nKVApdH495TWgWrUpRuq6w0xjHkYKklQNp7Hqt
Lr2GNx90mvQDgvj1RNa++oI8dhpeEv/d7as0xrwQibi85mw/F/jGpHdw7VnfcRF5
XcTIIMtA+M5KWxmTBnwH+pgB5aaEDUED82mifcdOeNgI7l6A20jBdT0MJ8SZBMff
wTMbuSOOEJlNjtcGtFm4EDdpVsoL1s4vAt0PGyVPpGvT2WVE1aGffPS4dMv4kNDU
xFQsh6ST+J25W9r4zib5HB6FivgKcEvkMmZb4ca/bcJGxAEb163Yyay8Z+sz4kNV
qEHjbm7zSfUiKELsFzzaulnLhEghZ6R/CQua+XdXq5J3QgKocqJ3m/a2Mm5rRXHv
XUE+aEy/cJdxxhqan8BZ8Ihn1SkMRCDNWTVopi4H12RtIfXBII/9LEWW8fp66GlW
55TYLjTrdA5V56/NHmm1fsHDP7KojHUTipg9WL07OL/LggJExOvBpBZIoCQPUOR7
bB6jlf8bu00Ecur091+HkFD1ePcT0DTO+1tHdpG2mv27WXVVsFAZmIDp3G64cEn3
vZOVNDEZBjyE/MMqKwd+W0ERERoQnW+YYdtigN5tWmk/+M+/11D/10x6FPr1Q+38
OdidhsU=
=+KlS
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpyRQsACgkQmmx57+YA
GNkjJQ//RfK/MpMrLOk4IPiA/+Ek93eXgVqfcXwUTAhg23HddOkOgZugVLi//xv0
flRkb/XbOc6aYOTIdmR6thfFOMkUbRxQl5EqSypNEWsrjsiVKbxmqH801BPPgFRw
KzbmqNNe1O0koJ+p7b6g9kwXzEyF9iyBqjZqfWfbayqcznI1DC8x2Hs8ieBQvsKj
7igqDpLE2XhRuBhIRxOmKb17nvYaAS0/Jxa97Mhic7CEyNmC0EWUWXwJzWDJSBSv
253kTU6JVXcm7BI33lIvkAZbUwMo8wtz6hApJPj+JCELXNho9CTondOMhQ+lLZmx
kZ3yJQRGQS41+nb6BVfVJkqfkErnxRM18sYbMzpEk79mnoN6OtomMypNQozq5U8/
qhA6sgygjL/jI62RCUTmiFhTXgkBXRw/yDiAUihaYWmCExUc/TCXw2Yb1FNk9m5m
k9l4F9ynH1DoFRCtzOzqtO72ZqBnbuELnYZ/AA/mw3bFyHAKeLfmQpREqWfDcJCO
g3me14uHHdWaMcoAICOBv9Obx1blxXU3vx6Fvm7ZJU4yygWvM/8BrroViHRGtUOb
a8vggrcangB6JxMMX3AygpYu0kIBILRXUvsQccavcNkf5p1p0nQhKEgdHpD4n72r
f70dhESEmIOLAxUI+ByQIh6deUJCPbOa/RE4F8QRaoTz8CcZKFc=
=5310
-----END PGP SIGNATURE-----
Merge tag 'qcom-drivers-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for v7.3
Add Maili platform bindings for SCM, IMEM, AOSS, and PMIC GLINK. Add
Shikra IMEM, RPM SMD, LLCC, and UBWC support, including handling for
firmware-configured LLCC ECC interrupts.
Add the generic Peripheral Authentication Service with SCM and OP-TEE
backends, and migrate the MSM DRM and IPA drivers to it.
Add SCM SMC-call tracepoints and configurable minidump delivery through
always-on SRAM. Correct SCM download-mode pointer ordering and improve
download-mode probe diagnostics.
Rework the UBWC configuration database and add Milos and Shikra
configuration. Add protection-domain mappings for SA8775P and QCS8300,
support newer ICE versions, Hawi subsystem statistics, and SDM850
identification.
Simplify Qualcomm SoC Kconfig selection and architecture dependencies.
Use managed resources in EBI2 and RPMh RSC probe paths to correct cleanup
on failures.
* tag 'qcom-drivers-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (44 commits)
soc: qcom: llcc: Skip ECC interrupt setup on Shikra, pre-configured by DSF
dt-bindings: sram: Document qcom,shikra-imem compatible
net: ipa: Switch to generic PAS TZ APIs
firmware: qcom: scm: Add minidump SRAM support
firmware: qcom: scm: use dev_err_probe() for dload address failure
firmware: qcom: scm: Fix missing smp_load_acquire()
dt-bindings: firmware: qcom,scm: Add minidump SRAM property
drm/msm: Switch to generic PAS TZ APIs
bus: qcom-ebi2: use managed resources for clocks and children
soc: qcom: rpmh-rsc: manage PM notifiers with devres
firmware: qcom: scm: Allow QSEECOM on Honor Magicbook Art 14
firmware: qcom: scm: instrument SMC call path with tracepoints
firmware: qcom: scm: add trace events for the SMC call interface
soc: qcom: Avoid SCM and SPM for cpuidle drivers
soc: qcom: Make important drivers default
soc: qcom: Restrict drivers per ARM/ARM64
soc: qcom: Hide all drivers behind selectable menu
MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service
firmware: qcom: Add a PAS TEE service
firmware: qcom_scm: Migrate to generic PAS service
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
'num-cs' property is a single integer, thus the binding should not set
maxItems. This could be replaced with proper min/max constraints for
values, except that such constraints are not known.
spi-controller.yaml schema already defines this property, so its
presence here is redundant.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260804-spi-num-cs-v1-2-4ccb13dcc7b0@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
'num-cs' property is a single integer, thus the binding should not set
maxItems. This could be replaced with proper min/max constraints for
values, except that hardware (as expressed in driver) supports only one
native chipselect, thus constraint of "const:1" would make the property
implied by the compatible. spi-controller.yaml schema already defines
this property, so its presence here is redundant.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260804-spi-num-cs-v1-1-4ccb13dcc7b0@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> says:
Add AudioReach support for LPASS Audio IF based TDM backends and wire it
up for the sc8280xp machine driver.
The series first adds topology-driven Audio IF source/sink handling so
the DSP interface parameters can be described by topology while runtime
media format and slot configuration still come from the machine driver.
It then adds TDM DAI operations for q6apm-lpass-dais, exposes the Audio
IF clock IDs through the q6dsp-lpass-ports binding and q6prm clock
tables, and introduces common QCOM helpers for parsing standard
dai-tdm-slot-* properties from backend CPU and codec endpoints.
Finally, sc8280xp uses the common helpers during hw_params to program
CPU and codec TDM slots, derive the backend bit clock from the active
PCM parameters, and request the CPU and codec clocks before the stream is
started.
Link: https://patch.msgid.link/20260804070307.117119-1-prasad.kumpatla@oss.qualcomm.com
Allow standard dai-tdm-slot-* properties in the CPU and codec child
nodes of a DAI link.
The QCOM machine driver parses these child nodes to configure TDM slots
on the active CPU and codec DAIs. The properties are already defined by
the common tdm-slot binding, but qcom,sm8250.yaml currently rejects them
because the CPU and codec child nodes set additionalProperties: false.
Permit dai-tdm-slot-num, dai-tdm-slot-width and dai-tdm-slot-[rt]x-mask
there so boards using TDM backends can describe the slot layout without
schema warnings.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Link: https://patch.msgid.link/20260804070307.117119-6-prasad.kumpatla@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> says:
Improve handling of some corner cases that are not used by current topology
designs, but can be crafted within the rules of a topology file.
For example branching topologies, where a single input routed to multiple
output endpoints. The already configured part of the graph places constraint
on how the new branch can be configured.
Handling of process modules also updated to be able to 'guess' what
parameters can be changed by the module and allow flexible operation.
Link: https://patch.msgid.link/20260730121729.18673-1-peter.ujfalusi@linux.intel.com
Add a dedicated binding for the Qualcomm Nord SoC PAS devices: ADSP
and CDSPs. Nord ADSP uses CX and MX power domains while the CDSPs
add an NSP domain on top of that.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260729023508.879752-3-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Correct a few white-space issues, like double space after '=' or before
bracket '{' characters, which will be flagged by dt-check-style. No
functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260801195505.235099-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Add a new compatible string "starfive,jhb100-sfc" for the StarFive
JHB100 SPI Flash Controller, it based on the Synopsys DesignWare
SSI version 2.00a but with minor modifications.
Due to these minor modifications, it only supports access for flash
memory and requires a system controller register to configure the
address mode filter for SPI NOR flash devices.
The starfive,sfc-filter-syscon property is required to provide a phandle
to the system controller that manages switching between 3-byte and
4-byte addressing modes, essential for supporting SPI NOR flash devices
with different address width requirements.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260803124044.156998-11-changhuang.liang@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The A733 MMC0/1/2 controllers are compatible with the D1 ones.
Add an A733-specific compatible string, with the D1 as fallback.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Ulf Hansson <ulfh@kernel.org>
Allow an eMMC hardware partition node to describe an NVMEM layout so the
partition can be exposed as an NVMEM provider. This lets a partition
(e.g. an eMMC boot partition) store device-specific information such as a
WiFi MAC address or a Bluetooth BD address and reference it through NVMEM
cells.
Accept "fixed-layout" as the partition node compatible, in addition to
"fixed-partitions", so the layout can be described directly on the
partition node.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Ulf Hansson <ulfh@kernel.org>
