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dt-bindings: display: bridge: renesas,dsi: Document RZ/G3L

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The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY
timings and also the PLLCLK is ungateble clock. Add the compatible
string "renesas,r9a08g046-mipi-dsi" to handle these difference for the
Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729125516.230757-2-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
This commit is contained in:
Biju Das 2026-07-29 13:54:53 +01:00
parent 3d33e9c726
commit a4377c7722
1 changed files with 1 additions and 0 deletions
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Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
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@ -28,6 +28,7 @@ properties:
- const: renesas,r9a09g057-mipi-dsi
- enum:
- renesas,r9a08g046-mipi-dsi # RZ/G3L
- renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
reg: