From a4377c7722b824d3d2eb940eb681cf37b0969a24 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 29 Jul 2026 13:54:53 +0100 Subject: [PATCH] dt-bindings: display: bridge: renesas,dsi: Document RZ/G3L The RZ/G3L DSI IP is similar to the RZ/G2L but has different global PHY timings and also the PLLCLK is ungateble clock. Add the compatible string "renesas,r9a08g046-mipi-dsi" to handle these difference for the Renesas RZ/G3L SoC. The power to DSI region is controlled by SYSC block. Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260729125516.230757-2-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das --- .../devicetree/bindings/display/bridge/renesas,dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index c20625b8425e..3832a553871b 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -28,6 +28,7 @@ properties: - const: renesas,r9a09g057-mipi-dsi - enum: + - renesas,r9a08g046-mipi-dsi # RZ/G3L - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) reg: