github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-22 04:34:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Qualcomm clock fixes for v7.2

Browse Source 
Fix the Eliza display clock controller to avoid RCG stall. Revert the
 rework of the "PHY mux" clock, as this broke PCIe on several different
 targets.
 
 Drop (and correct one) bouncing maintainer email addresses in DeviceTree
 bindings.
 -----BEGIN PGP SIGNATURE-----
 
 iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmpnlToOHGJqb3JuQGty
 eW8uc2UACgkQCx85Pw2ZrcWNXg//RN1nAKFwKalihovDtpk6wlkxdUEJl53E1dcU
 t5BWTTPWqlSmlc/FWvIqe7EccWRkm/3/rzt1KKaTw6mqupm2pmvtHa/A1dIfzNuw
 EMwcFZQssb4m56rS+hO8fvGTxSE8MEd+gl4UXet+neXGvmM7mLu+LotMIH0EbELT
 QZetojCYtZQVezkiNy/BKiXLCER/FnuQU0S37cpOR6bEWiS0rzptPKAFX3qgoKZ/
 I1ff7iCJ5DJSkIYgAZhFXvMk4V6GGP+HXBp5LnWyzxTt+J5+YER+L5Zmv0po8NFh
 NzFxfC9nH+kihD9716FouII64QbwbmKdTc0qS1tLhH9u5OQmhTZEQ283kadpZIdc
 nwIglsdmibgFixRDM6sI7CR3aYuFZVbaMCMKWRC9aE7Vxpf0KuRzJnmqxCOwqa1u
 5E6+Ps5wb93+mDtYAdx+qRXzLh8ZGUZksoVOE2gC6aZGFkDHEAkQewww6nEQ5ikT
 9dZlgnesgMux78Yn1H+PhTFtNXgJXFjWGgBm2YgVXOCvDyXaTF6LE3wlpSIeo9SV
 mGAExhPm0OrBmxyN15ynQhVXrn4cKv5sY3rBRKPWtVi3pzWmp1y7KVBf/AL6UONj
 c6VmCq1hFBPrV6IUPM8kHJK50Ju+yIrcqS2P6quEaEIT8RKCyunvurwHHjhUz7Ya
 uUM7ZxI=
 =yj29
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp6GioUHHN3Ym95ZEBj
 aHJvbWl1bS5vcmcACgkQrQKIl8bklSW9bA//SYbI1Mj6q2gMJyFZEL0Fz8P5pfWI
 LAPPAFK+xhTQDl0POkv2/zzRYmXhuQFTD/v2asRmCyu/C9b+GMKVBTuAQWnybSy3
 Mp6HjYRrAVpMbZE56lLGkgZXi6a3bZOh9K5m6wdd5frMQt131slBaiiK/U3ZyFKR
 TQEIpNsbNa5mx614yCqobEDlGBIO0o4r2Z4iQD05ni2MH+ZYhVUKo+8gisEJledR
 GK7ter1b04MCMaxLuW6GAj46DNUhXdXTaEunmgdimjhtSTCy09AulTZO477heQQj
 PGXXxjuh7bxY0z8xorbWeqgz1nhr1L/nSDXPxTOyydBJ4FESqEtx8H4SaYiqdqxI
 AGNMH7KQPPJTf9nB8lJWFW8tlUi71a/LlQHH8Gu55+N28nkTceQ02dR1eUSue43I
 o2g6PMDUayX5SQRyQyEmO4Geusm5yENNHSxL7myDOsw3XIJbt9fjCTdulA50azK2
 3QsFkXHy+fBOHxLa2njELKpga/AkUmmmfdj8u3nSe7z60Rjo0ZqUgPd61zO6HTf+
 ncDjKlWHnihb7TnEQWyYSLZr9t/BOALDQXS8UFoxaNYu1ReNrV9OqxZFKN/igX77
 HzYEmYURM5XeS3I/W8ignbxAXk6VBGvd91tv3By8o7fhlPfPQNCCcOJ9VvhdBkFb
 Vrf6zvBdavldz3U=
 =RZDP
 -----END PGP SIGNATURE-----

Merge tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes

Pull Qualcomm clock driver fixes from Bjorn Andersson:

 - Fix the Eliza display clock controller to avoid RCG stall.
   Revert the rework of the "PHY mux" clock, as this broke PCIe
   on several different targets
 - Drop (and correct one) bouncing maintainer email addresses in
   Qualcomm clk DeviceTree bindings

* tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  dt-bindings: clock: Replace bouncing emails
  Revert "clk: qcom: regmap-phy-mux: Rework the implementation"
  clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK
This commit is contained in:
Stephen Boyd 2026-08-10 11:35:50 -07:00
commit 7ae8acad2d
6 changed files with 22 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
View File

@ -7,8 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
- Sireesh Kodali <sireeshkodali@protonmail.com>
- Barnabas Czeman <barnabas.czeman@mainlining.org>
description: |

1
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
View File

@ -8,7 +8,6 @@ title: Qualcomm Global Clock & Reset Controller on IPQ9574
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Anusha Rao <quic_anusha@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

1
Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
View File

@ -8,7 +8,6 @@ title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IP
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Anusha Rao <quic_anusha@quicinc.com>
description: |
Qualcomm networking sub system clock control module provides the clocks,

2
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos Auto v9 SoC clock controller
maintainers:
- Chanho Park <chanho61.park@samsung.com>
- Alim Akhtar <alim.akhtar@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>

58
drivers/clk/qcom/clk-regmap-phy-mux.c
View File

@ -15,66 +15,48 @@
#define PHY_MUX_PHY_SRC 0
#define PHY_MUX_REF_SRC 2
#define XO_RATE 19200000UL
static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
{
return container_of(clkr, struct clk_regmap_phy_mux, clkr);
}
static unsigned long phy_mux_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
static int phy_mux_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
u32 val;
unsigned int val;
regmap_read(clkr->regmap, phy_mux->reg, &val);
val = FIELD_GET(PHY_MUX_MASK, val);
switch (FIELD_GET(PHY_MUX_MASK, val)) {
case PHY_MUX_PHY_SRC:
return ULONG_MAX;
case PHY_MUX_REF_SRC:
return XO_RATE;
default:
return 0;
}
WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
return val == PHY_MUX_PHY_SRC;
}
static int phy_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
if (req->rate == XO_RATE || req->rate == ULONG_MAX)
return 0;
return -EINVAL;
}
static int phy_mux_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
static int phy_mux_enable(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
u32 val;
switch (rate) {
case XO_RATE:
val = PHY_MUX_REF_SRC;
break;
case ULONG_MAX:
val = PHY_MUX_PHY_SRC;
break;
default:
return -EINVAL;
}
return regmap_update_bits(clkr->regmap, phy_mux->reg,
PHY_MUX_MASK,
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
}
static void phy_mux_disable(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
regmap_update_bits(clkr->regmap, phy_mux->reg,
PHY_MUX_MASK,
FIELD_PREP(PHY_MUX_MASK, val));
return 0;
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
}
const struct clk_ops clk_regmap_phy_mux_ops = {
.recalc_rate = phy_mux_recalc_rate,
.determine_rate = phy_mux_determine_rate,
.set_rate = phy_mux_set_rate,
.enable = phy_mux_enable,
.disable = phy_mux_disable,
.is_enabled = phy_mux_is_enabled,
};
EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);

2
drivers/clk/qcom/dispcc-eliza.c
View File

@ -756,7 +756,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.parent_data = disp_cc_parent_data_11,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_11),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
},
};