dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator

Document support for the Renesas R-Car X5H Clock Pulse Generator, and
add binding definitions for a limited initial set of clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/7a33c99816c850faeec5c17532811faf78959a1d.1785941595.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2026-08-05 17:20:49 +02:00
parent 8cdeaa50ea
commit 88656a46df
2 changed files with 69 additions and 0 deletions

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car X5H Clock Pulse Generator
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillators,
PLL circuits, clock dividers and clock control circuits. It provides various
clocks for other modules.
properties:
compatible:
const: renesas,r8a78000-cpg
reg:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: extal
- const: extalr
'#clock-cells':
description:
The single clock specifier cell must be the clock number, as defined in
<dt-bindings/clock/renesas,r8a78000-cpg.h>.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@c1320000 {
compatible = "renesas,r8a78000-cpg";
reg = <0xc1320000 0x10000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <1>;
};

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2026 Glider bv
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__
/* R-Car X5H Clock Pulse Generator Clocks */
#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0
#define R8A78000_CPG_SGASYNCD8_PERW_BUS 1
#define R8A78000_CPG_SGASYNCD16_PERW_BUS 2
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */