Clock driver for RV1106, fix for rk3576 spi source mux, better representing

fractional PLL coefficients and a fix for the dclk of the 3rd video-port to not affect other compoents when its rate gets changed. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmpzqVIQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgTYRB/9lSKLStQtLlreGs6zY5F2fVLN6qUgimFuz t7MFxUTJp/J8dArPK/PST78s+dbFcI2U2d+4K24zuDtNJm7Zsw3sEEcNjFRNqcnN FRyXdT1Yc1EhTFlwg8rSeVC/sCznm1b59BMBPRP2u11kDtPtS1HxpEPACFBg4rIg Bul89omf3Iyq//W5wweb69IK0GxAw3fldjgONOd9D1yd+GvO/HW/V03bXbX71T9Z RkSSyQ3E8bdxJzdEMUgaSSFVAxSCji0v8H30Kp5hlWm4JX3yhZzyTHcvv/QwxgNk F+irFyG5GfFzVg1wN+E55bdcL8o6OthIocVd9ae+OtKs5GFotzsi =6iqM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8DQIUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSV6Pw/9Fgw7gZRPS0KFJ/MXUgc/AZikVlpU r8GjmpcmpnjiZOIOKM2dvmBV7f1iB3xxNS0c9QDQ+HGa3G/+WWKsoHePumRVuJMf Mq7Zds7TP4DOSrxQGmrGA8B7YAthPV3iSUxjnxd5di0KXf0958HWVdNuYUNuS2x2 3qHGpqt24zGG1PV/59QKHK+fzrMt6dMOLOscYwhoaaQrnxXt0nQjslwew7W2QSlF 5F/2g8KHg3ezZU0S0AWsZ2+b2yhEojGxjjYwBjEgFysiOABAd2EfilgSG3EU7l5f 41uf3eJKfbocz7Lw0ZoHo1TBc9OAvA9mPLwoj/eFEc1oIH//2ODsvsd4spOSimJz RTWH2C9XJxlZKnBN/ZFRZtaghsdmF74iIumweekXXidsVP0+BsQyp6f6aKNOABiU 8RAEpL50vHFBt9RCNvV8dBghav6TWmR8oHkRlNoYzqZ9NX3L4wVQn8rhSNwwQcGw mvs7ginmTQX+uC9qgHuIV4kP4WasYCfTzFQlPlFMoAtpgtggtuXzxqeJJEfTpRiW 080t0XVS5kMIFPgbd51xdpBe+BJTLKUq+k8wZuP0XazfENP/fgAj1sw2DXdkD3NU IfknpUcBtywx5AIdXGWP7qNTWSJ+YAkSz/KTPd9f76UY1ToXgMMH2VAc42FD3rsf Qe1OM6jN7BB4CW8= =jLWg -----END PGP SIGNATURE----- Merge tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Clock driver for Rockchip RV1106 - Fix for Rockchip rk3576 spi source mux - Better representing fractional PLL coefficients in Rockchip clk driver - Fix for the Rockchip dclk of the 3rd video-port to not affect other compoents when its rate gets changed * tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src
2026-09-22 12:44:03 +02:00 · 2026-08-11 23:03:45 -07:00 · 2026-08-11 23:03:45 -07:00 · 1353d95e63
commit 1353d95e63
parent 8cdeaa50ea 586ff159ec
9 changed files with 1500 additions and 18 deletions
--- a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1106 Clock and Reset Unit
+
+maintainers:
+  - Simon Glass <sjg@chromium.org>
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  The RV1106 clock controller generates the clock and also implements a
+  reset controller for SoC peripherals.
+
+properties:
+  compatible:
+    const: rockchip,rv1106-cru
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF).
+      If missing, pll rates are not changeable due to the missing pll
+      lock status, and the MMC drive and sample phase clocks, whose
+      control registers live in the GRF region, are not registered.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@ff3b0000 {
+      compatible = "rockchip,rv1106-cru";
+      reg = <0xff3b0000 0x20000>;
+      rockchip,grf = <&grf>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@ -23,6 +23,13 @@ config CLK_RV1103B
 	help
 	  Build the driver for RV1103B Clock Driver.

+config CLK_RV1106
+	bool "Rockchip RV1106 clock controller support"
+	depends on ARM || COMPILE_TEST
+	default y
+	help
+	  Build the driver for RV1106 Clock Driver.
+
 config CLK_RV110X
 	bool "Rockchip RV110x clock controller support"
 	depends on ARM || COMPILE_TEST
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@ -19,6 +19,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o

 obj-$(CONFIG_CLK_PX30)          += clk-px30.o
 obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o
+obj-$(CONFIG_CLK_RV1106)	+= clk-rv1106.o
 obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
 obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o
 obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@ -13,6 +13,7 @@
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
 #include <linux/iopoll.h>
+#include <linux/math64.h>
 #include <linux/regmap.h>
 #include <linux/clk.h>
 #include "clk.h"
@ -900,6 +901,14 @@ static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
 	rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
 }

+/*
+ * 2250 MHz <= Fvco <= 4500 MHz
+ * For Fvco > 3 GHz: period jitter +-1% frac PLL, +-0.75% int PLL
+ * For Fvco < 3 GHz: period jitter +-2% frac PLL, +-1.50% int PLL
+ * Fvco = ((m + k / 65536) * Fin) / p
+ * Fout = ((m + k / 65536) * Fin) / (p * 2^s)
+ * -32768 <= k <= 32767 (only available in frac PLLs, not int PLLs)
+ */
 static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
 {
 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
@ -913,11 +922,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned

 	if (cur.k) {
 		/* fractional mode */
-		u64 frac_rate64 = prate * cur.k;
+		s64 frac_rate64 = (s64)prate * cur.k;

-		postdiv = cur.p * 65535;
-		do_div(frac_rate64, postdiv);
-		rate64 += frac_rate64;
+		postdiv = cur.p * 65536;
+		rate64 += div_s64(frac_rate64, postdiv);
 	}
 	rate64 = rate64 >> cur.s;

--- a/drivers/clk/rockchip/clk-rk3576.c
+++ b/drivers/clk/rockchip/clk-rk3576.c
@ -79,13 +79,13 @@ static struct rockchip_pll_rate_table rk3576_pll_rates[] = {
 	RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
 	RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
 	RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
-	RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
+	RK3588_PLL_RATE(955520000, 3, 478, 2, -15730),
 	RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
 	RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
 	RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
 	RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
 	RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
-	RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
+	RK3588_PLL_RATE(785560000, 3, 393, 2, -14419),
 	RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
 	RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
 	RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
@ -315,6 +315,7 @@ PNAME(mux_100m_24m_lclk0_p)		= { "clk_cpll_div10", "xin24m", "lclk_asrc_src_0" }
 PNAME(mux_100m_24m_lclk1_p)		= { "clk_cpll_div10", "xin24m", "lclk_asrc_src_1" };
 PNAME(mux_150m_100m_50m_24m_p)		= { "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
 PNAME(mux_200m_100m_50m_24m_p)		= { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
+PNAME(mux_200m_150m_100m_24m_p)		= { "clk_gpll_div6", "clk_gpll_div8", "clk_cpll_div10", "xin24m" };
 PNAME(mux_400m_200m_100m_24m_p)		= { "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m" };
 PNAME(mux_500m_250m_100m_24m_p)		= { "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m" };
 PNAME(mux_600m_400m_300m_24m_p)		= { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m" };
@ -706,19 +707,19 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
 			RK3576_CLKGATE_CON(16), 0, GFLAGS),
 	GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0,
 			RK3576_CLKGATE_CON(16), 1, GFLAGS),
-	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_100m_24m_p, 0,
 			RK3576_CLKSEL_CON(70), 13, 2, MFLAGS,
 			RK3576_CLKGATE_CON(16), 2, GFLAGS),
-	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
+	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_100m_24m_p, 0,
 			RK3576_CLKSEL_CON(71), 0, 2, MFLAGS,
 			RK3576_CLKGATE_CON(16), 3, GFLAGS),
-	COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0,
+	COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_100m_24m_p, 0,
 			RK3576_CLKSEL_CON(71), 2, 2, MFLAGS,
 			RK3576_CLKGATE_CON(16), 4, GFLAGS),
-	COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0,
+	COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_100m_24m_p, 0,
 			RK3576_CLKSEL_CON(71), 4, 2, MFLAGS,
 			RK3576_CLKGATE_CON(16), 5, GFLAGS),
-	COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0,
+	COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_100m_24m_p, 0,
 			RK3576_CLKSEL_CON(71), 6, 2, MFLAGS,
 			RK3576_CLKGATE_CON(16), 6, GFLAGS),
 	GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@ -79,14 +79,14 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
 	RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
 	RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
 	RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
-	RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
+	RK3588_PLL_RATE(955520000, 3, 478, 2, -15730),
 	RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
 	RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
 	RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
 	RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
 	RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
 	RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
-	RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
+	RK3588_PLL_RATE(785560000, 3, 393, 2, -14419),
 	RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
 	RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
 	RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
@ -2102,7 +2102,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
 	COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
 			RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
 			RK3588_CLKGATE_CON(52), 11, GFLAGS),
-	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, 0,
 			RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3588_CLKGATE_CON(52), 12, GFLAGS),
 	COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p,
--- a/drivers/clk/rockchip/clk-rv1106.c
+++ b/drivers/clk/rockchip/clk-rv1106.c
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@ -635,10 +635,10 @@ struct rockchip_pll_rate_table {
 		};
 		struct {
 			/* for RK3588 */
-			unsigned int m;
-			unsigned int p;
-			unsigned int s;
-			unsigned int k;
+			unsigned int m;	/* main divider, 10 bit unsigned */
+			unsigned int p;	/* pre-divider, 6 bit unsigned */
+			unsigned int s;	/* scaler, 3 bit unsigned */
+			s16 k;		/* fractional part, 16 bit two's complement */
 		};
 	};
 };
--- a/include/dt-bindings/clock/rockchip,rv1106-cru.h
+++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h
@ -0,0 +1,306 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
+
+/* pll clocks */
+#define PLL_APLL		0
+#define PLL_DPLL		1
+#define PLL_CPLL		2
+#define PLL_GPLL		3
+#define ARMCLK			4
+
+/* clk (clocks) */
+#define PCLK_DDRPHY		5
+#define PCLK_DDR_ROOT		6
+#define PCLK_DDRMON		7
+#define CLK_TIMER_DDRMON	8
+#define PCLK_DDRC		9
+#define PCLK_DFICTRL		10
+#define ACLK_DDR_ROOT		11
+#define ACLK_SYS_SHRM		12
+#define HCLK_NPU_ROOT		13
+#define ACLK_NPU_ROOT		14
+#define PCLK_NPU_ROOT		15
+#define HCLK_RKNN		16
+#define ACLK_RKNN		17
+#define PCLK_ACODEC		18
+#define MCLK_ACODEC_TX		19
+#define CLK_CORE_CRYPTO		20
+#define CLK_PKA_CRYPTO		21
+#define ACLK_CRYPTO		22
+#define HCLK_CRYPTO		23
+#define ACLK_DECOM		24
+#define PCLK_DECOM		25
+#define DCLK_DECOM		26
+#define ACLK_DMAC		27
+#define PCLK_DSM		28
+#define MCLK_DSM		29
+#define CCLK_SRC_EMMC		30
+#define HCLK_EMMC		31
+#define PCLK_GPIO4		32
+#define DBCLK_GPIO4		33
+#define PCLK_I2C0		34
+#define CLK_I2C0		35
+#define PCLK_I2C2		36
+#define CLK_I2C2		37
+#define PCLK_I2C3		38
+#define CLK_I2C3		39
+#define PCLK_I2C4		40
+#define CLK_I2C4		41
+#define HCLK_I2S0		42
+#define PCLK_DFT2APB		43
+#define HCLK_IVE		44
+#define ACLK_IVE		45
+#define PCLK_PWM0_PERI		46
+#define CLK_PWM0_PERI		47
+#define CLK_CAPTURE_PWM0_PERI	48
+#define PCLK_PERI_ROOT		49
+#define ACLK_PERI_ROOT		50
+#define HCLK_PERI_ROOT		51
+#define CLK_TIMER_ROOT		52
+#define ACLK_BUS_ROOT		53
+#define HCLK_SFC		54
+#define SCLK_SFC		55
+#define PCLK_UART0		56
+#define CLK_PVTM_CORE		57
+#define PCLK_UART1		58
+#define CLK_CORE_MCU_RTC	59
+#define PCLK_PWM1_PERI		60
+#define CLK_PWM1_PERI		61
+#define CLK_CAPTURE_PWM1_PERI	62
+#define PCLK_PWM2_PERI		63
+#define CLK_PWM2_PERI		64
+#define CLK_CAPTURE_PWM2_PERI	65
+#define HCLK_BOOTROM		66
+#define HCLK_SAI		67
+#define MCLK_SAI		68
+#define PCLK_SARADC		69
+#define CLK_SARADC		70
+#define PCLK_SPI1		71
+#define CLK_SPI1		72
+#define PCLK_STIMER		73
+#define CLK_STIMER0		74
+#define CLK_STIMER1		75
+#define PCLK_TIMER		76
+#define CLK_TIMER0		77
+#define CLK_TIMER1		78
+#define CLK_TIMER2		79
+#define CLK_TIMER3		80
+#define CLK_TIMER4		81
+#define CLK_TIMER5		82
+#define HCLK_TRNG_NS		83
+#define HCLK_TRNG_S		84
+#define PCLK_UART2		85
+#define HCLK_CPU		86
+#define PCLK_UART3		87
+#define CLK_CORE_MCU		88
+#define PCLK_UART4		89
+#define PCLK_DDR_HWLP		90
+#define PCLK_UART5		91
+#define ACLK_USBOTG		92
+#define CLK_REF_USBOTG		93
+#define CLK_UTMI_USBOTG		94
+#define PCLK_USBPHY		95
+#define CLK_REF_USBPHY		96
+#define PCLK_WDT_NS		97
+#define TCLK_WDT_NS		98
+#define PCLK_WDT_S		99
+#define TCLK_WDT_S		100
+#define CLK_DDR_FAIL_SAFE	101
+#define XIN_OSC0_DIV		102
+#define CLK_DEEPSLOW		103
+#define PCLK_PMU_GPIO0		104
+#define DBCLK_PMU_GPIO0		105
+#define CLK_PMU			106
+#define PCLK_PMU		107
+#define PCLK_PMU_HP_TIMER	108
+#define CLK_PMU_HP_TIMER	109
+#define CLK_PMU_32K_HP_TIMER	110
+#define PCLK_I2C1		111
+#define CLK_I2C1		112
+#define PCLK_PMU_IOC		113
+#define PCLK_PMU_MAILBOX	114
+#define CLK_PMU_MCU		115
+#define CLK_PMU_MCU_RTC		116
+#define CLK_PMU_MCU_JTAG	117
+#define CLK_PVTM_PMU		118
+#define PCLK_PVTM_PMU		119
+#define CLK_REFOUT		120
+#define CLK_100M_PMU		121
+#define PCLK_PMU_ROOT		122
+#define HCLK_PMU_ROOT		123
+#define HCLK_PMU_SRAM		124
+#define PCLK_PMU_WDT		125
+#define TCLK_PMU_WDT		126
+#define CLK_DFICTRL		127
+#define CLK_DDRMON		128
+#define CLK_DDR_PHY		129
+#define ACLK_DDRC		130
+#define CLK_CORE_DDRC_SRC	131
+#define CLK_CORE_DDRC		132
+#define CLK_50M_SRC		133
+#define CLK_100M_SRC		134
+#define CLK_150M_SRC		135
+#define CLK_200M_SRC		136
+#define CLK_250M_SRC		137
+#define CLK_300M_SRC		138
+#define CLK_339M_SRC		139
+#define CLK_400M_SRC		140
+#define CLK_450M_SRC		141
+#define CLK_500M_SRC		142
+#define CLK_I2S0_8CH_TX_SRC	143
+#define CLK_I2S0_8CH_TX_FRAC	144
+#define CLK_I2S0_8CH_TX		145
+#define CLK_I2S0_8CH_RX_SRC	146
+#define CLK_I2S0_8CH_RX_FRAC	147
+#define CLK_I2S0_8CH_RX		148
+#define I2S0_8CH_MCLKOUT	149
+#define MCLK_I2S0_8CH_RX	150
+#define MCLK_I2S0_8CH_TX	151
+#define CLK_REF_MIPI0_SRC	152
+#define CLK_REF_MIPI0_FRAC	153
+#define CLK_REF_MIPI0_OUT	154
+#define CLK_REF_MIPI1_SRC	155
+#define CLK_REF_MIPI1_FRAC	156
+#define MCLK_REF_MIPI0		157
+#define MCLK_REF_MIPI1		158
+#define CLK_REF_MIPI0		159
+#define CLK_REF_MIPI1		160
+#define CLK_UART0_SRC		161
+#define CLK_UART0_FRAC		162
+#define CLK_UART0		163
+#define SCLK_UART0		164
+#define CLK_UART1_SRC		165
+#define CLK_UART1_FRAC		166
+#define CLK_UART1		167
+#define SCLK_UART1		168
+#define CLK_UART2_SRC		169
+#define CLK_UART2_FRAC		170
+#define CLK_UART2		171
+#define SCLK_UART2		172
+#define CLK_UART3_SRC		173
+#define CLK_UART3_FRAC		174
+#define CLK_UART3		175
+#define SCLK_UART3		176
+#define CLK_UART4_SRC		177
+#define CLK_UART4_FRAC		178
+#define CLK_UART4		179
+#define SCLK_UART4		180
+#define CLK_UART5_SRC		181
+#define CLK_UART5_FRAC		182
+#define CLK_UART5		183
+#define SCLK_UART5		184
+#define CLK_VICAP_M0_SRC	185
+#define CLK_VICAP_M0_FRAC	186
+#define CLK_VICAP_M0		187
+#define SCLK_VICAP_M0		188
+#define CLK_VICAP_M1_SRC	189
+#define CLK_VICAP_M1_FRAC	190
+#define CLK_VICAP_M1		191
+#define SCLK_VICAP_M1		192
+#define DCLK_VOP_SRC		193
+#define PCLK_CRU		194
+#define PCLK_TOP_ROOT		195
+#define PCLK_SPI0		196
+#define CLK_SPI0		197
+#define SCLK_IN_SPI0		198
+#define CLK_UART_DETN_FLT	199
+#define HCLK_VEPU		200
+#define ACLK_VEPU		201
+#define CLK_CORE_VEPU		202
+#define CLK_CORE_VEPU_DVBM	203
+#define PCLK_GPIO1		204
+#define DBCLK_GPIO1		205
+#define HCLK_VEPU_PP		206
+#define ACLK_VEPU_PP		207
+#define HCLK_VEPU_ROOT		208
+#define ACLK_VEPU_COM_ROOT	209
+#define ACLK_VEPU_ROOT		210
+#define PCLK_VEPU_ROOT		211
+#define PCLK_VICAP_VEPU		212
+#define PCLK_CSIHOST0		213
+#define CLK_RXBYTECLKHS_0	214
+#define PCLK_CSIHOST1		215
+#define CLK_RXBYTECLKHS_1	216
+#define PCLK_GPIO3		217
+#define DBCLK_GPIO3		218
+#define HCLK_ISP3P2		219
+#define ACLK_ISP3P2		220
+#define CLK_CORE_ISP3P2		221
+#define PCLK_MIPICSIPHY		222
+#define CCLK_SRC_SDMMC		223
+#define HCLK_SDMMC		224
+#define CLK_SDMMC_DETN_FLT	225
+#define HCLK_VI_ROOT		226
+#define ACLK_VI_ROOT		227
+#define PCLK_VI_ROOT		228
+#define PCLK_VI_RTC_ROOT	229
+#define PCLK_VI_RTC_TEST	230
+#define PCLK_VI_RTC_PHY		231
+#define DCLK_VICAP		232
+#define PCLK_VICAP		233
+#define ACLK_VICAP		234
+#define HCLK_VICAP		235
+#define I0CLK_VICAP		236
+#define I1CLK_VICAP		237
+#define RX0PCLK_VICAP		238
+#define RX1PCLK_VICAP		239
+#define ISP0CLK_VICAP		240
+#define PCLK_GPIO2		241
+#define DBCLK_GPIO2		242
+#define ACLK_MAC		243
+#define PCLK_MAC		244
+#define CLK_GMAC0_50M_O		245
+#define CLK_GMAC0_TX_50M_O	246
+#define CLK_GMAC0_REF_50M	247
+#define CLK_GMAC0_TX_50M	248
+#define CLK_GMAC0_RX_50M	249
+#define ACLK_MAC_ROOT		250
+#define CLK_MACPHY		251
+#define CLK_OTPC_ARB		252
+#define PCLK_OTPC_NS		253
+#define CLK_SBPI_OTPC_NS	254
+#define CLK_USER_OTPC_NS	255
+#define PCLK_OTPC_S		256
+#define CLK_SBPI_OTPC_S		257
+#define CLK_USER_OTPC_S		258
+#define PCLK_OTP_MASK		259
+#define CLK_PMC_OTP		260
+#define HCLK_RGA2E		261
+#define ACLK_RGA2E		262
+#define CLK_CORE_RGA2E		263
+#define CCLK_SRC_SDIO		264
+#define HCLK_SDIO		265
+#define PCLK_TSADC		266
+#define CLK_TSADC		267
+#define CLK_TSADC_TSEN		268
+#define ACLK_VO_ROOT		269
+#define HCLK_VO_ROOT		270
+#define PCLK_VO_ROOT		271
+#define ACLK_VOP_ROOT		272
+#define HCLK_VOP		273
+#define DCLK_VOP		274
+#define ACLK_VOP		275
+#define CLK_RTC_32K		276
+#define PCLK_MAILBOX		277
+
+/* mmc phase clocks */
+#define SCLK_EMMC_DRV		278
+#define SCLK_EMMC_SAMPLE	279
+#define SCLK_SDMMC_DRV		280
+#define SCLK_SDMMC_SAMPLE	281
+#define SCLK_SDIO_DRV		282
+#define SCLK_SDIO_SAMPLE	283
+
+/* internal clocks */
+#define XIN_OSC0_HALF		284
+#define PCLK_DBG		285
+#define PCLK_CPU_ROOT		286
+#define CLK_RTC32K_FRAC		287
+
+#endif