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Qualcomm clock updates for v7.3

Browse Source 
Add global, TCSR, RPMh, and video clock controller support for Maili.
 Add global, RPM, GPU, display, and audio core clock controller support for
 Shikra. Add display and graphics clock controllers for Nord.
 
 Add Glymur camera and EVA clock controllers, the IPQ9650 REFGEN clocks, and
 Hawi video clock controller support. Extend the IPQ5210 APSS PLL and RPM
 clock support for Agatti.
 
 Enable runtime PM and regulator-backed reference clock handling where needed.
 Update QCM2290 clock and power-domain handling, critical clock definitions,
 and arm architecture Kconfig defaults.
 
 Correct MDM9607, MSM8916, MSM8939, SM6115, QCS8300, Kaanapali, and Glymur
 clock and power-domain handling. Improve GDSC error propagation and teardown.
 
 Update bindings for the added controllers and required power and OPP
 properties.
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Merge tag 'qcom-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

Add global, TCSR, RPMh, and video clock controller support for Maili.
Add global, RPM, GPU, display, and audio core clock controller support for
Shikra. Add display and graphics clock controllers for Nord.

Add Glymur camera and EVA clock controllers, the IPQ9650 REFGEN clocks, and
Hawi video clock controller support. Extend the IPQ5210 APSS PLL and RPM
clock support for Agatti.

Enable runtime PM and regulator-backed reference clock handling where needed.
Update QCM2290 clock and power-domain handling, critical clock definitions,
and arm architecture Kconfig defaults.

Correct MDM9607, MSM8916, MSM8939, SM6115, QCS8300, Kaanapali, and Glymur
clock and power-domain handling. Improve GDSC error propagation and teardown.

Update bindings for the added controllers and required power and OPP
properties.

* tag 'qcom-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (94 commits)
  clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra
  clk: qcom: Return expected ENOMEM error on dynamic allocation failure
  clk: qcom: apss-ipq-pll: Add IPQ5210 support
  dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible
  clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
  dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller
  dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller
  dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller
  clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable
  clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe
  clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
  clk: qcom: gpucc-qcm2290: Drop pm_clk handling
  clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values
  clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
  clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs
  clk: qcom: dispcc-qcm2290: Enable runtime PM support
  clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model
  clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
  dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property
  clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
  ...
This commit is contained in:
Stephen Boyd 2026-08-11 23:07:41 -07:00
commit 79b64c7476
73 changed files with 17313 additions and 887 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View File

@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,ipq5018-a53pll
- qcom,ipq5210-a53pll
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll

18
Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml
View File

@ -25,19 +25,33 @@ properties:
enum:
- qcom,gcc-mdm9607
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
unevaluatedProperties: false
examples:
- |
clock-controller@900000 {
clock-controller@1800000 {
compatible = "qcom,gcc-mdm9607";
reg = <0x900000 0x4000>;
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo_board>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
};
...

72
Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm EVA Clock & Reset Controller on Glymur SoC
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm EVA clock control module which supports the clocks, resets and
power domains for the EVA instances on Glymur SoC.
See also:
- include/dt-bindings/clock/qcom,glymur-evacc.h
properties:
compatible:
const: qcom,glymur-evacc
clocks:
items:
- description: Interface clock from GCC
- description: Board XO source
- description: Sleep clock source
power-domains:
items:
- description: MMCX power domain
- description: MXC power domain
required-opps:
description:
Required OPP nodes for the MMCX and MXC power domains.
items:
- description: MMCX performance point
- description: MXC performance point
required:
- compatible
- clocks
- power-domains
- required-opps
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,glymur-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ab00000 {
compatible = "qcom,glymur-evacc";
reg = <0x0ab00000 0x10000>;
clocks = <&gcc GCC_EVA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

8
Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml
View File

@ -65,9 +65,15 @@ properties:
- description: USB4 PHY 2 pcie pipe clock source
- description: USB4 PHY 2 Max pipe clock source
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -78,6 +84,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,glymur-gcc";
reg = <0x100000 0x1f9000>;
@ -113,6 +120,7 @@ examples:
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

146
Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml Normal file
View File

@ -0,0 +1,146 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm TCSR Clock Controller on Glymur
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on Glymur
See also:
- include/dt-bindings/clock/qcom,glymur-tcsr.h
properties:
compatible:
items:
- enum:
- qcom,glymur-tcsr
- qcom,mahua-tcsr
- const: syscon
clocks:
items:
- description: TCXO pad clock
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
vdda-qrefrpt0-0p9-supply: true
vdda-qrefrpt1-0p9-supply: true
vdda-qrefrpt2-0p9-supply: true
vdda-qrefrpt3-0p9-supply: true
vdda-qrefrpt4-0p9-supply: true
vdda-qrefrpt5-0p9-supply: true
vdda-qrefrx0-0p9-supply: true
vdda-qrefrx1-0p9-supply: true
vdda-qrefrx2-0p9-supply: true
vdda-qrefrx3-0p9-supply: true
vdda-qrefrx4-0p9-supply: true
vdda-qrefrx5-0p9-supply: true
vdda-qreftx0-0p9-supply: true
vdda-qreftx0-1p2-supply: true
vdda-qreftx1-0p9-supply: true
vdda-refgen3-0p9-supply: true
vdda-refgen3-1p2-supply: true
vdda-refgen4-0p9-supply: true
vdda-refgen4-1p2-supply: true
allOf:
- if:
properties:
compatible:
contains:
const: qcom,glymur-tcsr
then:
required:
- vdda-qrefrpt0-0p9-supply
- vdda-qrefrpt1-0p9-supply
- vdda-qrefrpt2-0p9-supply
- vdda-qrefrpt3-0p9-supply
- vdda-qrefrpt4-0p9-supply
- vdda-qrefrx0-0p9-supply
- vdda-qrefrx1-0p9-supply
- vdda-qrefrx2-0p9-supply
- vdda-qrefrx4-0p9-supply
- vdda-qrefrx5-0p9-supply
- vdda-qreftx0-0p9-supply
- vdda-qreftx0-1p2-supply
- vdda-qreftx1-0p9-supply
- vdda-refgen3-0p9-supply
- vdda-refgen3-1p2-supply
- vdda-refgen4-0p9-supply
- vdda-refgen4-1p2-supply
- if:
properties:
compatible:
contains:
const: qcom,mahua-tcsr
then:
required:
- vdda-qrefrpt0-0p9-supply
- vdda-qrefrpt1-0p9-supply
- vdda-qrefrpt2-0p9-supply
- vdda-qrefrpt3-0p9-supply
- vdda-qrefrpt4-0p9-supply
- vdda-qrefrpt5-0p9-supply
- vdda-qrefrx1-0p9-supply
- vdda-qrefrx2-0p9-supply
- vdda-qrefrx3-0p9-supply
- vdda-qreftx1-0p9-supply
- vdda-refgen3-0p9-supply
- vdda-refgen3-1p2-supply
required:
- compatible
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@1fd5000 {
compatible = "qcom,glymur-tcsr", "syscon";
reg = <0x0 0x1fd5000 0x0 0x21000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
vdda-qrefrpt0-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt1-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt2-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt3-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt4-0p9-supply = <&vreg_l1a>;
vdda-qrefrx0-0p9-supply = <&vreg_l1a>;
vdda-qrefrx1-0p9-supply = <&vreg_l1a>;
vdda-qrefrx2-0p9-supply = <&vreg_l1a>;
vdda-qrefrx4-0p9-supply = <&vreg_l1a>;
vdda-qrefrx5-0p9-supply = <&vreg_l1a>;
vdda-qreftx0-0p9-supply = <&vreg_l1a>;
vdda-qreftx0-1p2-supply = <&vreg_l2a>;
vdda-qreftx1-0p9-supply = <&vreg_l1a>;
vdda-refgen3-0p9-supply = <&vreg_l1a>;
vdda-refgen3-1p2-supply = <&vreg_l2a>;
vdda-refgen4-0p9-supply = <&vreg_l1a>;
vdda-refgen4-1p2-supply = <&vreg_l2a>;
};
};
...

11
Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml
View File

@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Hawi
maintainers:
- Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Hawi.
domains on Hawi and Maili.
See also: include/dt-bindings/clock/qcom,hawi-gcc.h
See also:
include/dt-bindings/clock/qcom,hawi-gcc.h
include/dt-bindings/clock/qcom,maili-gcc.h
properties:
compatible:
const: qcom,hawi-gcc
enum:
- qcom,hawi-gcc
- qcom,maili-gcc
clocks:
items:

15
Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
View File

@ -17,7 +17,13 @@ description: |
properties:
compatible:
const: qcom,qcm2290-dispcc
oneOf:
- items:
- enum:
- qcom,shikra-dispcc
- const: qcom,qcm2290-dispcc
- enum:
- qcom,qcm2290-dispcc
clocks:
items:
@ -37,10 +43,15 @@ properties:
- const: dsi0_phy_pll_out_byteclk
- const: dsi0_phy_pll_out_dsiclk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -53,6 +64,7 @@ examples:
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@5f00000 {
compatible = "qcom,qcm2290-dispcc";
reg = <0x5f00000 0x20000>;
@ -68,6 +80,7 @@ examples:
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk";
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

4
Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml
View File

@ -18,7 +18,9 @@ description: |
properties:
compatible:
const: qcom,qcm2290-gpucc
enum:
- qcom,qcm2290-gpucc
- qcom,shikra-gpucc
reg:
maxItems: 1

65
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
View File

@ -21,35 +21,41 @@ description: |
properties:
compatible:
items:
- enum:
- qcom,rpmcc-apq8060
- qcom,rpmcc-apq8064
- qcom,rpmcc-ipq806x
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8937
- qcom,rpmcc-msm8940
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
- qcom,rpmcc-msm8992
- qcom,rpmcc-msm8994
- qcom,rpmcc-msm8996
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
- qcom,rpmcc-sm6375
- const: qcom,rpmcc
oneOf:
- items:
- enum:
- qcom,rpmcc-apq8060
- qcom,rpmcc-apq8064
- qcom,rpmcc-ipq806x
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8937
- qcom,rpmcc-msm8940
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
- qcom,rpmcc-msm8992
- qcom,rpmcc-msm8994
- qcom,rpmcc-msm8996
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
- qcom,rpmcc-sm6375
- const: qcom,rpmcc
- items:
- enum:
- qcom,rpmcc-shikra
- const: qcom,rpmcc-qcm2290
- const: qcom,rpmcc
'#clock-cells':
const: 1
@ -126,6 +132,7 @@ allOf:
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-shikra
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125

65
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -16,36 +16,41 @@ description: |
properties:
compatible:
enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,hawi-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
- qcom,sar2130p-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
- qcom,sc8280xp-rpmh-clk
- qcom,sdm670-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,sm8750-rpmh-clk
- qcom,x1e80100-rpmh-clk
oneOf:
- enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,hawi-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
- qcom,sar2130p-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
- qcom,sc8280xp-rpmh-clk
- qcom,sdm670-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,sm8750-rpmh-clk
- qcom,x1e80100-rpmh-clk
- items:
- enum:
- qcom,maili-rpmh-clk
- const: qcom,hawi-rpmh-clk
clocks:
maxItems: 1

55
Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml Normal file
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@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Audio Core Clock Controller for Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
description: |
Audio core clock control module provides the clocks on Qualcomm Shikra
SoC platform.
See also:
- include/dt-bindings/clock/qcom,shikra-audiocorecc.h
properties:
compatible:
const: qcom,shikra-audiocorecc
clocks:
items:
- description: Board XO source
- description: Board sleep clock
- description: Audio ref clock source
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
clock-controller@a0a0000 {
compatible = "qcom,shikra-audiocorecc";
reg = <0x0a0a0000 0x10000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&aud_ref_clk_src>;
#clock-cells = <1>;
};
...

70
Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml Normal file
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@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Global Clock & Reset Controller on Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Global clock control module provides the clocks, resets and power
domains on Qualcomm Shikra SoC platform.
See also: include/dt-bindings/clock/qcom,shikra-gcc.h
properties:
compatible:
const: qcom,shikra-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: EMAC0 sgmiiphy mac rclk source
- description: EMAC0 sgmiiphy mac tclk source
- description: EMAC1 sgmiiphy mac rclk source
- description: EMAC1 sgmiiphy mac tclk source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@1400000 {
compatible = "qcom,shikra-gcc";
reg = <0x01400000 0x1f0000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&emac0_sgmiiphy_rclk>,
<&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>,
<&pcie_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

12
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -70,13 +70,11 @@ allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
not:
contains:
enum:
- qcom,sm8475-camcc
- qcom,sm8650-camcc
then:
required:
- required-opps

4
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -18,6 +18,8 @@ description: |
include/dt-bindings/clock/qcom,glymur-gpucc.h
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,nord-gpu2cc.h
include/dt-bindings/clock/qcom,nord-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
include/dt-bindings/clock/qcom,sm4450-gpucc.h
include/dt-bindings/clock/qcom,sm8450-gpucc.h
@ -33,6 +35,8 @@ properties:
- qcom,glymur-gpucc
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,nord-gpu2cc
- qcom,nord-gpucc
- qcom,sar2130p-gpucc
- qcom,sm4450-gpucc
- qcom,sm8450-gpucc

17
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@ -16,7 +16,9 @@ description: |
See also:
include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,hawi-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,maili-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@ -26,7 +28,9 @@ properties:
compatible:
enum:
- qcom,glymur-videocc
- qcom,hawi-videocc
- qcom,kaanapali-videocc
- qcom,maili-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
@ -65,14 +69,11 @@ allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
- qcom,x1p42100-videocc
not:
contains:
enum:
- qcom,sm8475-videocc
- qcom,sm8650-videocc
then:
required:
- required-opps

3
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -16,6 +16,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,nord-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
@ -25,6 +26,8 @@ properties:
compatible:
enum:
- qcom,kaanapali-dispcc
- qcom,nord-dispcc0
- qcom,nord-dispcc1
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc

34
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -16,7 +16,6 @@ description: |
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,hawi-tcsrcc.h
- include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
@ -25,20 +24,25 @@ description: |
properties:
compatible:
items:
- enum:
- qcom,eliza-tcsr
- qcom,glymur-tcsr
- qcom,hawi-tcsrcc
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon
oneOf:
- items:
- enum:
- qcom,eliza-tcsr
- qcom,hawi-tcsrcc
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon
- items:
- enum:
- qcom,maili-tcsrcc
- const: qcom,hawi-tcsrcc
- const: syscon
clocks:
items:

3
Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
View File

@ -8,12 +8,14 @@ title: Qualcomm Camera Clock & Reset Controller on x1e80100
maintainers:
- Bryan O'Donoghue <bryan.odonoghue@linaro.org>
- Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on x1e80100.
See also:
include/dt-bindings/clock/qcom,glymur-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
@ -22,6 +24,7 @@ allOf:
properties:
compatible:
enum:
- qcom,glymur-camcc
- qcom,x1e80100-camcc
- qcom,x1p42100-camcc

42
Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml Normal file
View File

@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/qcom,shikra-audiocore-csr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Audio Core CSR for Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
description: |
Audio Core CSR module provides the resets on Qualcomm Shikra SoC platform.
See also:
- include/dt-bindings/clock/qcom,shikra-audiocorecc.h
properties:
compatible:
const: qcom,shikra-audiocore-csr
reg:
maxItems: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
- |
reset-controller@a0b4000 {
compatible = "qcom,shikra-audiocore-csr";
reg = <0x0a0b4000 0x1000>;
#reset-cells = <1>;
};
...

274
drivers/clk/qcom/Kconfig
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File diff suppressed because it is too large Load Diff

9
drivers/clk/qcom/Makefile
View File

@ -8,6 +8,7 @@ clk-qcom-y += clk-pll.o
clk-qcom-y += clk-rcg.o
clk-qcom-y += clk-rcg2.o
clk-qcom-y += clk-branch.o
clk-qcom-y += clk-ref.o
clk-qcom-y += clk-regmap-divider.o
clk-qcom-y += clk-regmap-mux.o
clk-qcom-y += clk-regmap-mux-div.o
@ -24,21 +25,29 @@ obj-$(CONFIG_CLK_ELIZA_DISPCC) += dispcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_GCC) += gcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o
obj-$(CONFIG_CLK_HAWI_GCC) += gcc-hawi.o
obj-$(CONFIG_CLK_HAWI_TCSRCC) += tcsrcc-hawi.o
obj-$(CONFIG_CLK_HAWI_VIDEOCC) += videocc-hawi.o
obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
obj-$(CONFIG_CLK_MAILI_VIDEOCC) += videocc-maili.o
obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o
obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o
obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o
obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o

19
drivers/clk/qcom/apss-ipq-pll.c
View File

@ -79,6 +79,18 @@ static const struct alpha_pll_config ipq5018_pll_config = {
.test_ctl_hi_val = 0x00400003,
};
static const struct alpha_pll_config ipq5210_pll_config = {
.l = 0x22,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
.aux2_output_mask = BIT(2),
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.test_ctl_val = 0x0,
.test_ctl_hi_val = 0x400003,
};
/* 1.080 GHz configuration */
static const struct alpha_pll_config ipq5332_pll_config = {
.l = 0x2d,
@ -140,6 +152,12 @@ static const struct apss_pll_data ipq5018_pll_data = {
.pll_config = &ipq5018_pll_config,
};
static const struct apss_pll_data ipq5210_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq5210_pll_config,
};
static const struct apss_pll_data ipq5332_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
@ -207,6 +225,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
{ .compatible = "qcom,ipq5210-a53pll", .data = &ipq5210_pll_data },
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },

810
drivers/clk/qcom/audiocorecc-shikra.c Normal file
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@ -0,0 +1,810 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_AUD_REF_CLK_SRC,
};
enum {
P_AUD_REF_CLK_SRC,
P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX,
P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2,
P_BI_TCXO,
P_SLEEP_CLK,
};
static const struct pll_vco spark_vco[] = {
{ 500000000, 1000000000, 2 },
};
/* 614.4 MHz Configuration */
static const struct alpha_pll_config audio_core_cc_dig_pll_config = {
.l = 0x20,
.alpha = 0x0,
.vco_val = BIT(21),
.post_div_val = 0x28100,
.post_div_mask = GENMASK(17, 8),
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.aux2_output_mask = BIT(2),
.config_ctl_val = 0x4001055b,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll audio_core_cc_dig_pll = {
.offset = 0x0,
.config = &audio_core_cc_dig_pll_config,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_dig_pll",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data) {
.name = "audio_core_cc_dig_pll_out_aux",
.parent_data = &(const struct clk_parent_data) {
.hw = &audio_core_cc_dig_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "audio_core_cc_dig_pll_out_aux2",
.parent_data = &(const struct clk_parent_data) {
.hw = &audio_core_cc_dig_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static const struct parent_map audio_core_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_AUD_REF_CLK_SRC, 1 },
{ P_SLEEP_CLK, 2 },
{ P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4 },
{ P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 6 },
};
static const struct clk_parent_data audio_core_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_AUD_REF_CLK_SRC },
{ .index = DT_SLEEP_CLK },
{ .hw = &audio_core_cc_dig_pll_out_aux.hw },
{ .hw = &audio_core_cc_dig_pll_out_aux2.hw },
};
static const struct freq_tbl ftbl_audio_core_cc_aif_if0_clk_src[] = {
F(240000, P_BI_TCXO, 10, 1, 8),
F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32),
F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16),
F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16),
F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8),
F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8),
F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4),
F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4),
F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2),
F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2),
F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
{ }
};
static struct clk_rcg2 audio_core_cc_aif_if0_clk_src = {
.cmd_rcgr = 0x104c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if0_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 audio_core_cc_aif_if1_clk_src = {
.cmd_rcgr = 0x10b0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if1_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 audio_core_cc_aif_if2_clk_src = {
.cmd_rcgr = 0x1114,
.mnd_width = 16,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if2_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_audio_core_cc_aif_if3_clk_src[] = {
F(240000, P_BI_TCXO, 10, 1, 8),
F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32),
F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16),
F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16),
F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8),
F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8),
F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4),
F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4),
F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2),
F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2),
F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
F(49152000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 audio_core_cc_aif_if3_clk_src = {
.cmd_rcgr = 0x1178,
.mnd_width = 16,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aif_if3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if3_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_audio_core_cc_aud_dma_clk_src[] = {
F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0),
F(102400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 3, 0, 0),
F(153600000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 2, 0, 0),
F(307200000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 1, 0, 0),
{ }
};
static struct clk_rcg2 audio_core_cc_aud_dma_clk_src = {
.cmd_rcgr = 0x1028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aud_dma_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aud_dma_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_audio_core_cc_bus_clk_src[] = {
F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0),
F(76800000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 4, 0, 0),
{ }
};
static struct clk_rcg2 audio_core_cc_bus_clk_src = {
.cmd_rcgr = 0x1008,
.mnd_width = 0,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_bus_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_bus_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 audio_core_cc_ext_mclka_clk_src = {
.cmd_rcgr = 0x123c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_ext_mclka_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 audio_core_cc_ext_mclkb_clk_src = {
.cmd_rcgr = 0x125c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_ext_mclkb_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_audio_core_cc_lpaif_pcmoe_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(15360000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 8, 0, 0),
F(30720000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4, 0, 0),
F(61440000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2, 0, 0),
{ }
};
static struct clk_rcg2 audio_core_cc_lpaif_pcmoe_clk_src = {
.cmd_rcgr = 0x12ac,
.mnd_width = 8,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_lpaif_pcmoe_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_lpaif_pcmoe_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_audio_core_cc_tx_mclk_rcg_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
{ }
};
static struct clk_rcg2 audio_core_cc_tx_mclk_rcg_clk_src = {
.cmd_rcgr = 0x127c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = audio_core_cc_parent_map_0,
.freq_tbl = ftbl_audio_core_cc_tx_mclk_rcg_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_tx_mclk_rcg_clk_src",
.parent_data = audio_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div audio_core_cc_cdiv_tx_mclk_div_clk_src = {
.reg = 0x129c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_cdiv_tx_mclk_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch audio_core_cc_aif_if0_ebit_clk = {
.halt_reg = 0x1068,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if0_ebit_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if0_ibit_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if0_ibit_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_aif_if0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if1_ebit_clk = {
.halt_reg = 0x10cc,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if1_ebit_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if1_ibit_clk = {
.halt_reg = 0x10c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if1_ibit_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_aif_if1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if2_ebit_clk = {
.halt_reg = 0x1130,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if2_ebit_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if2_ibit_clk = {
.halt_reg = 0x112c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x112c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if2_ibit_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_aif_if2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if3_ebit_clk = {
.halt_reg = 0x1194,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1194,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if3_ebit_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aif_if3_ibit_clk = {
.halt_reg = 0x1190,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1190,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aif_if3_ibit_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_aif_if3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aud_dma_clk = {
.halt_reg = 0x1040,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aud_dma_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_aud_dma_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_aud_dma_mem_clk = {
.halt_reg = 0x1044,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1044,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_aud_dma_mem_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_aud_dma_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_bus_clk = {
.halt_reg = 0x1020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_bus_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_bus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch audio_core_cc_ext_mclka_out_clk = {
.halt_reg = 0x1254,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1254,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_ext_mclka_out_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_ext_mclka_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_ext_mclkb_out_clk = {
.halt_reg = 0x1274,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1274,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_ext_mclkb_out_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_ext_mclkb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_im_sleep_clk = {
.halt_reg = 0x12cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_im_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_lpaif_pcmoe_clk = {
.halt_reg = 0x12c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12c4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_lpaif_pcmoe_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_lpaif_pcmoe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_rx_mclk_2x_clk = {
.halt_reg = 0x1298,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1298,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_rx_mclk_2x_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_rx_mclk_clk = {
.halt_reg = 0x12a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_rx_mclk_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_sampling_clk = {
.halt_reg = 0x1000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_sampling_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_tx_mclk_2x_clk = {
.halt_reg = 0x1294,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1294,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_tx_mclk_2x_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch audio_core_cc_tx_mclk_clk = {
.halt_reg = 0x12a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "audio_core_cc_tx_mclk_clk",
.parent_hws = (const struct clk_hw*[]) {
&audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *audio_core_cc_shikra_hws[] = {
[AUDIO_CORE_CC_DIG_PLL_OUT_AUX] = &audio_core_cc_dig_pll_out_aux.hw,
[AUDIO_CORE_CC_DIG_PLL_OUT_AUX2] = &audio_core_cc_dig_pll_out_aux2.hw,
};
static struct clk_regmap *audio_core_cc_shikra_clocks[] = {
[AUDIO_CORE_CC_AIF_IF0_CLK_SRC] = &audio_core_cc_aif_if0_clk_src.clkr,
[AUDIO_CORE_CC_AIF_IF0_EBIT_CLK] = &audio_core_cc_aif_if0_ebit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF0_IBIT_CLK] = &audio_core_cc_aif_if0_ibit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF1_CLK_SRC] = &audio_core_cc_aif_if1_clk_src.clkr,
[AUDIO_CORE_CC_AIF_IF1_EBIT_CLK] = &audio_core_cc_aif_if1_ebit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF1_IBIT_CLK] = &audio_core_cc_aif_if1_ibit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF2_CLK_SRC] = &audio_core_cc_aif_if2_clk_src.clkr,
[AUDIO_CORE_CC_AIF_IF2_EBIT_CLK] = &audio_core_cc_aif_if2_ebit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF2_IBIT_CLK] = &audio_core_cc_aif_if2_ibit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF3_CLK_SRC] = &audio_core_cc_aif_if3_clk_src.clkr,
[AUDIO_CORE_CC_AIF_IF3_EBIT_CLK] = &audio_core_cc_aif_if3_ebit_clk.clkr,
[AUDIO_CORE_CC_AIF_IF3_IBIT_CLK] = &audio_core_cc_aif_if3_ibit_clk.clkr,
[AUDIO_CORE_CC_AUD_DMA_CLK] = &audio_core_cc_aud_dma_clk.clkr,
[AUDIO_CORE_CC_AUD_DMA_CLK_SRC] = &audio_core_cc_aud_dma_clk_src.clkr,
[AUDIO_CORE_CC_AUD_DMA_MEM_CLK] = &audio_core_cc_aud_dma_mem_clk.clkr,
[AUDIO_CORE_CC_BUS_CLK] = &audio_core_cc_bus_clk.clkr,
[AUDIO_CORE_CC_BUS_CLK_SRC] = &audio_core_cc_bus_clk_src.clkr,
[AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr,
[AUDIO_CORE_CC_DIG_PLL] = &audio_core_cc_dig_pll.clkr,
[AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC] = &audio_core_cc_ext_mclka_clk_src.clkr,
[AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK] = &audio_core_cc_ext_mclka_out_clk.clkr,
[AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC] = &audio_core_cc_ext_mclkb_clk_src.clkr,
[AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK] = &audio_core_cc_ext_mclkb_out_clk.clkr,
[AUDIO_CORE_CC_IM_SLEEP_CLK] = &audio_core_cc_im_sleep_clk.clkr,
[AUDIO_CORE_CC_LPAIF_PCMOE_CLK] = &audio_core_cc_lpaif_pcmoe_clk.clkr,
[AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC] = &audio_core_cc_lpaif_pcmoe_clk_src.clkr,
[AUDIO_CORE_CC_RX_MCLK_2X_CLK] = &audio_core_cc_rx_mclk_2x_clk.clkr,
[AUDIO_CORE_CC_RX_MCLK_CLK] = &audio_core_cc_rx_mclk_clk.clkr,
[AUDIO_CORE_CC_SAMPLING_CLK] = &audio_core_cc_sampling_clk.clkr,
[AUDIO_CORE_CC_TX_MCLK_2X_CLK] = &audio_core_cc_tx_mclk_2x_clk.clkr,
[AUDIO_CORE_CC_TX_MCLK_CLK] = &audio_core_cc_tx_mclk_clk.clkr,
[AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC] = &audio_core_cc_tx_mclk_rcg_clk_src.clkr,
};
static struct clk_alpha_pll *audio_core_cc_shikra_plls[] = {
&audio_core_cc_dig_pll,
};
static const struct qcom_cc_driver_data audio_core_cc_shikra_driver_data = {
.alpha_plls = audio_core_cc_shikra_plls,
.num_alpha_plls = ARRAY_SIZE(audio_core_cc_shikra_plls),
};
static const struct regmap_config audio_core_cc_shikra_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x305c,
.fast_io = true,
};
static const struct qcom_reset_map audio_core_csr_shikra_resets[] = {
[AUDIO_CORE_CSR_RX_SWR_CGCR] = { 0x1c, 1 },
[AUDIO_CORE_CSR_TX_SWR_CGCR] = { 0x30, 1 },
};
static const struct regmap_config audio_core_csr_shikra_regmap_config = {
.name = "audio_core_cc_shikra_reset",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.max_register = 0x34,
};
static const struct qcom_cc_desc audio_core_csr_shikra_desc = {
.config = &audio_core_csr_shikra_regmap_config,
.resets = audio_core_csr_shikra_resets,
.num_resets = ARRAY_SIZE(audio_core_csr_shikra_resets),
};
static const struct qcom_cc_desc audio_core_cc_shikra_desc = {
.config = &audio_core_cc_shikra_regmap_config,
.clk_hws = audio_core_cc_shikra_hws,
.num_clk_hws = ARRAY_SIZE(audio_core_cc_shikra_hws),
.clks = audio_core_cc_shikra_clocks,
.num_clks = ARRAY_SIZE(audio_core_cc_shikra_clocks),
.driver_data = &audio_core_cc_shikra_driver_data,
};
static const struct of_device_id audio_core_cc_shikra_match_table[] = {
{ .compatible = "qcom,shikra-audiocorecc", .data = &audio_core_cc_shikra_desc },
{ .compatible = "qcom,shikra-audiocore-csr", .data = &audio_core_csr_shikra_desc },
{ }
};
MODULE_DEVICE_TABLE(of, audio_core_cc_shikra_match_table);
static int audio_core_cc_shikra_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
desc = device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
return qcom_cc_probe(pdev, desc);
}
static struct platform_driver audio_core_cc_shikra_driver = {
.probe = audio_core_cc_shikra_probe,
.driver = {
.name = "audiocorecc-shikra",
.of_match_table = audio_core_cc_shikra_match_table,
},
};
module_platform_driver(audio_core_cc_shikra_driver);
MODULE_DESCRIPTION("QTI AUDIOCORECC Shikra Driver");
MODULE_LICENSE("GPL");

2279
drivers/clk/qcom/camcc-glymur.c Normal file
View File

File diff suppressed because it is too large Load Diff

19
drivers/clk/qcom/camcc-sc8280xp.c
View File

@ -1753,24 +1753,6 @@ static struct clk_branch camcc_csiphy3_clk = {
},
};
static struct clk_branch camcc_gdsc_clk = {
.halt_reg = 0xc1e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc1e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_gdsc_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_icp_ahb_clk = {
.halt_reg = 0xc0d8,
.halt_check = BRANCH_HALT,
@ -2839,7 +2821,6 @@ static struct clk_regmap *camcc_sc8280xp_clocks[] = {
[CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
[CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
[CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
[CAMCC_GDSC_CLK] = &camcc_gdsc_clk.clkr,
[CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr,
[CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
[CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,

6
drivers/clk/qcom/camcc-x1p42100.c
View File

@ -2165,7 +2165,7 @@ static struct clk_alpha_pll *cam_cc_x1p42100_plls[] = {
&cam_cc_pll6,
};
static u32 cam_cc_x1p42100_critical_cbcrs[] = {
static const u32 cam_cc_x1p42100_critical_cbcrs[] = {
0x13a9c, /* CAM_CC_GDSC_CLK */
0x13ab8, /* CAM_CC_SLEEP_CLK */
};
@ -2178,14 +2178,14 @@ static const struct regmap_config cam_cc_x1p42100_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data cam_cc_x1p42100_driver_data = {
static const struct qcom_cc_driver_data cam_cc_x1p42100_driver_data = {
.alpha_plls = cam_cc_x1p42100_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_x1p42100_plls),
.clk_cbcrs = cam_cc_x1p42100_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1p42100_critical_cbcrs),
};
static struct qcom_cc_desc cam_cc_x1p42100_desc = {
static const struct qcom_cc_desc cam_cc_x1p42100_desc = {
.config = &cam_cc_x1p42100_regmap_config,
.clks = cam_cc_x1p42100_clocks,
.num_clks = ARRAY_SIZE(cam_cc_x1p42100_clocks),

4
drivers/clk/qcom/clk-hfpll.c
View File

@ -166,7 +166,7 @@ static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(&h->lock, flags);
enabled = __clk_is_enabled(hw->clk);
enabled = clk_hw_is_enabled(hw);
if (enabled)
__clk_hfpll_disable(h);
@ -220,7 +220,7 @@ static int clk_hfpll_init(struct clk_hw *hw)
regmap_read(regmap, hd->status_reg, &status);
if (!(status & BIT(hd->lock_bit))) {
WARN(1, "HFPLL %s is ON, but not locked!\n",
__clk_get_name(hw->clk));
clk_hw_get_name(hw));
clk_hfpll_disable(hw);
__clk_hfpll_init_once(hw);
}

2
drivers/clk/qcom/clk-krait.c
View File

@ -68,7 +68,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
if (clk_hw_is_enabled(hw))
__krait_mux_set_sel(mux, sel);
mux->reparent = true;

4
drivers/clk/qcom/clk-rcg.c
View File

@ -208,7 +208,7 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
bool banked_p = !!rcg->p[1].pre_div_width;
struct clk_hw *hw = &rcg->clkr.hw;
enabled = __clk_is_enabled(hw->clk);
enabled = clk_hw_is_enabled(hw);
ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
if (ret)
@ -771,7 +771,7 @@ static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
ret = __clk_rcg_set_rate(rcg, f);
/* Switch back to M/N if it's clocking */
if (__clk_is_enabled(hw->clk))
if (clk_hw_is_enabled(hw))
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
return ret;

2
drivers/clk/qcom/clk-rcg2.c
View File

@ -489,7 +489,7 @@ static int clk_rcg2_determine_gp_rate(struct clk_hw *hw,
u64 parent_rate;
parent = clk_hw_get_parent(hw);
parent_rate = clk_get_rate(parent->clk);
parent_rate = clk_hw_get_rate(parent);
if (!parent_rate)
return -EINVAL;

205
drivers/clk/qcom/clk-ref.c Normal file
View File

@ -0,0 +1,205 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/clk/qcom.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#define QCOM_CLK_REF_EN_MASK BIT(0)
struct qcom_clk_ref_provider {
size_t num_refs;
struct qcom_clk_ref refs[] __counted_by(num_refs);
};
static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw)
{
return container_of(hw, struct qcom_clk_ref, hw);
}
static const struct clk_parent_data qcom_clk_ref_parent_data = {
.index = 0,
};
static int qcom_clk_ref_prepare(struct clk_hw *hw)
{
struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
int ret;
if (!rclk->desc.num_regulators)
return 0;
ret = regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators);
if (ret)
pr_err("Failed to enable regulators for %s: %d\n",
clk_hw_get_name(hw), ret);
return ret;
}
static void qcom_clk_ref_unprepare(struct clk_hw *hw)
{
struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
if (rclk->desc.num_regulators)
regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators);
}
static int qcom_clk_ref_enable(struct clk_hw *hw)
{
struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
int ret;
ret = regmap_set_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK);
if (ret)
return ret;
udelay(10);
return 0;
}
static void qcom_clk_ref_disable(struct clk_hw *hw)
{
struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
regmap_clear_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK);
udelay(10);
}
static int qcom_clk_ref_is_enabled(struct clk_hw *hw)
{
struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
u32 val;
int ret;
ret = regmap_read(rclk->regmap, rclk->desc.offset, &val);
if (ret)
return 0;
return !!(val & QCOM_CLK_REF_EN_MASK);
}
static const struct clk_ops qcom_clk_ref_ops = {
.prepare = qcom_clk_ref_prepare,
.unprepare = qcom_clk_ref_unprepare,
.enable = qcom_clk_ref_enable,
.disable = qcom_clk_ref_disable,
.is_enabled = qcom_clk_ref_is_enabled,
};
static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap,
struct qcom_clk_ref *clk_refs,
const struct qcom_clk_ref_desc * const *descs,
size_t num_clk_refs)
{
const struct qcom_clk_ref_desc *desc;
struct clk_init_data init_data = {};
struct qcom_clk_ref *clk_ref;
size_t clk_idx;
unsigned int i;
int ret;
for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) {
clk_ref = &clk_refs[clk_idx];
desc = descs[clk_idx];
/* Skip unpopulated indices; the array is indexed by clock ID. */
if (!desc)
continue;
if (WARN_ON(!desc->name))
continue;
clk_ref->regmap = regmap;
clk_ref->desc = *desc;
if (clk_ref->desc.num_regulators) {
clk_ref->regulators = devm_kcalloc(dev, clk_ref->desc.num_regulators,
sizeof(*clk_ref->regulators),
GFP_KERNEL);
if (!clk_ref->regulators)
return -ENOMEM;
for (i = 0; i < clk_ref->desc.num_regulators; i++)
clk_ref->regulators[i].supply =
clk_ref->desc.regulator_names[i];
ret = devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators,
clk_ref->regulators);
if (ret)
return dev_err_probe(dev, ret,
"Failed to get regulators for %s\n",
clk_ref->desc.name);
}
init_data.name = clk_ref->desc.name;
init_data.parent_data = &qcom_clk_ref_parent_data;
init_data.num_parents = 1;
init_data.ops = &qcom_clk_ref_ops;
clk_ref->hw.init = &init_data;
ret = devm_clk_hw_register(dev, &clk_ref->hw);
if (ret)
return ret;
}
return 0;
}
static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *clkspec, void *data)
{
struct qcom_clk_ref_provider *provider = data;
unsigned int idx = clkspec->args[0];
if (idx >= provider->num_refs)
return ERR_PTR(-EINVAL);
if (!provider->refs[idx].regmap)
return ERR_PTR(-ENOENT);
return &provider->refs[idx].hw;
}
int qcom_clk_ref_probe(struct platform_device *pdev,
const struct regmap_config *config,
const struct qcom_clk_ref_desc * const *descs,
size_t num_clk_refs)
{
struct qcom_clk_ref_provider *provider;
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
provider = devm_kzalloc(dev, struct_size(provider, refs, num_clk_refs),
GFP_KERNEL);
if (!provider)
return -ENOMEM;
provider->num_refs = num_clk_refs;
ret = qcom_clk_ref_register(dev, regmap, provider->refs, descs,
provider->num_refs);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provider);
}
EXPORT_SYMBOL_GPL(qcom_clk_ref_probe);

5
drivers/clk/qcom/clk-smd-rpm.c
View File

@ -495,6 +495,7 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk2, 5, 38400000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000);
@ -1262,6 +1263,10 @@ static struct clk_smd_rpm *qcm2290_clks[] = {
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_38m4_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_38m4_rf_clk2_a,
[RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,

6
drivers/clk/qcom/common.c
View File

@ -169,7 +169,7 @@ static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
if (!node) {
fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
if (!fixed)
return -EINVAL;
return -ENOMEM;
fixed->fixed_rate = rate;
fixed->hw.init = &init_data;
@ -186,7 +186,7 @@ static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
if (add_factor) {
factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
if (!factor)
return -EINVAL;
return -ENOMEM;
factor->mult = factor->div = 1;
factor->hw.init = &init_data;
@ -428,7 +428,7 @@ int qcom_cc_really_probe(struct device *dev,
put_rpm:
if (desc->use_rpm)
pm_runtime_put(dev);
pm_runtime_put_sync(dev);
return ret;
}

44
drivers/clk/qcom/dispcc-qcm2290.c
View File

@ -2,6 +2,7 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
@ -48,6 +49,7 @@ static const struct alpha_pll_config disp_cc_pll0_config = {
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.config = &disp_cc_pll0_config,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@ -449,11 +451,14 @@ static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
.flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc *disp_cc_qcm2290_gdscs[] = {
@ -482,6 +487,14 @@ static struct clk_regmap *disp_cc_qcm2290_clocks[] = {
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
};
static struct clk_alpha_pll *disp_cc_qcm2290_plls[] = {
&disp_cc_pll0,
};
static const u32 disp_cc_qcm2290_critical_cbcrs[] = {
0x604c, /* DISP_CC_XO_CLK */
};
static const struct regmap_config disp_cc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -490,6 +503,13 @@ static const struct regmap_config disp_cc_qcm2290_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_driver_data disp_cc_qcm2290_driver_data = {
.alpha_plls = disp_cc_qcm2290_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_qcm2290_plls),
.clk_cbcrs = disp_cc_qcm2290_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_qcm2290_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.config = &disp_cc_qcm2290_regmap_config,
.clks = disp_cc_qcm2290_clocks,
@ -498,6 +518,8 @@ static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
.resets = disp_cc_qcm2290_resets,
.num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets),
.use_rpm = true,
.driver_data = &disp_cc_qcm2290_driver_data,
};
static const struct of_device_id disp_cc_qcm2290_match_table[] = {
@ -508,25 +530,7 @@ MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table);
static int disp_cc_qcm2290_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
}
return ret;
return qcom_cc_probe(pdev, &disp_cc_qcm2290_desc);
}
static struct platform_driver disp_cc_qcm2290_driver = {

2004
drivers/clk/qcom/dispcc0-nord.c Normal file
View File

File diff suppressed because it is too large Load Diff

2004
drivers/clk/qcom/dispcc1-nord.c Normal file
View File

File diff suppressed because it is too large Load Diff

454
drivers/clk/qcom/evacc-glymur.c Normal file
View File

@ -0,0 +1,454 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,glymur-evacc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_AHB_CLK,
DT_BI_TCXO,
DT_SLEEP_CLK,
};
enum {
P_BI_TCXO,
P_EVA_CC_PLL0_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct pll_vco taycan_eko_t_vco[] = {
{ 249600000, 2500000000, 0 },
};
/* 840.0 MHz Configuration */
static const struct alpha_pll_config eva_cc_pll0_config = {
.l = 0x2b,
.alpha = 0xc000,
.config_ctl_val = 0x25c400e7,
.config_ctl_hi_val = 0x0a8060e0,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000008,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll eva_cc_pll0 = {
.offset = 0x0,
.config = &eva_cc_pll0_config,
.vco_table = taycan_eko_t_vco,
.num_vco = ARRAY_SIZE(taycan_eko_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eko_t_ops,
},
},
};
static const struct parent_map eva_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data eva_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map eva_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_EVA_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data eva_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &eva_cc_pll0.clkr.hw },
};
static const struct parent_map eva_cc_parent_map_2[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data eva_cc_parent_data_2[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_eva_cc_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 eva_cc_ahb_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = eva_cc_parent_map_0,
.freq_tbl = ftbl_eva_cc_ahb_clk_src,
.hw_clk_ctrl = true,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_ahb_clk_src",
.parent_data = eva_cc_parent_data_0,
.num_parents = ARRAY_SIZE(eva_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
},
};
static const struct freq_tbl ftbl_eva_cc_mvs0_clk_src[] = {
F(840000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1050000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1350000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1500000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1650000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 eva_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = eva_cc_parent_map_1,
.freq_tbl = ftbl_eva_cc_mvs0_clk_src,
.hw_clk_ctrl = true,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0_clk_src",
.parent_data = eva_cc_parent_data_1,
.num_parents = ARRAY_SIZE(eva_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
},
};
static const struct freq_tbl ftbl_eva_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 eva_cc_sleep_clk_src = {
.cmd_rcgr = 0x80e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = eva_cc_parent_map_2,
.freq_tbl = ftbl_eva_cc_sleep_clk_src,
.hw_clk_ctrl = true,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_sleep_clk_src",
.parent_data = eva_cc_parent_data_2,
.num_parents = ARRAY_SIZE(eva_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
},
};
static struct clk_rcg2 eva_cc_xo_clk_src = {
.cmd_rcgr = 0x80bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = eva_cc_parent_map_0,
.freq_tbl = ftbl_eva_cc_ahb_clk_src,
.hw_clk_ctrl = true,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_xo_clk_src",
.parent_data = eva_cc_parent_data_0,
.num_parents = ARRAY_SIZE(eva_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
},
};
static struct clk_regmap_div eva_cc_mvs0_div_clk_src = {
.reg = 0x809c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div eva_cc_mvs0c_div2_div_clk_src = {
.reg = 0x8060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch eva_cc_mvs0_clk = {
.halt_reg = 0x807c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x807c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x807c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch eva_cc_mvs0_freerun_clk = {
.halt_reg = 0x808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x808c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch eva_cc_mvs0_shift_clk = {
.halt_reg = 0x80d8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80d8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch eva_cc_mvs0c_clk = {
.halt_reg = 0x804c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x804c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_mvs0c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch eva_cc_mvs0c_freerun_clk = {
.halt_reg = 0x805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x805c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0c_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_mvs0c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch eva_cc_mvs0c_shift_clk = {
.halt_reg = 0x80dc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80dc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "eva_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&eva_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc eva_cc_mvs0c_gdsc = {
.gdscr = 0x8034,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "eva_cc_mvs0c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc eva_cc_mvs0_gdsc = {
.gdscr = 0x8068,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "eva_cc_mvs0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
.parent = &eva_cc_mvs0c_gdsc.pd,
};
static struct clk_regmap *eva_cc_glymur_clocks[] = {
[EVA_CC_AHB_CLK_SRC] = &eva_cc_ahb_clk_src.clkr,
[EVA_CC_MVS0_CLK] = &eva_cc_mvs0_clk.clkr,
[EVA_CC_MVS0_CLK_SRC] = &eva_cc_mvs0_clk_src.clkr,
[EVA_CC_MVS0_DIV_CLK_SRC] = &eva_cc_mvs0_div_clk_src.clkr,
[EVA_CC_MVS0_FREERUN_CLK] = &eva_cc_mvs0_freerun_clk.clkr,
[EVA_CC_MVS0_SHIFT_CLK] = &eva_cc_mvs0_shift_clk.clkr,
[EVA_CC_MVS0C_CLK] = &eva_cc_mvs0c_clk.clkr,
[EVA_CC_MVS0C_DIV2_DIV_CLK_SRC] = &eva_cc_mvs0c_div2_div_clk_src.clkr,
[EVA_CC_MVS0C_FREERUN_CLK] = &eva_cc_mvs0c_freerun_clk.clkr,
[EVA_CC_MVS0C_SHIFT_CLK] = &eva_cc_mvs0c_shift_clk.clkr,
[EVA_CC_PLL0] = &eva_cc_pll0.clkr,
[EVA_CC_SLEEP_CLK_SRC] = &eva_cc_sleep_clk_src.clkr,
[EVA_CC_XO_CLK_SRC] = &eva_cc_xo_clk_src.clkr,
};
static struct gdsc *eva_cc_glymur_gdscs[] = {
[EVA_CC_MVS0_GDSC] = &eva_cc_mvs0_gdsc,
[EVA_CC_MVS0C_GDSC] = &eva_cc_mvs0c_gdsc,
};
static const struct qcom_reset_map eva_cc_glymur_resets[] = {
[EVA_CC_INTERFACE_BCR] = { 0x80a0 },
[EVA_CC_MVS0_BCR] = { 0x8064 },
[EVA_CC_MVS0C_CLK_ARES] = { 0x804c, 2 },
[EVA_CC_MVS0C_BCR] = { 0x8030 },
[EVA_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 },
};
static struct clk_alpha_pll *eva_cc_glymur_plls[] = {
&eva_cc_pll0,
};
static const u32 eva_cc_glymur_critical_cbcrs[] = {
0x80a4, /* EVA_CC_AHB_CLK */
0x80f8, /* EVA_CC_SLEEP_CLK */
0x80d4, /* EVA_CC_XO_CLK */
};
static const struct regmap_config eva_cc_glymur_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9f50,
.fast_io = true,
};
static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
{
/*
* Update CTRL_IN register as per HW recommendation to ensure clocks
* stay cycle‑aligned when the EVA core is ON.
*/
regmap_set_bits(regmap, 0x9f24, BIT(0));
}
static const struct qcom_cc_driver_data eva_cc_glymur_driver_data = {
.alpha_plls = eva_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(eva_cc_glymur_plls),
.clk_cbcrs = eva_cc_glymur_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(eva_cc_glymur_critical_cbcrs),
.clk_regs_configure = clk_glymur_regs_configure,
};
static const struct qcom_cc_desc eva_cc_glymur_desc = {
.config = &eva_cc_glymur_regmap_config,
.clks = eva_cc_glymur_clocks,
.num_clks = ARRAY_SIZE(eva_cc_glymur_clocks),
.resets = eva_cc_glymur_resets,
.num_resets = ARRAY_SIZE(eva_cc_glymur_resets),
.gdscs = eva_cc_glymur_gdscs,
.num_gdscs = ARRAY_SIZE(eva_cc_glymur_gdscs),
.use_rpm = true,
.driver_data = &eva_cc_glymur_driver_data,
};
static const struct of_device_id eva_cc_glymur_match_table[] = {
{ .compatible = "qcom,glymur-evacc" },
{ }
};
MODULE_DEVICE_TABLE(of, eva_cc_glymur_match_table);
static int eva_cc_glymur_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &eva_cc_glymur_desc);
}
static struct platform_driver eva_cc_glymur_driver = {
.probe = eva_cc_glymur_probe,
.driver = {
.name = "evacc-glymur",
.of_match_table = eva_cc_glymur_match_table,
},
};
module_platform_driver(eva_cc_glymur_driver);
MODULE_DESCRIPTION("QTI EVACC Glymur Driver");
MODULE_LICENSE("GPL");

33
drivers/clk/qcom/gcc-glymur.c
View File

@ -3668,21 +3668,6 @@ static struct clk_branch gcc_disp_hf_axi_clk = {
},
};
static struct clk_branch gcc_eva_ahb_clk = {
.halt_reg = 0x9b004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9b004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9b004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eva_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eva_axi0_clk = {
.halt_reg = 0x9b008,
.halt_check = BRANCH_HALT_SKIP,
@ -3713,19 +3698,6 @@ static struct clk_branch gcc_eva_axi0c_clk = {
},
};
static struct clk_branch gcc_eva_xo_clk = {
.halt_reg = 0x9b024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9b024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eva_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
@ -7992,10 +7964,8 @@ static struct clk_regmap *gcc_glymur_clocks[] = {
[GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
[GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_EVA_AHB_CLK] = &gcc_eva_ahb_clk.clkr,
[GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr,
[GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr,
[GCC_EVA_XO_CLK] = &gcc_eva_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
@ -8544,6 +8514,8 @@ static const u32 gcc_glymur_critical_cbcrs[] = {
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x32004, /* GCC_VIDEO_AHB_CLK */
0x32058, /* GCC_VIDEO_XO_CLK */
0x9b004, /* GCC_EVA_AHB_CLK */
0x9b024, /* GCC_EVA_XO_CLK */
};
static const struct regmap_config gcc_glymur_regmap_config = {
@ -8576,6 +8548,7 @@ static const struct qcom_cc_desc gcc_glymur_desc = {
.num_resets = ARRAY_SIZE(gcc_glymur_resets),
.gdscs = gcc_glymur_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_glymur_gdscs),
.use_rpm = true,
.driver_data = &gcc_glymur_driver_data,
};

201
drivers/clk/qcom/gcc-hawi.c
View File

@ -10,6 +10,7 @@
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,hawi-gcc.h>
#include <dt-bindings/clock/qcom,maili-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@ -1114,6 +1115,31 @@ static struct clk_rcg2 gcc_qupv3_wrap4_s4_clk_src = {
.clkr.hw.init = &gcc_qupv3_wrap4_s4_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap5_qspi_ref_clk_src[] = {
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(196078431, P_GCC_GPLL0_OUT_EVEN, 1, 100, 153),
F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap5_qspi_ref_clk_src_init = {
.name = "gcc_qupv3_wrap5_qspi_ref_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap5_qspi_ref_clk_src = {
.cmd_rcgr = 0xad024,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap5_qspi_ref_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap5_qspi_ref_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
@ -1281,6 +1307,21 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
},
};
static struct clk_regmap_div gcc_qupv3_wrap5_s0_clk_src = {
.reg = 0xad018,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap5_s0_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap5_qspi_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x3904c,
.mnd_width = 0,
@ -2739,6 +2780,68 @@ static struct clk_branch gcc_qupv3_wrap4_s4_clk = {
},
};
static struct clk_branch gcc_qupv3_wrap5_core_2x_clk = {
.halt_reg = 0x236bc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap5_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap5_core_clk = {
.halt_reg = 0x236a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap5_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap5_qspi_ref_clk = {
.halt_reg = 0xad01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap5_qspi_ref_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap5_qspi_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap5_s0_clk = {
.halt_reg = 0xad004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap5_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap5_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_axi_clk = {
.halt_reg = 0x23140,
.halt_check = BRANCH_HALT_VOTED,
@ -2859,6 +2962,36 @@ static struct clk_branch gcc_qupv3_wrap_4_s_ahb_clk = {
},
};
static struct clk_branch gcc_qupv3_wrap_5_m_ahb_clk = {
.halt_reg = 0x236a0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x236a0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_5_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_5_s_ahb_clk = {
.halt_reg = 0x236a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x236a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_5_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14014,
.halt_check = BRANCH_HALT,
@ -3484,6 +3617,11 @@ static struct clk_regmap *gcc_hawi_clocks[] = {
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr,
/*
* Maili has more clocks than Hawi. Ensure the array is appropriately
* sized and assign the additional clocks in .probe()
*/
[GCC_QUPV3_WRAP_5_S_AHB_CLK] = NULL,
};
static struct gdsc *gcc_hawi_gdscs[] = {
@ -3587,6 +3725,34 @@ static const struct clk_rcg_dfs_data gcc_hawi_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src),
};
static const struct clk_rcg_dfs_data gcc_maili_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap4_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap4_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap4_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap4_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap5_qspi_ref_clk_src),
};
static const struct regmap_config gcc_hawi_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -3621,14 +3787,49 @@ static const struct qcom_cc_desc gcc_hawi_desc = {
.driver_data = &gcc_hawi_driver_data,
};
static const struct qcom_cc_driver_data gcc_maili_driver_data = {
.clk_cbcrs = gcc_hawi_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_hawi_critical_cbcrs),
.dfs_rcgs = gcc_maili_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_maili_dfs_clocks),
.clk_regs_configure = clk_hawi_regs_configure,
};
static const struct qcom_cc_desc gcc_maili_desc = {
.config = &gcc_hawi_regmap_config,
.clks = gcc_hawi_clocks,
.num_clks = ARRAY_SIZE(gcc_hawi_clocks),
.resets = gcc_hawi_resets,
.num_resets = ARRAY_SIZE(gcc_hawi_resets),
.gdscs = gcc_hawi_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_hawi_gdscs),
.use_rpm = true,
.driver_data = &gcc_maili_driver_data,
};
static const struct of_device_id gcc_hawi_match_table[] = {
{ .compatible = "qcom,hawi-gcc" },
{ .compatible = "qcom,maili-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_hawi_match_table);
static int gcc_hawi_probe(struct platform_device *pdev)
{
if (of_device_is_compatible(pdev->dev.of_node, "qcom,maili-gcc")) {
gcc_hawi_clocks[GCC_QUPV3_WRAP5_CORE_2X_CLK] = &gcc_qupv3_wrap5_core_2x_clk.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP5_CORE_CLK] = &gcc_qupv3_wrap5_core_clk.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP5_QSPI_REF_CLK] = &gcc_qupv3_wrap5_qspi_ref_clk.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP5_QSPI_REF_CLK_SRC] =
&gcc_qupv3_wrap5_qspi_ref_clk_src.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP5_S0_CLK] = &gcc_qupv3_wrap5_s0_clk.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP5_S0_CLK_SRC] = &gcc_qupv3_wrap5_s0_clk_src.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP_5_M_AHB_CLK] = &gcc_qupv3_wrap_5_m_ahb_clk.clkr;
gcc_hawi_clocks[GCC_QUPV3_WRAP_5_S_AHB_CLK] = &gcc_qupv3_wrap_5_s_ahb_clk.clkr;
return qcom_cc_probe(pdev, &gcc_maili_desc);
}
return qcom_cc_probe(pdev, &gcc_hawi_desc);
}

11
drivers/clk/qcom/gcc-ipq5424.c
View File

@ -139,17 +139,6 @@ static struct clk_alpha_pll gpll4 = {
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
/*
* There are no consumers for this GPLL in kernel yet,
* (will be added soon), so the clock framework
* disables this source. But some of the clocks
* initialized by boot loaders uses this source. So we
* need to keep this clock ON. Add the
* CLK_IGNORE_UNUSED flag so the clock will not be
* disabled. Once the consumer in kernel is added, we
* can get rid of this flag.
*/
.flags = CLK_IGNORE_UNUSED,
},
},
};

89
drivers/clk/qcom/gcc-ipq9650.c
View File

@ -3022,6 +3022,90 @@ static struct clk_branch gcc_usb1_sleep_clk = {
},
};
static struct clk_rcg2 gcc_refgen_core_clk_src = {
.cmd_rcgr = 0x23004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_nss_ts_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_core_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_refgen_cmn_uphy_core_clk = {
.halt_reg = 0x2300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_cmn_uphy_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_refgen_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_refgen_pcie_core_clk = {
.halt_reg = 0x23020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x23020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_pcie_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_refgen_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_refgen_pcie_hclk = {
.halt_reg = 0x23024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x23024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_pcie_hclk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_refgen_cmn_uphy_hclk = {
.halt_reg = 0x23010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x23010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_cmn_uphy_hclk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gcc_ipq9650_clocks[] = {
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
@ -3179,6 +3263,11 @@ static struct clk_regmap *gcc_ipq9650_clocks[] = {
[GPLL2] = &gpll2.clkr,
[GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
[GPLL4] = &gpll4.clkr,
[GCC_REFGEN_CORE_CLK_SRC] = &gcc_refgen_core_clk_src.clkr,
[GCC_REFGEN_PCIE_CORE_CLK] = &gcc_refgen_pcie_core_clk.clkr,
[GCC_REFGEN_PCIE_HCLK] = &gcc_refgen_pcie_hclk.clkr,
[GCC_REFGEN_CMN_UPHY_HCLK] = &gcc_refgen_cmn_uphy_hclk.clkr,
[GCC_REFGEN_CMN_UPHY_CORE_CLK] = &gcc_refgen_cmn_uphy_core_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq9650_resets[] = {

193
drivers/clk/qcom/gcc-mdm9607.c
View File

@ -26,7 +26,6 @@
enum {
P_XO,
P_BIMC,
P_GPLL0,
P_GPLL1,
P_GPLL2,
@ -121,7 +120,7 @@ static struct clk_alpha_pll gpll2_early = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(3), /* Yeah, apparently it's not 2 */
.enable_mask = BIT(3), /* BIT(2) is used for BIMC PLL */
.hw.init = &(struct clk_init_data)
{
.name = "gpll2_early",
@ -158,20 +157,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
{ P_GPLL2, 3 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
@ -192,80 +177,6 @@ static struct clk_rcg2 apss_ahb_clk_src = {
},
};
static struct clk_pll bimc_pll = {
.l_reg = 0x23004,
.m_reg = 0x23008,
.n_reg = 0x2300c,
.config_reg = 0x23010,
.mode_reg = 0x23000,
.status_reg = 0x2301c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap bimc_pll_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
.parent_hws = (const struct clk_hw *[]){ &bimc_pll.clkr.hw },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_BIMC, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &bimc_pll_vote.hw },
};
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
@ -674,26 +585,6 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
F(155000000, P_GPLL2, 6, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 apss_tcu_clk_src = {
.cmd_rcgr = 0x1207c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_gpll2_map,
.freq_tbl = ftbl_gcc_apss_tcu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_gpll2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(57140000, P_GPLL0, 14, 0, 0),
@ -781,8 +672,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -790,9 +679,10 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.enable_reg = 0x45004,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.parent_data = &(const struct clk_parent_data){
@ -1083,8 +973,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -1098,9 +986,6 @@ static struct clk_branch gcc_crypto_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1114,9 +999,6 @@ static struct clk_branch gcc_crypto_axi_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1190,9 +1072,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1220,9 +1099,6 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1236,9 +1112,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1251,9 +1124,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1281,9 +1151,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1304,19 +1171,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
},
};
static struct clk_rcg2 bimc_ddr_clk_src = {
.cmd_rcgr = 0x32004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = 3,
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.clkr = {
@ -1324,9 +1178,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1340,8 +1191,6 @@ static struct clk_branch gcc_apss_tcu_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
.parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -1355,9 +1204,6 @@ static struct clk_branch gcc_smmu_cfg_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1405,9 +1251,6 @@ static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1420,9 +1263,6 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1451,23 +1291,19 @@ static struct clk_branch gcc_apss_ahb_clk = {
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x4601c,
.halt_reg = 0x46020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -1480,11 +1316,6 @@ static struct clk_regmap *gcc_mdm9607_clocks[] = {
[GPLL1_VOTE] = &gpll1_vote,
[GPLL2] = &gpll2.clkr,
[GPLL2_EARLY] = &gpll2_early.clkr,
[BIMC_PLL] = &bimc_pll.clkr,
[BIMC_PLL_VOTE] = &bimc_pll_vote,
[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
@ -1511,7 +1342,6 @@ static struct clk_regmap *gcc_mdm9607_clocks[] = {
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
@ -1567,7 +1397,7 @@ static const struct qcom_reset_map gcc_mdm9607_resets[] = {
[USB_HS_HSIC_BCR] = { 0x3d05c },
[GCC_MSS_RESTART] = { 0x3e000 },
[USB_HS_BCR] = { 0x41000 },
[USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
[USB2_HS_PHY_ONLY_BCR] = { .reg = 0x41034, .udelay = 15 },
[QUSB2_PHY_BCR] = { 0x4103c },
};
@ -1595,16 +1425,7 @@ MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table);
static int gcc_mdm9607_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_mdm9607_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Vote for GPLL0 to turn on. Needed by acpuclock. */
regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9607_desc, regmap);
return qcom_cc_probe(pdev, &gcc_mdm9607_desc);
}
static struct platform_driver gcc_mdm9607_driver = {

5
drivers/clk/qcom/gcc-msm8916.c
View File

@ -1589,9 +1589,10 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x01004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x01004,
.enable_mask = BIT(0),
.enable_reg = 0x45004,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.parent_data = &(const struct clk_parent_data){

5
drivers/clk/qcom/gcc-msm8939.c
View File

@ -1929,9 +1929,10 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x01004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x01004,
.enable_mask = BIT(0),
.enable_reg = 0x45004,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.ops = &clk_branch2_ops,

45
drivers/clk/qcom/gcc-nord.c
View File

@ -701,7 +701,7 @@ static struct clk_branch gcc_pcie_a_phy_rchng_clk = {
static struct clk_branch gcc_pcie_a_pipe_clk = {
.halt_reg = 0x49068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x49068,
.hwcg_bit = 1,
.clkr = {
@ -850,7 +850,7 @@ static struct clk_branch gcc_pcie_b_phy_rchng_clk = {
static struct clk_branch gcc_pcie_b_pipe_clk = {
.halt_reg = 0x4a068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9d008,
.enable_mask = BIT(24),
@ -995,7 +995,7 @@ static struct clk_branch gcc_pcie_c_phy_rchng_clk = {
static struct clk_branch gcc_pcie_c_pipe_clk = {
.halt_reg = 0x4b068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9d010,
.enable_mask = BIT(1),
@ -1140,7 +1140,7 @@ static struct clk_branch gcc_pcie_d_phy_rchng_clk = {
static struct clk_branch gcc_pcie_d_pipe_clk = {
.halt_reg = 0x4c068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9d010,
.enable_mask = BIT(10),
@ -1184,34 +1184,6 @@ static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = {
},
};
static struct clk_branch gcc_pcie_link_ahb_clk = {
.halt_reg = 0x52464,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52464,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_link_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_link_xo_clk = {
.halt_reg = 0x52468,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x52468,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52468,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_link_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_noc_async_bridge_clk = {
.halt_reg = 0x52048,
.halt_check = BRANCH_HALT_SKIP,
@ -1757,8 +1729,6 @@ static struct clk_regmap *gcc_nord_clocks[] = {
[GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr,
[GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr,
[GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr,
[GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr,
[GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr,
[GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr,
[GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr,
[GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr,
@ -1849,9 +1819,16 @@ static const struct regmap_config gcc_nord_regmap_config = {
.fast_io = true,
};
static const u32 gcc_nord_critical_cbcrs[] = {
0x52464, /* GCC_PCIE_LINK_AHB_CLK */
0x52468, /* GCC_PCIE_LINK_XO_CLK */
};
static const struct qcom_cc_driver_data gcc_nord_driver_data = {
.dfs_rcgs = gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
.clk_cbcrs = gcc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_nord_critical_cbcrs),
};
static const struct qcom_cc_desc gcc_nord_desc = {

131
drivers/clk/qcom/gcc-qcm2290.c
View File

@ -116,7 +116,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll10 = {
@ -148,7 +148,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll11 = {
@ -309,7 +309,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll8 = {
@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = {
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_axi_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
.reg = 0x17058,
.shift = 0,
@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = {
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x4d000,
.halt_check = BRANCH_HALT,
@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk = {
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x36004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@ -2439,22 +2363,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x2b06c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b06c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a080,
.halt_check = BRANCH_HALT,
@ -2775,8 +2683,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = {
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
@ -2817,19 +2723,16 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = {
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
@ -2870,7 +2773,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = {
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
@ -2943,6 +2845,15 @@ static struct gdsc *gcc_qcm2290_gdscs[] = {
[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
};
static const u32 gcc_qcm2290_critical_cbcrs[] = {
0x17008, /* GCC_CAMERA_AHB_CLK */
0x17028, /* GCC_CAMERA_XO_CLK */
0x1700c, /* GCC_DISP_AHB_CLK */
0x1702c, /* GCC_DISP_XO_CLK */
0x36004, /* GCC_GPU_CFG_AHB_CLK */
0x79004, /* GCC_SYS_NOC_CPUSS_AHB_CLK */
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
@ -2960,6 +2871,11 @@ static const struct regmap_config gcc_qcm2290_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_driver_data gcc_qcm2290_driver_data = {
.clk_cbcrs = gcc_qcm2290_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_qcm2290_critical_cbcrs),
};
static const struct qcom_cc_desc gcc_qcm2290_desc = {
.config = &gcc_qcm2290_regmap_config,
.clks = gcc_qcm2290_clocks,
@ -2968,6 +2884,7 @@ static const struct qcom_cc_desc gcc_qcm2290_desc = {
.num_resets = ARRAY_SIZE(gcc_qcm2290_resets),
.gdscs = gcc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs),
.driver_data = &gcc_qcm2290_driver_data,
};
static const struct of_device_id gcc_qcm2290_match_table[] = {

8
drivers/clk/qcom/gcc-qcs8300.c
View File

@ -3267,7 +3267,7 @@ static struct gdsc gcc_pcie_0_gdsc = {
.pd = {
.name = "gcc_pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
@ -3281,7 +3281,7 @@ static struct gdsc gcc_pcie_1_gdsc = {
.pd = {
.name = "gcc_pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
@ -3305,7 +3305,7 @@ static struct gdsc gcc_usb20_prim_gdsc = {
.pd = {
.name = "gcc_usb20_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
@ -3317,7 +3317,7 @@ static struct gdsc gcc_usb30_prim_gdsc = {
.pd = {
.name = "gcc_usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};

4432
drivers/clk/qcom/gcc-shikra.c Normal file
View File

File diff suppressed because it is too large Load Diff

7
drivers/clk/qcom/gcc-sm6115.c
View File

@ -120,7 +120,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
@ -173,7 +173,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
@ -367,7 +367,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
@ -3218,6 +3218,7 @@ static struct gdsc gcc_vcodec0_gdsc = {
.pd = {
.name = "gcc_vcodec0",
},
.flags = HW_CTRL_TRIGGER,
.pwrsts = PWRSTS_OFF_ON,
};

47
drivers/clk/qcom/gdsc.c
View File

@ -104,14 +104,21 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
{
ktime_t start;
int ret;
start = ktime_get();
do {
if (gdsc_check_status(sc, status))
ret = gdsc_check_status(sc, status);
if (ret < 0)
return ret;
if (ret)
return 0;
} while (ktime_us_delta(ktime_get(), start) < STATUS_POLL_TIMEOUT_US);
if (gdsc_check_status(sc, status))
ret = gdsc_check_status(sc, status);
if (ret < 0)
return ret;
if (ret)
return 0;
return -ETIMEDOUT;
@ -493,7 +500,9 @@ static int gdsc_init(struct gdsc *sc)
} else if (sc->flags & ALWAYS_ON) {
/* If ALWAYS_ON GDSCs are not ON, turn them ON */
gdsc_enable(&sc->pd);
ret = gdsc_enable(&sc->pd);
if (ret)
return ret;
on = true;
}
@ -669,10 +678,18 @@ int gdsc_register(struct gdsc_desc *desc,
void gdsc_unregister(struct gdsc_desc *desc)
{
struct device *dev = desc->dev;
struct gdsc **scs = desc->scs;
size_t num = desc->num;
int i;
gdsc_pm_subdomain_remove(desc, num);
of_genpd_del_provider(dev->of_node);
gdsc_pm_subdomain_remove(desc, num);
for (i = 0; i < num; i++) {
if (!scs[i])
continue;
pm_genpd_remove(&scs[i]->pd);
}
}
/*
@ -708,3 +725,25 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
return ret;
}
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
/*
* GX GDSC is a special power domain. Normally, its disable sequence
* is managed by the GMU firmware, and high level OS must not attempt
* to disable it. The only exception is during GMU recovery, where the
* GMU driver can set GenPD’s synced_poweroff flag to allow explicitly
* disable GX GDSC in hardware.
*/
int gdsc_gx_disable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
if (domain->synced_poweroff)
return gdsc_disable(domain);
/* Remove parent-supply placed in enable */
if (sc->rsupply)
return regulator_disable(sc->rsupply);
return 0;
}
EXPORT_SYMBOL_GPL(gdsc_gx_disable);

1
drivers/clk/qcom/gdsc.h
View File

@ -93,6 +93,7 @@ int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
struct regmap *);
void gdsc_unregister(struct gdsc_desc *desc);
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
int gdsc_gx_disable(struct generic_pm_domain *domain);
#else
static inline int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev,

545
drivers/clk/qcom/gpu2cc-nord.c Normal file
View File

@ -0,0 +1,545 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,nord-gpu2cc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_2_CC_PLL0_OUT_MAIN,
P_GPU_2_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
/* 934.0 MHz Configuration */
static const struct alpha_pll_config gpu_2_cc_pll0_config = {
.l = 0x30,
.alpha = 0xa555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00400005,
};
static struct clk_alpha_pll gpu_2_cc_pll0 = {
.offset = 0x0,
.config = &gpu_2_cc_pll0_config,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 1100.0 MHz Configuration */
static const struct alpha_pll_config gpu_2_cc_pll1_config = {
.l = 0x39,
.alpha = 0x4aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00400005,
};
static struct clk_alpha_pll gpu_2_cc_pll1 = {
.offset = 0x1000,
.config = &gpu_2_cc_pll1_config,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_2_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_2_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_2_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_2_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_2_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_2_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_2_cc_pll0.clkr.hw },
{ .hw = &gpu_2_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_2_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_2_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_2_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_2_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct freq_tbl ftbl_gpu_2_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_2_cc_ff_clk_src = {
.cmd_rcgr = 0x91c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_2_cc_parent_map_0,
.freq_tbl = ftbl_gpu_2_cc_ff_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_ff_clk_src",
.parent_data = gpu_2_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_2_cc_gmu_clk_src[] = {
F(550000000, P_GPU_2_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_2_cc_gmu_clk_src = {
.cmd_rcgr = 0x9174,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_2_cc_parent_map_1,
.freq_tbl = ftbl_gpu_2_cc_gmu_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_gmu_clk_src",
.parent_data = gpu_2_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gpu_2_cc_hub_clk_src = {
.cmd_rcgr = 0x91a8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_2_cc_parent_map_2,
.freq_tbl = ftbl_gpu_2_cc_ff_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_hub_clk_src",
.parent_data = gpu_2_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_2_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch gpu_2_cc_ahb_clk = {
.halt_reg = 0x90cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_2_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_crc_ahb_clk = {
.halt_reg = 0x90d0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90d0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_2_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_cx_accu_shift_clk = {
.halt_reg = 0x9114,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9114,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_cx_accu_shift_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_cx_ff_clk = {
.halt_reg = 0x9100,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9100,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_2_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_cx_gmu_clk = {
.halt_reg = 0x90e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_2_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_2_cc_cxo_clk = {
.halt_reg = 0x90f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90f8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_freq_measure_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_gpu_smmu_vote_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_gpu_smmu_vote_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_hub_aon_clk = {
.halt_reg = 0x91a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x91a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_2_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_2_cc_hub_cx_int_clk = {
.halt_reg = 0x90fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90fc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_2_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_2_cc_memnoc_gfx_clk = {
.halt_reg = 0x9104,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9104,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x9168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9168,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_2_cc_sleep_clk = {
.halt_reg = 0x90e0,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x90e0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_2_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_2_cc_cx_gdsc = {
.gdscr = 0x9090,
.gds_hw_ctrl = 0x90a4,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_2_cc_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gpu_2_cc_gx_gdsc = {
.gdscr = 0x9034,
.clamp_io_ctrl = 0x9504,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_2_cc_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gpu_2_cc_nord_clocks[] = {
[GPU_2_CC_AHB_CLK] = &gpu_2_cc_ahb_clk.clkr,
[GPU_2_CC_CRC_AHB_CLK] = &gpu_2_cc_crc_ahb_clk.clkr,
[GPU_2_CC_CX_ACCU_SHIFT_CLK] = &gpu_2_cc_cx_accu_shift_clk.clkr,
[GPU_2_CC_CX_FF_CLK] = &gpu_2_cc_cx_ff_clk.clkr,
[GPU_2_CC_CX_GMU_CLK] = &gpu_2_cc_cx_gmu_clk.clkr,
[GPU_2_CC_CXO_CLK] = &gpu_2_cc_cxo_clk.clkr,
[GPU_2_CC_FF_CLK_SRC] = &gpu_2_cc_ff_clk_src.clkr,
[GPU_2_CC_FREQ_MEASURE_CLK] = &gpu_2_cc_freq_measure_clk.clkr,
[GPU_2_CC_GMU_CLK_SRC] = &gpu_2_cc_gmu_clk_src.clkr,
[GPU_2_CC_GPU_SMMU_VOTE_CLK] = &gpu_2_cc_gpu_smmu_vote_clk.clkr,
[GPU_2_CC_HUB_AON_CLK] = &gpu_2_cc_hub_aon_clk.clkr,
[GPU_2_CC_HUB_CLK_SRC] = &gpu_2_cc_hub_clk_src.clkr,
[GPU_2_CC_HUB_CX_INT_CLK] = &gpu_2_cc_hub_cx_int_clk.clkr,
[GPU_2_CC_MEMNOC_GFX_CLK] = &gpu_2_cc_memnoc_gfx_clk.clkr,
[GPU_2_CC_MND1X_0_GFX3D_CLK] = &gpu_2_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_2_CC_MND1X_1_GFX3D_CLK] = &gpu_2_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_2_CC_PLL0] = &gpu_2_cc_pll0.clkr,
[GPU_2_CC_PLL1] = &gpu_2_cc_pll1.clkr,
[GPU_2_CC_SLEEP_CLK] = &gpu_2_cc_sleep_clk.clkr,
};
static struct gdsc *gpu_2_cc_nord_gdscs[] = {
[GPU_2_CC_CX_GDSC] = &gpu_2_cc_cx_gdsc,
[GPU_2_CC_GX_GDSC] = &gpu_2_cc_gx_gdsc,
};
static const struct qcom_reset_map gpu_2_cc_nord_resets[] = {
[GPU_2_CC_ACD_BCR] = { 0x918c },
[GPU_2_CC_CB_BCR] = { 0x9198 },
[GPU_2_CC_CX_BCR] = { 0x908c },
[GPU_2_CC_FAST_HUB_BCR] = { 0x91a0 },
[GPU_2_CC_FF_BCR] = { 0x91c0 },
[GPU_2_CC_GFX3D_AON_BCR] = { 0x9118 },
[GPU_2_CC_GMU_BCR] = { 0x9170 },
[GPU_2_CC_GX_BCR] = { 0x9030 },
[GPU_2_CC_XO_BCR] = { 0x9000 },
};
static struct clk_alpha_pll *gpu_2_cc_nord_plls[] = {
&gpu_2_cc_pll0,
&gpu_2_cc_pll1,
};
static const u32 gpu_2_cc_nord_critical_cbcrs[] = {
0x9004, /* GPU_2_CC_CXO_AON_CLK */
0x900c, /* GPU_2_CC_DEMET_CLK */
};
static const struct regmap_config gpu_2_cc_nord_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9ff0,
.fast_io = true,
};
static const struct qcom_cc_driver_data gpu_2_cc_nord_driver_data = {
.alpha_plls = gpu_2_cc_nord_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_2_cc_nord_plls),
.clk_cbcrs = gpu_2_cc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gpu_2_cc_nord_critical_cbcrs),
};
static const struct qcom_cc_desc gpu_2_cc_nord_desc = {
.config = &gpu_2_cc_nord_regmap_config,
.clks = gpu_2_cc_nord_clocks,
.num_clks = ARRAY_SIZE(gpu_2_cc_nord_clocks),
.resets = gpu_2_cc_nord_resets,
.num_resets = ARRAY_SIZE(gpu_2_cc_nord_resets),
.gdscs = gpu_2_cc_nord_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_2_cc_nord_gdscs),
.use_rpm = true,
.driver_data = &gpu_2_cc_nord_driver_data,
};
static const struct of_device_id gpu_2_cc_nord_match_table[] = {
{ .compatible = "qcom,nord-gpu2cc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_2_cc_nord_match_table);
static int gpu_2_cc_nord_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gpu_2_cc_nord_desc);
}
static struct platform_driver gpu_2_cc_nord_driver = {
.probe = gpu_2_cc_nord_probe,
.driver = {
.name = "gpu2cc-nord",
.of_match_table = gpu_2_cc_nord_match_table,
},
};
module_platform_driver(gpu_2_cc_nord_driver);
MODULE_DESCRIPTION("QTI GPU2CC Nord Driver");
MODULE_LICENSE("GPL");

593
drivers/clk/qcom/gpucc-nord.c Normal file
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@ -0,0 +1,593 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,nord-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
/* 936.0 MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x30,
.alpha = 0xc000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00400005,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.config = &gpu_cc_pll0_config,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 1250.0 MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x41,
.alpha = 0x1aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00400005,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.config = &gpu_cc_pll1_config,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x93d4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(416666667, P_GPU_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x92b8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x938c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
.reg = 0x93cc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_acd_gfx3d_clk = {
.halt_reg = 0x92a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x92a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_acd_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_acmu_clk = {
.halt_reg = 0x9294,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9294,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_acmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9154,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9154,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_accu_shift_clk = {
.halt_reg = 0x91a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x91a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_accu_shift_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x9184,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9184,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x916c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x916c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x917c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x917c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_dpm_clk = {
.halt_reg = 0x91a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x91a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_dpm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_freq_measure_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gpu_smmu_vote_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gpu_smmu_vote_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x9388,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9388,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9180,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9180,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9188,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9188,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_gfx3d_clk = {
.halt_reg = 0x92ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x92ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9164,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cc_cx_gdsc = {
.gdscr = 0x90e8,
.gds_hw_ctrl = 0x9128,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cc_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gpu_cc_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cc_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gpu_cc_nord_clocks[] = {
[GPU_CC_ACD_GFX3D_CLK] = &gpu_cc_acd_gfx3d_clk.clkr,
[GPU_CC_ACMU_CLK] = &gpu_cc_acmu_clk.clkr,
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_GFX3D_CLK] = &gpu_cc_mnd1x_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
};
static struct gdsc *gpu_cc_nord_gdscs[] = {
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_nord_resets[] = {
[GPU_CC_ACD_BCR] = { 0x92f8 },
[GPU_CC_CB_BCR] = { 0x9340 },
[GPU_CC_CX_BCR] = { 0x90e4 },
[GPU_CC_FAST_HUB_BCR] = { 0x9384 },
[GPU_CC_GFX3D_AON_BCR] = { 0x91ac },
[GPU_CC_GX_BCR] = { 0x9058 },
[GPU_CC_XO_BCR] = { 0x9000 },
};
static struct clk_alpha_pll *gpu_cc_nord_plls[] = {
&gpu_cc_pll0,
&gpu_cc_pll1,
};
static const u32 gpu_cc_nord_critical_cbcrs[] = {
0x9004, /* GPU_CC_CXO_AON_CLK */
0x900c, /* GPU_CC_DEMET_CLK */
};
static const struct regmap_config gpu_cc_nord_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9660,
.fast_io = true,
};
static const struct qcom_cc_driver_data gpu_cc_nord_driver_data = {
.alpha_plls = gpu_cc_nord_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_nord_plls),
.clk_cbcrs = gpu_cc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gpu_cc_nord_critical_cbcrs),
};
static const struct qcom_cc_desc gpu_cc_nord_desc = {
.config = &gpu_cc_nord_regmap_config,
.clks = gpu_cc_nord_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_nord_clocks),
.resets = gpu_cc_nord_resets,
.num_resets = ARRAY_SIZE(gpu_cc_nord_resets),
.gdscs = gpu_cc_nord_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_nord_gdscs),
.use_rpm = true,
.driver_data = &gpu_cc_nord_driver_data,
};
static const struct of_device_id gpu_cc_nord_match_table[] = {
{ .compatible = "qcom,nord-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_nord_match_table);
static int gpu_cc_nord_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gpu_cc_nord_desc);
}
static struct platform_driver gpu_cc_nord_driver = {
.probe = gpu_cc_nord_probe,
.driver = {
.name = "gpucc-nord",
.of_match_table = gpu_cc_nord_match_table,
},
};
module_platform_driver(gpu_cc_nord_driver);
MODULE_DESCRIPTION("QTI GPUCC Nord Driver");
MODULE_LICENSE("GPL");

102
drivers/clk/qcom/gpucc-qcm2290.c
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@ -2,13 +2,12 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2024, Linaro Limited
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
@ -20,6 +19,7 @@
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
@ -56,6 +56,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = {
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.config = &gpu_cc_pll0_config,
.vco_table = huayra_vco,
.num_vco = ARRAY_SIZE(huayra_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
@ -132,6 +133,17 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src_shikra[] = {
F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
F(537600000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(1142400000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
@ -143,21 +155,7 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
.ops = &clk_rcg2_shared_ops,
},
};
@ -296,11 +294,14 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
.flags = RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
@ -308,16 +309,18 @@ static struct gdsc gpu_gx_gdsc = {
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_gx_gdsc",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | SW_RESET,
.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
};
static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
@ -341,6 +344,15 @@ static struct gdsc *gpu_cc_qcm2290_gdscs[] = {
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] = {
&gpu_cc_pll0,
};
static const u32 gpu_cc_qcm2290_critical_cbcrs[] = {
0x1078, /* GPU_CC_AHB_CLK */
0x1060, /* GPU_CC_GX_CXO_CLK */
};
static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -349,6 +361,12 @@ static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data = {
.alpha_plls = gpu_cc_qcm2290_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_qcm2290_plls),
.clk_cbcrs = gpu_cc_qcm2290_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs),
};
static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
.config = &gpu_cc_qcm2290_regmap_config,
@ -358,55 +376,23 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
.num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
.gdscs = gpu_cc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
.use_rpm = true,
.driver_data = &gpu_cc_qcm2290_driver_data,
};
static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
{ .compatible = "qcom,qcm2290-gpucc" },
{ .compatible = "qcom,shikra-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
if (device_is_compatible(&pdev->dev, "qcom,shikra-gpucc"))
gpu_cc_gx_gfx3d_clk_src.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src_shikra;
regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, NULL);
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire ahb clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
}
out_pm_runtime_put:
pm_runtime_put_sync(&pdev->dev);
return 0;
return qcom_cc_probe(pdev, &gpu_cc_qcm2290_desc);
}
static struct platform_driver gpu_cc_qcm2290_driver = {

12
drivers/clk/qcom/gxclkctl-kaanapali.c
View File

@ -6,6 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
@ -25,6 +26,7 @@ static struct gdsc gx_clkctl_gx_gdsc = {
.pd = {
.name = "gx_clkctl_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
.power_off = gdsc_gx_disable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
@ -60,7 +62,15 @@ MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table);
static int gx_clkctl_kaanapali_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gx_clkctl_kaanapali_desc);
int ret;
ret = qcom_cc_probe(pdev, &gx_clkctl_kaanapali_desc);
if (ret)
return ret;
pm_runtime_disable(&pdev->dev);
return ret;
}
static struct platform_driver gx_clkctl_kaanapali_driver = {

75
drivers/clk/qcom/negcc-nord.c
View File

@ -16,7 +16,6 @@
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
@ -41,8 +40,6 @@ enum {
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
};
static struct clk_alpha_pll ne_gcc_gpll0 = {
@ -165,26 +162,6 @@ static const struct clk_parent_data ne_gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map ne_gcc_parent_map_6[] = {
{ P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data ne_gcc_parent_data_6[] = {
{ .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map ne_gcc_parent_map_7[] = {
{ P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data ne_gcc_parent_data_7[] = {
{ .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x33068,
.clkr = {
@ -227,32 +204,30 @@ static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = {
},
};
static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
static struct clk_regmap_phy_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x2a078,
.shift = 0,
.width = 2,
.parent_map = ne_gcc_parent_map_6,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "ne_gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = ne_gcc_parent_data_6,
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_6),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
static struct clk_regmap_phy_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
.reg = 0x2c078,
.shift = 0,
.width = 2,
.parent_map = ne_gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "ne_gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = ne_gcc_parent_data_7,
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_7),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
@ -951,21 +926,6 @@ static struct clk_branch ne_gcc_gp2_clk = {
},
};
static struct clk_branch ne_gcc_gpu_2_cfg_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x34004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "ne_gcc_gpu_2_cfg_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@ -1641,7 +1601,7 @@ static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = {
static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x2a074,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2a074,
.hwcg_bit = 1,
.clkr = {
@ -1697,7 +1657,7 @@ static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = {
static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x2c074,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2c074,
.hwcg_bit = 1,
.clkr = {
@ -1816,7 +1776,6 @@ static struct clk_regmap *ne_gcc_nord_clocks[] = {
[NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr,
[NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr,
[NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr,
[NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr,
[NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr,
[NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr,
[NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr,
@ -1945,10 +1904,16 @@ static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
}
static const u32 ne_gcc_nord_critical_cbcrs[] = {
0x34004, /* NE_GCC_GPU_2_CFG_CLK */
};
static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
.dfs_rcgs = ne_gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
.clk_regs_configure = clk_nord_regs_configure,
.clk_cbcrs = ne_gcc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(ne_gcc_nord_critical_cbcrs),
};
static const struct qcom_cc_desc ne_gcc_nord_desc = {

477
drivers/clk/qcom/tcsrcc-glymur.c
View File

@ -4,262 +4,98 @@
*/
#include <linux/clk-provider.h>
#include <linux/clk/qcom.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
struct tcsrcc_glymur_data {
const struct qcom_clk_ref_desc * const *descs;
size_t num_descs;
};
static struct clk_branch tcsr_edp_clkref_en = {
.halt_reg = 0x60,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x60,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_edp_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx0_rx5_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
"vdda-qrefrx5-0p9",
"vdda-qreftx0-0p9",
"vdda-qreftx0-1p2",
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
.halt_reg = 0x48,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt0_rx0_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrx0-0p9",
};
static struct clk_branch tcsr_pcie_2_clkref_en = {
.halt_reg = 0x4c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x4c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrpt1-0p9",
"vdda-qrefrx1-0p9",
};
static struct clk_branch tcsr_pcie_3_clkref_en = {
.halt_reg = 0x54,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x54,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrpt1-0p9",
"vdda-qrefrpt2-0p9",
"vdda-qrefrx2-0p9",
};
static struct clk_branch tcsr_pcie_4_clkref_en = {
.halt_reg = 0x58,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x58,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] = {
"vdda-refgen4-0p9",
"vdda-refgen4-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt3-0p9",
"vdda-qrefrpt4-0p9",
"vdda-qrefrx4-0p9",
};
static struct clk_branch tcsr_usb2_1_clkref_en = {
.halt_reg = 0x6c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const mahua_tcsr_tx1_rpt01_rx1_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrpt1-0p9",
"vdda-qrefrx1-0p9",
};
static struct clk_branch tcsr_usb2_2_clkref_en = {
.halt_reg = 0x70,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x70,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const mahua_tcsr_tx1_rpt012_rx2_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrpt1-0p9",
"vdda-qrefrpt2-0p9",
"vdda-qrefrx2-0p9",
};
static struct clk_branch tcsr_usb2_3_clkref_en = {
.halt_reg = 0x74,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x74,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
static const char * const mahua_tcsr_tx1_rpt0_rx0_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt0-0p9",
"vdda-qrefrx0-0p9",
};
static struct clk_branch tcsr_usb2_4_clkref_en = {
.halt_reg = 0x88,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x88,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_4_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_0_clkref_en = {
.halt_reg = 0x64,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x64,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_1_clkref_en = {
.halt_reg = 0x68,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_1_clkref_en = {
.halt_reg = 0x44,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x44,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb4_2_clkref_en = {
.halt_reg = 0x5c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb4_2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_glymur_clocks[] = {
[TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr,
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
[TCSR_PCIE_2_CLKREF_EN] = &tcsr_pcie_2_clkref_en.clkr,
[TCSR_PCIE_3_CLKREF_EN] = &tcsr_pcie_3_clkref_en.clkr,
[TCSR_PCIE_4_CLKREF_EN] = &tcsr_pcie_4_clkref_en.clkr,
[TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
[TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
[TCSR_USB2_3_CLKREF_EN] = &tcsr_usb2_3_clkref_en.clkr,
[TCSR_USB2_4_CLKREF_EN] = &tcsr_usb2_4_clkref_en.clkr,
[TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
[TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
[TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr,
[TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr,
static const char * const mahua_tcsr_tx1_rpt345_rx3_regulators[] = {
"vdda-refgen3-0p9",
"vdda-refgen3-1p2",
"vdda-qreftx1-0p9",
"vdda-qrefrpt3-0p9",
"vdda-qrefrpt4-0p9",
"vdda-qrefrpt5-0p9",
"vdda-qrefrx3-0p9",
};
static const struct regmap_config tcsr_cc_glymur_regmap_config = {
@ -270,21 +106,186 @@ static const struct regmap_config tcsr_cc_glymur_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_glymur_desc = {
.config = &tcsr_cc_glymur_regmap_config,
.clks = tcsr_cc_glymur_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_glymur_clocks),
static const struct qcom_clk_ref_desc * const tcsr_cc_glymur_clk_descs[] = {
[TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_edp_clkref_en",
.offset = 0x60,
.regulator_names = glymur_tcsr_tx1_rpt0_rx0_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt0_rx0_regulators),
},
[TCSR_PCIE_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_1_clkref_en",
.offset = 0x48,
.regulator_names = glymur_tcsr_tx0_rx5_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators),
},
[TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_2_clkref_en",
.offset = 0x4c,
.regulator_names = glymur_tcsr_tx1_rpt012_rx2_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators),
},
[TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_3_clkref_en",
.offset = 0x54,
.regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators),
},
[TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_4_clkref_en",
.offset = 0x58,
.regulator_names = glymur_tcsr_tx1_rpt012_rx2_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators),
},
[TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_1_clkref_en",
.offset = 0x6c,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_2_clkref_en",
.offset = 0x70,
.regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators),
},
[TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_3_clkref_en",
.offset = 0x74,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_4_clkref_en",
.offset = 0x88,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb3_0_clkref_en",
.offset = 0x64,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb3_1_clkref_en",
.offset = 0x68,
.regulator_names = glymur_tcsr_tx1_rpt34_rx4_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators),
},
[TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb4_1_clkref_en",
.offset = 0x44,
.regulator_names = glymur_tcsr_tx0_rx5_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators),
},
[TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb4_2_clkref_en",
.offset = 0x5c,
.regulator_names = glymur_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators),
},
};
static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = {
[TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_edp_clkref_en",
.offset = 0x60,
.regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators),
},
[TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_2_clkref_en",
.offset = 0x4c,
.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
},
[TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_3_clkref_en",
.offset = 0x54,
.regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators),
},
[TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_pcie_4_clkref_en",
.offset = 0x58,
.regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators),
},
[TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_1_clkref_en",
.offset = 0x6c,
.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
},
[TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_2_clkref_en",
.offset = 0x70,
.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
},
[TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_3_clkref_en",
.offset = 0x74,
.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
},
[TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb2_4_clkref_en",
.offset = 0x88,
.regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators),
},
[TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb3_0_clkref_en",
.offset = 0x64,
.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
},
[TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb3_1_clkref_en",
.offset = 0x68,
.regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators),
},
[TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb4_1_clkref_en",
.offset = 0x44,
},
[TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) {
.name = "tcsr_usb4_2_clkref_en",
.offset = 0x5c,
.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
},
};
static const struct tcsrcc_glymur_data tcsr_cc_glymur_data = {
.descs = tcsr_cc_glymur_clk_descs,
.num_descs = ARRAY_SIZE(tcsr_cc_glymur_clk_descs),
};
static const struct tcsrcc_glymur_data tcsr_cc_mahua_data = {
.descs = tcsr_cc_mahua_clk_descs,
.num_descs = ARRAY_SIZE(tcsr_cc_mahua_clk_descs),
};
static const struct of_device_id tcsr_cc_glymur_match_table[] = {
{ .compatible = "qcom,glymur-tcsr" },
{ .compatible = "qcom,glymur-tcsr", .data = &tcsr_cc_glymur_data },
{ .compatible = "qcom,mahua-tcsr", .data = &tcsr_cc_mahua_data },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table);
static int tcsr_cc_glymur_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc);
const struct tcsrcc_glymur_data *data = device_get_match_data(&pdev->dev);
if (!data)
return -ENODEV;
return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config,
data->descs, data->num_descs);
}
static struct platform_driver tcsr_cc_glymur_driver = {

839
drivers/clk/qcom/videocc-hawi.c Normal file
View File

@ -0,0 +1,839 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,hawi-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_AHB_CLK,
};
enum {
P_BI_TCXO,
P_VIDEO_CC_PLL0_OUT_EVEN,
P_VIDEO_CC_PLL0_OUT_MAIN,
P_VIDEO_CC_PLL1_OUT_MAIN,
P_VIDEO_CC_PLL2_OUT_MAIN,
P_VIDEO_CC_PLL3_OUT_MAIN,
};
static const struct pll_vco taycan_eha_t_vco[] = {
{ 249600000, 2500000000, 0 },
};
/* 360.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll0_config = {
.l = 0x12,
.cal_l = 0x48,
.alpha = 0xc000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a8060e0,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll0 = {
.offset = 0x0,
.config = &video_cc_pll0_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
static const struct clk_div_table post_div_table_video_cc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv video_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_video_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_video_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_taycan_eha_t_ops,
},
};
/* 300.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll1_config = {
.l = 0xf,
.cal_l = 0x48,
.alpha = 0xa000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a8060e0,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll1 = {
.offset = 0x1000,
.config = &video_cc_pll1_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
/* 300.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll2_config = {
.l = 0xf,
.cal_l = 0x48,
.alpha = 0xa000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a8060e0,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll2 = {
.offset = 0x2000,
.config = &video_cc_pll2_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
/* 300.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll3_config = {
.l = 0xf,
.cal_l = 0x48,
.alpha = 0xa000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a8060e0,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll3 = {
.offset = 0x3000,
.config = &video_cc_pll3_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll3",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL3_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll3.clkr.hw },
};
static const struct parent_map video_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL2_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll2.clkr.hw },
};
static const struct parent_map video_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
{ P_VIDEO_CC_PLL0_OUT_EVEN, 2 },
};
static const struct clk_parent_data video_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll0.clkr.hw },
{ .hw = &video_cc_pll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_ahb_clk_src = {
.cmd_rcgr = 0x8060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_ahb_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(150000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(285000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(311000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(533000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(714000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0a_clk_src[] = {
F(150000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(240000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(338000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(420000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(533000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(630000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(710000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0a_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_mvs0a_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0a_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] = {
F(150000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(311000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(667000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0b_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_3,
.freq_tbl = ftbl_video_cc_mvs0b_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0b_clk_src",
.parent_data = video_cc_parent_data_3,
.num_parents = ARRAY_SIZE(video_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] = {
F(225000000, P_VIDEO_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(430000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(557000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(634000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(782000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(928000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1060000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0c_clk_src = {
.cmd_rcgr = 0x8048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_4,
.freq_tbl = ftbl_video_cc_mvs0c_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk_src",
.parent_data = video_cc_parent_data_4,
.num_parents = ARRAY_SIZE(video_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0x8180,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_ahb_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch video_cc_cx_axi0_clk = {
.halt_reg = 0x81e8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81e8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_cx_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0x80cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch video_cc_mvs0_shift_clk = {
.halt_reg = 0x81a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_vpp0_clk = {
.halt_reg = 0x811c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x811c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x811c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_vpp0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch video_cc_mvs0_vpp0_vpp1_gating_clk = {
.halt_reg = 0x80c8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80c8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_vpp0_vpp1_gating_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_vpp1_clk = {
.halt_reg = 0x80f4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80f4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80f4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_vpp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch video_cc_mvs0a_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0a_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0a_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0b_clk = {
.halt_reg = 0x80b8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80b8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0b_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0b_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x814c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x814c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x814c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_ctl_freerun_clk = {
.halt_reg = 0x8160,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8160,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_ctl_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_debug_clk = {
.halt_reg = 0x8148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_debug_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_freerun_clk = {
.halt_reg = 0x815c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x815c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_shift_clk = {
.halt_reg = 0x81a8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81a8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x8130,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_axi0_cx_int_gdsc = {
.gdscr = 0x81cc,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_axi0_cx_int_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0c_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mm_int_gdsc = {
.gdscr = 0x81b4,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "video_cc_mm_int_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_axi0_cx_int_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_gdsc = {
.gdscr = 0x80a4,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mm_int_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_vpp0_gdsc = {
.gdscr = 0x8108,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_mvs0_vpp0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_vpp1_gdsc = {
.gdscr = 0x80e0,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_mvs0_vpp1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0a_gdsc = {
.gdscr = 0x807c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_mvs0a_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mm_int_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *video_cc_hawi_clocks[] = {
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
[VIDEO_CC_CX_AXI0_CLK] = &video_cc_cx_axi0_clk.clkr,
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
[VIDEO_CC_MVS0_VPP0_CLK] = &video_cc_mvs0_vpp0_clk.clkr,
[VIDEO_CC_MVS0_VPP0_VPP1_GATING_CLK] = &video_cc_mvs0_vpp0_vpp1_gating_clk.clkr,
[VIDEO_CC_MVS0_VPP1_CLK] = &video_cc_mvs0_vpp1_clk.clkr,
[VIDEO_CC_MVS0A_CLK] = &video_cc_mvs0a_clk.clkr,
[VIDEO_CC_MVS0A_CLK_SRC] = &video_cc_mvs0a_clk_src.clkr,
[VIDEO_CC_MVS0B_CLK] = &video_cc_mvs0b_clk.clkr,
[VIDEO_CC_MVS0B_CLK_SRC] = &video_cc_mvs0b_clk_src.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_CLK_SRC] = &video_cc_mvs0c_clk_src.clkr,
[VIDEO_CC_MVS0C_CTL_FREERUN_CLK] = &video_cc_mvs0c_ctl_freerun_clk.clkr,
[VIDEO_CC_MVS0C_DEBUG_CLK] = &video_cc_mvs0c_debug_clk.clkr,
[VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL0_OUT_EVEN] = &video_cc_pll0_out_even.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
[VIDEO_CC_PLL2] = &video_cc_pll2.clkr,
[VIDEO_CC_PLL3] = &video_cc_pll3.clkr,
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
};
static struct gdsc *video_cc_hawi_gdscs[] = {
[VIDEO_CC_AXI0_CX_INT_GDSC] = &video_cc_axi0_cx_int_gdsc,
[VIDEO_CC_MM_INT_GDSC] = &video_cc_mm_int_gdsc,
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
[VIDEO_CC_MVS0_VPP0_GDSC] = &video_cc_mvs0_vpp0_gdsc,
[VIDEO_CC_MVS0_VPP1_GDSC] = &video_cc_mvs0_vpp1_gdsc,
[VIDEO_CC_MVS0A_GDSC] = &video_cc_mvs0a_gdsc,
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
};
static const struct qcom_reset_map video_cc_hawi_resets[] = {
[VIDEO_CC_AXI0_CX_INT_BCR] = { 0x81c8 },
[VIDEO_CC_INTERFACE_BCR] = { 0x8164 },
[VIDEO_CC_MM_INT_BCR] = { 0x81b0 },
[VIDEO_CC_MVS0_BCR] = { 0x80a0 },
[VIDEO_CC_MVS0_VPP0_BCR] = { 0x8104 },
[VIDEO_CC_MVS0_VPP1_BCR] = { 0x80dc },
[VIDEO_CC_MVS0A_BCR] = { 0x8078 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x814c, 2 },
[VIDEO_CC_MVS0C_BCR] = { 0x812c },
[VIDEO_CC_MVS0C_CTL_FREERUN_CLK_ARES] = { 0x8160, 2 },
[VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x815c, 2 },
[VIDEO_CC_XO_CLK_ARES] = { 0x8198, 2 },
};
static struct clk_alpha_pll *video_cc_hawi_plls[] = {
&video_cc_pll0,
&video_cc_pll1,
&video_cc_pll2,
&video_cc_pll3,
};
static const u32 video_cc_hawi_critical_cbcrs[] = {
0x8168, /* VIDEO_CC_AHB_CLK */
0x81e4, /* VIDEO_CC_CX_DBGCH_XO_CLK */
0x81e0, /* VIDEO_CC_CX_XO_CLK */
0x81a0, /* VIDEO_CC_DBGCH_XO_CLK */
0x81ac, /* VIDEO_CC_SLEEP_CLK */
0x819c, /* VIDEO_CC_TS_XO_CLK */
0x8198, /* VIDEO_CC_XO_CLK */
};
static const struct regmap_config video_cc_hawi_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xa018,
.fast_io = true,
};
static struct qcom_cc_driver_data video_cc_hawi_driver_data = {
.alpha_plls = video_cc_hawi_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_hawi_plls),
.clk_cbcrs = video_cc_hawi_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(video_cc_hawi_critical_cbcrs),
};
static const struct qcom_cc_desc video_cc_hawi_desc = {
.config = &video_cc_hawi_regmap_config,
.clks = video_cc_hawi_clocks,
.num_clks = ARRAY_SIZE(video_cc_hawi_clocks),
.resets = video_cc_hawi_resets,
.num_resets = ARRAY_SIZE(video_cc_hawi_resets),
.gdscs = video_cc_hawi_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_hawi_gdscs),
.use_rpm = true,
.driver_data = &video_cc_hawi_driver_data,
};
static const struct of_device_id video_cc_hawi_match_table[] = {
{ .compatible = "qcom,hawi-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_hawi_match_table);
static int video_cc_hawi_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &video_cc_hawi_desc);
}
static struct platform_driver video_cc_hawi_driver = {
.probe = video_cc_hawi_probe,
.driver = {
.name = "videocc-hawi",
.of_match_table = video_cc_hawi_match_table,
},
};
module_platform_driver(video_cc_hawi_driver);
MODULE_DESCRIPTION("QTI VIDEOCC Hawi Driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,maili-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
#define ACCU_CFG_MASK GENMASK(25, 21)
enum {
DT_BI_TCXO,
DT_AHB_CLK,
};
enum {
P_BI_TCXO,
P_VIDEO_CC_PLL0_OUT_MAIN,
P_VIDEO_CC_PLL1_OUT_MAIN,
P_VIDEO_CC_PLL2_OUT_MAIN,
};
static const struct pll_vco taycan_eha_t_vco[] = {
{ 249600000, 2500000000, 0 },
};
/* 360.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll0_config = {
.l = 0x12,
.cal_l = 0x42,
.alpha = 0xc000,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll0 = {
.offset = 0x0,
.config = &video_cc_pll0_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
/* 480.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll1_config = {
.l = 0x19,
.cal_l = 0x42,
.alpha = 0x0,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll1 = {
.offset = 0x1000,
.config = &video_cc_pll1_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
/* 480.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll2_config = {
.l = 0x19,
.cal_l = 0x42,
.alpha = 0x0,
.config_ctl_val = 0xa5c400e7,
.config_ctl_hi_val = 0x0a806160,
.config_ctl_hi1_val = 0xf51dea20,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000002,
};
static struct clk_alpha_pll video_cc_pll2 = {
.offset = 0x2000,
.config = &video_cc_pll2_config,
.vco_table = taycan_eha_t_vco,
.num_vco = ARRAY_SIZE(taycan_eha_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_taycan_eha_t_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL2_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll2.clkr.hw },
};
static const struct parent_map video_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll0.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_ahb_clk_src = {
.cmd_rcgr = 0x8060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_ahb_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_ahb_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(338000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(600000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(800000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(1000000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] = {
F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(338000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
F(800000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0b_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_mvs0b_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0b_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] = {
F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(507000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(630000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(666000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(800000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1104000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0c_clk_src = {
.cmd_rcgr = 0x8048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_3,
.freq_tbl = ftbl_video_cc_mvs0c_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk_src",
.parent_data = video_cc_parent_data_3,
.num_parents = ARRAY_SIZE(video_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0x8194,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0x80d0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80d0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80d0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_mem_branch video_cc_mvs0_freerun_clk = {
.mem_enable_reg = 0x80e4,
.mem_ack_reg = 0x80e4,
.mem_enable_mask = BIT(3),
.mem_enable_ack_mask = GENMASK(11, 10),
.mem_enable_invert = true,
.branch = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80e0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_mem_ops,
},
},
},
};
static struct clk_branch video_cc_mvs0_shift_clk = {
.halt_reg = 0x81b4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81b4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_vpp0_clk = {
.halt_reg = 0x8134,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8134,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_vpp0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_vpp0_freerun_clk = {
.halt_reg = 0x8144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_vpp0_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0b_clk = {
.halt_reg = 0x80bc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80bc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0b_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0b_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0b_freerun_clk = {
.halt_reg = 0x80cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0b_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0b_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8164,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8164,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_debug_clk = {
.halt_reg = 0x81c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x81c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_debug_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_freerun_clk = {
.halt_reg = 0x8174,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8174,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_freerun_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_shift_clk = {
.halt_reg = 0x81b8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81b8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x814c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_gdsc = {
.gdscr = 0x80a8,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0_gdsc",
},
.parent = &video_cc_mvs0c_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_vpp0_gdsc = {
.gdscr = 0x8120,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_mvs0_vpp0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *video_cc_maili_clocks[] = {
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.branch.clkr,
[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
[VIDEO_CC_MVS0_VPP0_CLK] = &video_cc_mvs0_vpp0_clk.clkr,
[VIDEO_CC_MVS0_VPP0_FREERUN_CLK] = &video_cc_mvs0_vpp0_freerun_clk.clkr,
[VIDEO_CC_MVS0B_CLK] = &video_cc_mvs0b_clk.clkr,
[VIDEO_CC_MVS0B_CLK_SRC] = &video_cc_mvs0b_clk_src.clkr,
[VIDEO_CC_MVS0B_FREERUN_CLK] = &video_cc_mvs0b_freerun_clk.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_CLK_SRC] = &video_cc_mvs0c_clk_src.clkr,
[VIDEO_CC_MVS0C_DEBUG_CLK] = &video_cc_mvs0c_debug_clk.clkr,
[VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
[VIDEO_CC_PLL2] = &video_cc_pll2.clkr,
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
};
static struct gdsc *video_cc_maili_gdscs[] = {
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
[VIDEO_CC_MVS0_VPP0_GDSC] = &video_cc_mvs0_vpp0_gdsc,
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
};
static const struct qcom_reset_map video_cc_maili_resets[] = {
[VIDEO_CC_INTERFACE_BCR] = { 0x8178 },
[VIDEO_CC_MVS0_BCR] = { 0x80a4 },
[VIDEO_CC_MVS0_CLK_ARES] = { 0x80d0, 2 },
[VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x80e0, 2 },
[VIDEO_CC_MVS0_VPP0_BCR] = { 0x811c },
[VIDEO_CC_MVS0C_BCR] = { 0x8148 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8164, 2 },
[VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x8174, 2 },
[VIDEO_CC_XO_CLK_ARES] = { 0x81ac, 2 },
};
static struct clk_alpha_pll *video_cc_maili_plls[] = {
&video_cc_pll0,
&video_cc_pll1,
&video_cc_pll2,
};
static const u32 video_cc_maili_critical_cbcrs[] = {
0x817c, /* VIDEO_CC_AHB_CLK */
0x81bc, /* VIDEO_CC_SLEEP_CLK */
0x81b0, /* VIDEO_CC_TS_XO_CLK */
0x81ac, /* VIDEO_CC_XO_CLK */
};
static const struct regmap_config video_cc_maili_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xa010,
.fast_io = true,
};
static void clk_maili_regs_configure(struct device *dev, struct regmap *regmap)
{
/*
* Enable clk_on sync for MVS0 and VPP clocks as per the
* hardware recommendation.
*/
regmap_set_bits(regmap, 0x9f24, BIT(0));
/*
* Update ACCU configuration for MVS0 CFG3, MVS0 VPP0 CFG3,
* MVS0C CFG3 GDSCRs as per the hardware recommendation.
*/
regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK);
regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK);
regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK);
}
static const struct qcom_cc_driver_data video_cc_maili_driver_data = {
.alpha_plls = video_cc_maili_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_maili_plls),
.clk_cbcrs = video_cc_maili_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(video_cc_maili_critical_cbcrs),
.clk_regs_configure = clk_maili_regs_configure,
};
static const struct qcom_cc_desc video_cc_maili_desc = {
.config = &video_cc_maili_regmap_config,
.clks = video_cc_maili_clocks,
.num_clks = ARRAY_SIZE(video_cc_maili_clocks),
.resets = video_cc_maili_resets,
.num_resets = ARRAY_SIZE(video_cc_maili_resets),
.gdscs = video_cc_maili_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_maili_gdscs),
.use_rpm = true,
.driver_data = &video_cc_maili_driver_data,
};
static const struct of_device_id video_cc_maili_match_table[] = {
{ .compatible = "qcom,maili-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_maili_match_table);
static int video_cc_maili_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &video_cc_maili_desc);
}
static struct platform_driver video_cc_maili_driver = {
.probe = video_cc_maili_probe,
.driver = {
.name = "videocc-maili",
.of_match_table = video_cc_maili_match_table,
},
};
module_platform_driver(video_cc_maili_driver);
MODULE_DESCRIPTION("QTI VIDEOCC Maili Driver");
MODULE_LICENSE("GPL");

4
drivers/clk/qcom/videocc-x1p42100.c
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@ -526,7 +526,7 @@ static struct clk_alpha_pll *video_cc_x1p42100_plls[] = {
&video_cc_pll1,
};
static u32 video_cc_x1p42100_critical_cbcrs[] = {
static const u32 video_cc_x1p42100_critical_cbcrs[] = {
0x80f4, /* VIDEO_CC_AHB_CLK */
0x8150, /* VIDEO_CC_SLEEP_CLK */
0x8124, /* VIDEO_CC_XO_CLK */
@ -540,7 +540,7 @@ static const struct regmap_config video_cc_x1p42100_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data video_cc_x1p42100_driver_data = {
static const struct qcom_cc_driver_data video_cc_x1p42100_driver_data = {
.alpha_plls = video_cc_x1p42100_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_x1p42100_plls),
.clk_cbcrs = video_cc_x1p42100_critical_cbcrs,

1
include/dt-bindings/clock/qcom,gcc-mdm9607.h
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@ -13,7 +13,6 @@
#define GPLL2 4
#define GPLL2_EARLY 5
#define PCNOC_BFDCD_CLK_SRC 6
#define SYSTEM_NOC_BFDCD_CLK_SRC 7
#define GCC_SMMU_CFG_CLK 8
#define APSS_AHB_CLK_SRC 9
#define GCC_QDSS_DAP_CLK 10

122
include/dt-bindings/clock/qcom,glymur-camcc.h Normal file
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@ -0,0 +1,122 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_CAMNOC_AXI_NRT_CLK 4
#define CAM_CC_CAMNOC_AXI_RT_CLK 5
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6
#define CAM_CC_CAMNOC_DCD_XO_CLK 7
#define CAM_CC_CAMNOC_XO_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPAS_BPS_CLK 15
#define CAM_CC_CPAS_FAST_AHB_CLK 16
#define CAM_CC_CPAS_IFE_0_CLK 17
#define CAM_CC_CPAS_IFE_1_CLK 18
#define CAM_CC_CPAS_IFE_LITE_CLK 19
#define CAM_CC_CPAS_IPE_NPS_CLK 20
#define CAM_CC_CPHY_RX_CLK_SRC 21
#define CAM_CC_CSI0PHYTIMER_CLK 22
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23
#define CAM_CC_CSI1PHYTIMER_CLK 24
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25
#define CAM_CC_CSI4PHYTIMER_CLK 26
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27
#define CAM_CC_CSID_CLK 28
#define CAM_CC_CSID_CLK_SRC 29
#define CAM_CC_CSID_CSIPHY_RX_CLK 30
#define CAM_CC_CSIPHY0_CLK 31
#define CAM_CC_CSIPHY1_CLK 32
#define CAM_CC_CSIPHY4_CLK 33
#define CAM_CC_FAST_AHB_CLK_SRC 34
#define CAM_CC_GDSC_CLK 35
#define CAM_CC_ICP_AHB_CLK 36
#define CAM_CC_ICP_CLK 37
#define CAM_CC_ICP_CLK_SRC 38
#define CAM_CC_IFE_0_CLK 39
#define CAM_CC_IFE_0_CLK_SRC 40
#define CAM_CC_IFE_0_DSP_CLK 41
#define CAM_CC_IFE_0_FAST_AHB_CLK 42
#define CAM_CC_IFE_1_CLK 43
#define CAM_CC_IFE_1_CLK_SRC 44
#define CAM_CC_IFE_1_DSP_CLK 45
#define CAM_CC_IFE_1_FAST_AHB_CLK 46
#define CAM_CC_IFE_LITE_AHB_CLK 47
#define CAM_CC_IFE_LITE_CLK 48
#define CAM_CC_IFE_LITE_CLK_SRC 49
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 50
#define CAM_CC_IFE_LITE_CSID_CLK 51
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 52
#define CAM_CC_IPE_NPS_AHB_CLK 53
#define CAM_CC_IPE_NPS_CLK 54
#define CAM_CC_IPE_NPS_CLK_SRC 55
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 56
#define CAM_CC_IPE_PPS_CLK 57
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 58
#define CAM_CC_JPEG_CLK 59
#define CAM_CC_JPEG_CLK_SRC 60
#define CAM_CC_MCLK0_CLK 61
#define CAM_CC_MCLK0_CLK_SRC 62
#define CAM_CC_MCLK1_CLK 63
#define CAM_CC_MCLK1_CLK_SRC 64
#define CAM_CC_MCLK2_CLK 65
#define CAM_CC_MCLK2_CLK_SRC 66
#define CAM_CC_MCLK3_CLK 67
#define CAM_CC_MCLK3_CLK_SRC 68
#define CAM_CC_MCLK4_CLK 69
#define CAM_CC_MCLK4_CLK_SRC 70
#define CAM_CC_MCLK5_CLK 71
#define CAM_CC_MCLK5_CLK_SRC 72
#define CAM_CC_MCLK6_CLK 73
#define CAM_CC_MCLK6_CLK_SRC 74
#define CAM_CC_MCLK7_CLK 75
#define CAM_CC_MCLK7_CLK_SRC 76
#define CAM_CC_PLL0 77
#define CAM_CC_PLL0_OUT_EVEN 78
#define CAM_CC_PLL0_OUT_ODD 79
#define CAM_CC_PLL1 80
#define CAM_CC_PLL1_OUT_EVEN 81
#define CAM_CC_PLL2 82
#define CAM_CC_PLL3 83
#define CAM_CC_PLL3_OUT_EVEN 84
#define CAM_CC_PLL4 85
#define CAM_CC_PLL4_OUT_EVEN 86
#define CAM_CC_PLL5 87
#define CAM_CC_PLL5_OUT_EVEN 88
#define CAM_CC_QDSS_DEBUG_CLK 89
#define CAM_CC_QDSS_DEBUG_CLK_SRC 90
#define CAM_CC_QDSS_DEBUG_XO_CLK 91
#define CAM_CC_SLEEP_CLK 92
#define CAM_CC_SLEEP_CLK_SRC 93
#define CAM_CC_SLOW_AHB_CLK_SRC 94
#define CAM_CC_XO_CLK_SRC 95
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0
#define CAM_CC_IFE_0_GDSC 1
#define CAM_CC_IFE_1_GDSC 2
#define CAM_CC_IPE_0_GDSC 3
#define CAM_CC_TITAN_TOP_GDSC 4
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IFE_0_BCR 2
#define CAM_CC_IFE_1_BCR 3
#define CAM_CC_IPE_0_BCR 4
#define CAM_CC_QDSS_DEBUG_BCR 5
#endif

38
include/dt-bindings/clock/qcom,glymur-evacc.h Normal file
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@ -0,0 +1,38 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H
/* EVA_CC clocks */
#define EVA_CC_AHB_CLK 0
#define EVA_CC_AHB_CLK_SRC 1
#define EVA_CC_MVS0_CLK 2
#define EVA_CC_MVS0_CLK_SRC 3
#define EVA_CC_MVS0_DIV_CLK_SRC 4
#define EVA_CC_MVS0_FREERUN_CLK 5
#define EVA_CC_MVS0_SHIFT_CLK 6
#define EVA_CC_MVS0C_CLK 7
#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define EVA_CC_MVS0C_FREERUN_CLK 9
#define EVA_CC_MVS0C_SHIFT_CLK 10
#define EVA_CC_PLL0 11
#define EVA_CC_SLEEP_CLK 12
#define EVA_CC_SLEEP_CLK_SRC 13
#define EVA_CC_XO_CLK 14
#define EVA_CC_XO_CLK_SRC 15
/* EVA_CC power domains */
#define EVA_CC_MVS0_GDSC 0
#define EVA_CC_MVS0C_GDSC 1
/* EVA_CC resets */
#define EVA_CC_INTERFACE_BCR 0
#define EVA_CC_MVS0_BCR 1
#define EVA_CC_MVS0C_CLK_ARES 2
#define EVA_CC_MVS0C_BCR 3
#define EVA_CC_MVS0C_FREERUN_CLK_ARES 4
#endif /* _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H */

64
include/dt-bindings/clock/qcom,hawi-videocc.h Normal file
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@ -0,0 +1,64 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_HAWI_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_HAWI_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_CX_AXI0_CLK 2
#define VIDEO_CC_CX_DBGCH_XO_CLK 3
#define VIDEO_CC_CX_XO_CLK 4
#define VIDEO_CC_DBGCH_XO_CLK 5
#define VIDEO_CC_MVS0_CLK 6
#define VIDEO_CC_MVS0_CLK_SRC 7
#define VIDEO_CC_MVS0_SHIFT_CLK 8
#define VIDEO_CC_MVS0_VPP0_CLK 9
#define VIDEO_CC_MVS0_VPP0_VPP1_GATING_CLK 10
#define VIDEO_CC_MVS0_VPP1_CLK 11
#define VIDEO_CC_MVS0A_CLK 12
#define VIDEO_CC_MVS0A_CLK_SRC 13
#define VIDEO_CC_MVS0B_CLK 14
#define VIDEO_CC_MVS0B_CLK_SRC 15
#define VIDEO_CC_MVS0C_CLK 16
#define VIDEO_CC_MVS0C_CLK_SRC 17
#define VIDEO_CC_MVS0C_CTL_FREERUN_CLK 18
#define VIDEO_CC_MVS0C_DEBUG_CLK 19
#define VIDEO_CC_MVS0C_FREERUN_CLK 20
#define VIDEO_CC_MVS0C_SHIFT_CLK 21
#define VIDEO_CC_PLL0 22
#define VIDEO_CC_PLL0_OUT_EVEN 23
#define VIDEO_CC_PLL1 24
#define VIDEO_CC_PLL2 25
#define VIDEO_CC_PLL3 26
#define VIDEO_CC_SLEEP_CLK 27
#define VIDEO_CC_XO_CLK 28
#define VIDEO_CC_XO_CLK_SRC 29
/* VIDEO_CC power domains */
#define VIDEO_CC_AXI0_CX_INT_GDSC 0
#define VIDEO_CC_MM_INT_GDSC 1
#define VIDEO_CC_MVS0_GDSC 2
#define VIDEO_CC_MVS0_VPP0_GDSC 3
#define VIDEO_CC_MVS0_VPP1_GDSC 4
#define VIDEO_CC_MVS0A_GDSC 5
#define VIDEO_CC_MVS0C_GDSC 6
/* VIDEO_CC resets */
#define VIDEO_CC_AXI0_CX_INT_BCR 0
#define VIDEO_CC_INTERFACE_BCR 1
#define VIDEO_CC_MM_INT_BCR 2
#define VIDEO_CC_MVS0_BCR 3
#define VIDEO_CC_MVS0_VPP0_BCR 4
#define VIDEO_CC_MVS0_VPP1_BCR 5
#define VIDEO_CC_MVS0A_BCR 6
#define VIDEO_CC_MVS0C_CLK_ARES 7
#define VIDEO_CC_MVS0C_BCR 8
#define VIDEO_CC_MVS0C_CTL_FREERUN_CLK_ARES 9
#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 10
#define VIDEO_CC_XO_CLK_ARES 11
#endif

5
include/dt-bindings/clock/qcom,ipq9650-gcc.h
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@ -169,4 +169,9 @@
#define GPLL2 160
#define GPLL2_OUT_MAIN 161
#define GPLL4 162
#define GCC_REFGEN_CORE_CLK_SRC 163
#define GCC_REFGEN_PCIE_CORE_CLK 164
#define GCC_REFGEN_PCIE_HCLK 165
#define GCC_REFGEN_CMN_UPHY_HCLK 166
#define GCC_REFGEN_CMN_UPHY_CORE_CLK 167
#endif

21
include/dt-bindings/clock/qcom,maili-gcc.h Normal file
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@ -0,0 +1,21 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MAILI_H
#define _DT_BINDINGS_CLK_QCOM_GCC_MAILI_H
#include "qcom,hawi-gcc.h"
/* Maili has below additional clocks on top of Hawi */
#define GCC_QUPV3_WRAP5_CORE_2X_CLK 188
#define GCC_QUPV3_WRAP5_CORE_CLK 189
#define GCC_QUPV3_WRAP5_QSPI_REF_CLK 190
#define GCC_QUPV3_WRAP5_QSPI_REF_CLK_SRC 191
#define GCC_QUPV3_WRAP5_S0_CLK 192
#define GCC_QUPV3_WRAP5_S0_CLK_SRC 193
#define GCC_QUPV3_WRAP_5_M_AHB_CLK 194
#define GCC_QUPV3_WRAP_5_S_AHB_CLK 195
#endif

50
include/dt-bindings/clock/qcom,maili-videocc.h Normal file
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@ -0,0 +1,50 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_MVS0_CLK 2
#define VIDEO_CC_MVS0_CLK_SRC 3
#define VIDEO_CC_MVS0_FREERUN_CLK 4
#define VIDEO_CC_MVS0_SHIFT_CLK 5
#define VIDEO_CC_MVS0_VPP0_CLK 6
#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7
#define VIDEO_CC_MVS0B_CLK 8
#define VIDEO_CC_MVS0B_CLK_SRC 9
#define VIDEO_CC_MVS0B_FREERUN_CLK 10
#define VIDEO_CC_MVS0C_CLK 11
#define VIDEO_CC_MVS0C_CLK_SRC 12
#define VIDEO_CC_MVS0C_DEBUG_CLK 13
#define VIDEO_CC_MVS0C_FREERUN_CLK 14
#define VIDEO_CC_MVS0C_SHIFT_CLK 15
#define VIDEO_CC_PLL0 16
#define VIDEO_CC_PLL1 17
#define VIDEO_CC_PLL2 18
#define VIDEO_CC_SLEEP_CLK 19
#define VIDEO_CC_TS_XO_CLK 20
#define VIDEO_CC_XO_CLK 21
#define VIDEO_CC_XO_CLK_SRC 22
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0_GDSC 0
#define VIDEO_CC_MVS0_VPP0_GDSC 1
#define VIDEO_CC_MVS0C_GDSC 2
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0_CLK_ARES 2
#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 3
#define VIDEO_CC_MVS0_VPP0_BCR 4
#define VIDEO_CC_MVS0C_BCR 5
#define VIDEO_CC_MVS0C_CLK_ARES 6
#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 7
#define VIDEO_CC_XO_CLK_ARES 8
#endif

115
include/dt-bindings/clock/qcom,nord-dispcc.h Normal file
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@ -0,0 +1,115 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H
/* DISP_CC_0 and DISP_CC_1 clocks */
#define MDSS_DISP_CC_ACMU_CLK 0
#define MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK 1
#define MDSS_DISP_CC_MDSS_AHB1_CLK 2
#define MDSS_DISP_CC_MDSS_AHB_CLK 3
#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 4
#define MDSS_DISP_CC_MDSS_BYTE0_CLK 5
#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 6
#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 8
#define MDSS_DISP_CC_MDSS_BYTE1_CLK 9
#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 10
#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 11
#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 12
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 13
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 14
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 15
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 16
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 17
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 18
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 19
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 20
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 21
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 22
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 23
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 24
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 25
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 26
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 27
#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 29
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 31
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK 40
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC 41
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK 42
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC 43
#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 44
#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK 45
#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 46
#define MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK 47
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK 48
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 49
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 50
#define MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 51
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK 52
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 53
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK 54
#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 55
#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK 56
#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 57
#define MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK 58
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK 59
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 60
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 61
#define MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62
#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63
#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64
#define MDSS_DISP_CC_MDSS_ESC0_CLK 65
#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 66
#define MDSS_DISP_CC_MDSS_ESC1_CLK 67
#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 68
#define MDSS_DISP_CC_MDSS_MDP1_CLK 69
#define MDSS_DISP_CC_MDSS_MDP_CLK 70
#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 71
#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 72
#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 73
#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 74
#define MDSS_DISP_CC_MDSS_PCLK0_CLK 75
#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 76
#define MDSS_DISP_CC_MDSS_PCLK1_CLK 77
#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 78
#define MDSS_DISP_CC_MDSS_PCLK2_CLK 79
#define MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC 80
#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 81
#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 82
#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 83
#define MDSS_DISP_CC_MDSS_VSYNC_CLK 84
#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 85
#define MDSS_DISP_CC_PLL0 86
#define MDSS_DISP_CC_PLL1 87
#define MDSS_DISP_CC_PLL2 88
#define MDSS_DISP_CC_PLL3 89
#define MDSS_DISP_CC_SLEEP_CLK 90
#define MDSS_DISP_CC_SLEEP_CLK_SRC 91
#define MDSS_DISP_CC_SM_DIV_CLK_SRC 92
#define MDSS_DISP_CC_XO_CLK 93
#define MDSS_DISP_CC_XO_CLK_SRC 94
/* DISP_CC_0 and DISP_CC_1 power domains */
#define MDSS_DISP_CC_MDSS_CORE_GDSC 0
#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC_0 and DISP_CC_1 resets */
#define MDSS_DISP_CC_MDSS_CORE_BCR 0
#define MDSS_DISP_CC_MDSS_CORE_INT2_BCR 1
#define MDSS_DISP_CC_MDSS_RSCC_BCR 2
#endif

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include/dt-bindings/clock/qcom,nord-gpu2cc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_2_CC_NORD_H
#define _DT_BINDINGS_CLK_QCOM_GPU_2_CC_NORD_H
/* GPU_2_CC clocks */
#define GPU_2_CC_AHB_CLK 0
#define GPU_2_CC_CRC_AHB_CLK 1
#define GPU_2_CC_CX_ACCU_SHIFT_CLK 2
#define GPU_2_CC_CX_FF_CLK 3
#define GPU_2_CC_CX_GMU_CLK 4
#define GPU_2_CC_CXO_AON_CLK 5
#define GPU_2_CC_CXO_CLK 6
#define GPU_2_CC_DEMET_CLK 7
#define GPU_2_CC_FF_CLK_SRC 8
#define GPU_2_CC_FREQ_MEASURE_CLK 9
#define GPU_2_CC_GMU_CLK_SRC 10
#define GPU_2_CC_GPU_SMMU_VOTE_CLK 11
#define GPU_2_CC_HUB_AON_CLK 12
#define GPU_2_CC_HUB_CLK_SRC 13
#define GPU_2_CC_HUB_CX_INT_CLK 14
#define GPU_2_CC_MEMNOC_GFX_CLK 15
#define GPU_2_CC_MND1X_0_GFX3D_CLK 16
#define GPU_2_CC_MND1X_1_GFX3D_CLK 17
#define GPU_2_CC_PLL0 18
#define GPU_2_CC_PLL1 19
#define GPU_2_CC_SLEEP_CLK 20
/* GPU_2_CC power domains */
#define GPU_2_CC_CX_GDSC 0
#define GPU_2_CC_GX_GDSC 1
/* GPU_2_CC resets */
#define GPU_2_CC_ACD_BCR 0
#define GPU_2_CC_CB_BCR 1
#define GPU_2_CC_CX_BCR 2
#define GPU_2_CC_FAST_HUB_BCR 3
#define GPU_2_CC_FF_BCR 4
#define GPU_2_CC_GFX3D_AON_BCR 5
#define GPU_2_CC_GMU_BCR 6
#define GPU_2_CC_GX_BCR 7
#define GPU_2_CC_XO_BCR 8
#endif

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include/dt-bindings/clock/qcom,nord-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H
/* GPU_CC clocks */
#define GPU_CC_ACD_GFX3D_CLK 0
#define GPU_CC_ACMU_CLK 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CRC_AHB_CLK 3
#define GPU_CC_CX_ACCU_SHIFT_CLK 4
#define GPU_CC_CX_FF_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_DEMET_CLK 9
#define GPU_CC_DPM_CLK 10
#define GPU_CC_FF_CLK_SRC 11
#define GPU_CC_FREQ_MEASURE_CLK 12
#define GPU_CC_GMU_CLK_SRC 13
#define GPU_CC_GPU_SMMU_VOTE_CLK 14
#define GPU_CC_HUB_AON_CLK 15
#define GPU_CC_HUB_CLK_SRC 16
#define GPU_CC_HUB_CX_INT_CLK 17
#define GPU_CC_HUB_DIV_CLK_SRC 18
#define GPU_CC_MEMNOC_GFX_CLK 19
#define GPU_CC_MND1X_GFX3D_CLK 20
#define GPU_CC_PLL0 21
#define GPU_CC_PLL1 22
#define GPU_CC_SLEEP_CLK 23
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_ACD_BCR 0
#define GPU_CC_CB_BCR 1
#define GPU_CC_CX_BCR 2
#define GPU_CC_FAST_HUB_BCR 3
#define GPU_CC_GFX3D_AON_BCR 4
#define GPU_CC_GX_BCR 5
#define GPU_CC_XO_BCR 6
#endif

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include/dt-bindings/clock/qcom,shikra-audiocorecc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H
#define _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H
/* AUDIO_CORE_CC clocks */
#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX 0
#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX2 1
#define AUDIO_CORE_CC_DIG_PLL 2
#define AUDIO_CORE_CC_AIF_IF0_CLK_SRC 3
#define AUDIO_CORE_CC_AIF_IF0_EBIT_CLK 4
#define AUDIO_CORE_CC_AIF_IF0_IBIT_CLK 5
#define AUDIO_CORE_CC_AIF_IF1_CLK_SRC 6
#define AUDIO_CORE_CC_AIF_IF1_EBIT_CLK 7
#define AUDIO_CORE_CC_AIF_IF1_IBIT_CLK 8
#define AUDIO_CORE_CC_AIF_IF2_CLK_SRC 9
#define AUDIO_CORE_CC_AIF_IF2_EBIT_CLK 10
#define AUDIO_CORE_CC_AIF_IF2_IBIT_CLK 11
#define AUDIO_CORE_CC_AIF_IF3_CLK_SRC 12
#define AUDIO_CORE_CC_AIF_IF3_EBIT_CLK 13
#define AUDIO_CORE_CC_AIF_IF3_IBIT_CLK 14
#define AUDIO_CORE_CC_AUD_DMA_CLK 15
#define AUDIO_CORE_CC_AUD_DMA_CLK_SRC 16
#define AUDIO_CORE_CC_AUD_DMA_MEM_CLK 17
#define AUDIO_CORE_CC_BUS_CLK 18
#define AUDIO_CORE_CC_BUS_CLK_SRC 19
#define AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC 20
#define AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC 21
#define AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK 22
#define AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC 23
#define AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK 24
#define AUDIO_CORE_CC_IM_SLEEP_CLK 25
#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK 26
#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC 27
#define AUDIO_CORE_CC_RX_MCLK_2X_CLK 28
#define AUDIO_CORE_CC_RX_MCLK_CLK 29
#define AUDIO_CORE_CC_SAMPLING_CLK 30
#define AUDIO_CORE_CC_TX_MCLK_2X_CLK 31
#define AUDIO_CORE_CC_TX_MCLK_CLK 32
#define AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC 33
/* AUDIO_CORE_CSR resets */
#define AUDIO_CORE_CSR_RX_SWR_CGCR 0
#define AUDIO_CORE_CSR_TX_SWR_CGCR 1
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
/* GCC clocks */
#define GPLL0 0
#define GPLL0_OUT_AUX2 1
#define GPLL1 2
#define GPLL10 3
#define GPLL11 4
#define GPLL12 5
#define GPLL12_OUT_AUX2 6
#define GPLL3 7
#define GPLL3_OUT_MAIN 8
#define GPLL4 9
#define GPLL5 10
#define GPLL6 11
#define GPLL6_OUT_MAIN 12
#define GPLL7 13
#define GPLL8 14
#define GPLL8_OUT_MAIN 15
#define GPLL9 16
#define GPLL9_OUT_MAIN 17
#define GCC_AHB2PHY_CSI_CLK 18
#define GCC_AHB2PHY_USB_CLK 19
#define GCC_BOOT_ROM_AHB_CLK 20
#define GCC_CAM_THROTTLE_NRT_CLK 21
#define GCC_CAM_THROTTLE_RT_CLK 22
#define GCC_CAMERA_AHB_CLK 23
#define GCC_CAMERA_XO_CLK 24
#define GCC_CAMSS_AXI_CLK 25
#define GCC_CAMSS_AXI_CLK_SRC 26
#define GCC_CAMSS_CAMNOC_ATB_CLK 27
#define GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK 28
#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 29
#define GCC_CAMSS_CCI_0_CLK 30
#define GCC_CAMSS_CCI_CLK_SRC 31
#define GCC_CAMSS_CPHY_0_CLK 32
#define GCC_CAMSS_CPHY_1_CLK 33
#define GCC_CAMSS_CSI0PHYTIMER_CLK 34
#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 35
#define GCC_CAMSS_CSI1PHYTIMER_CLK 36
#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 37
#define GCC_CAMSS_MCLK0_CLK 38
#define GCC_CAMSS_MCLK0_CLK_SRC 39
#define GCC_CAMSS_MCLK1_CLK 40
#define GCC_CAMSS_MCLK1_CLK_SRC 41
#define GCC_CAMSS_MCLK2_CLK 42
#define GCC_CAMSS_MCLK2_CLK_SRC 43
#define GCC_CAMSS_MCLK3_CLK 44
#define GCC_CAMSS_MCLK3_CLK_SRC 45
#define GCC_CAMSS_NRT_AXI_CLK 46
#define GCC_CAMSS_OPE_AHB_CLK 47
#define GCC_CAMSS_OPE_AHB_CLK_SRC 48
#define GCC_CAMSS_OPE_CLK 49
#define GCC_CAMSS_OPE_CLK_SRC 50
#define GCC_CAMSS_RT_AXI_CLK 51
#define GCC_CAMSS_TFE_0_CLK 52
#define GCC_CAMSS_TFE_0_CLK_SRC 53
#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 54
#define GCC_CAMSS_TFE_0_CSID_CLK 55
#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 56
#define GCC_CAMSS_TFE_1_CLK 57
#define GCC_CAMSS_TFE_1_CLK_SRC 58
#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 59
#define GCC_CAMSS_TFE_1_CSID_CLK 60
#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 61
#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 62
#define GCC_CAMSS_TOP_AHB_CLK 63
#define GCC_CAMSS_TOP_AHB_CLK_SRC 64
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 65
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 66
#define GCC_DDRSS_GPU_AXI_CLK 67
#define GCC_DDRSS_MEMNOC_PCIE_SF_CLK 68
#define GCC_DISP_AHB_CLK 69
#define GCC_DISP_GPLL0_CLK_SRC 70
#define GCC_DISP_GPLL0_DIV_CLK_SRC 71
#define GCC_DISP_HF_AXI_CLK 72
#define GCC_DISP_THROTTLE_CORE_CLK 73
#define GCC_DISP_XO_CLK 74
#define GCC_EMAC0_AHB_CLK 75
#define GCC_EMAC0_AXI_CLK 76
#define GCC_EMAC0_AXI_CLK_SRC 77
#define GCC_EMAC0_AXI_SYS_NOC_CLK 78
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 79
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 80
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 81
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 82
#define GCC_EMAC0_PHY_AUX_CLK 83
#define GCC_EMAC0_PHY_AUX_CLK_SRC 84
#define GCC_EMAC0_PTP_CLK 85
#define GCC_EMAC0_PTP_CLK_SRC 86
#define GCC_EMAC0_RGMII_CLK 87
#define GCC_EMAC0_RGMII_CLK_SRC 88
#define GCC_EMAC1_AHB_CLK 89
#define GCC_EMAC1_AXI_CLK 90
#define GCC_EMAC1_AXI_CLK_SRC 91
#define GCC_EMAC1_AXI_SYS_NOC_CLK 92
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 93
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 94
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 95
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 96
#define GCC_EMAC1_PHY_AUX_CLK 97
#define GCC_EMAC1_PHY_AUX_CLK_SRC 98
#define GCC_EMAC1_PTP_CLK 99
#define GCC_EMAC1_PTP_CLK_SRC 100
#define GCC_EMAC1_RGMII_CLK 101
#define GCC_EMAC1_RGMII_CLK_SRC 102
#define GCC_GP1_CLK 103
#define GCC_GP1_CLK_SRC 104
#define GCC_GP2_CLK 105
#define GCC_GP2_CLK_SRC 106
#define GCC_GP3_CLK 107
#define GCC_GP3_CLK_SRC 108
#define GCC_GPU_CFG_AHB_CLK 109
#define GCC_GPU_GPLL0_CLK_SRC 110
#define GCC_GPU_GPLL0_DIV_CLK_SRC 111
#define GCC_GPU_IREF_CLK 112
#define GCC_GPU_MEMNOC_GFX_CLK 113
#define GCC_GPU_SMMU_VOTE_CLK 114
#define GCC_GPU_SNOC_DVM_GFX_CLK 115
#define GCC_GPU_THROTTLE_CORE_CLK 116
#define GCC_LPASS_CONFIG_CLK 117
#define GCC_LPASS_CORE_AXIM_CLK 118
#define GCC_MMU_TCU_VOTE_CLK 119
#define GCC_PCIE_AUX_CLK 120
#define GCC_PCIE_AUX_CLK_SRC 121
#define GCC_PCIE_AUX_PHY_CLK_SRC 122
#define GCC_PCIE_CFG_AHB_CLK 123
#define GCC_PCIE_CLKREF_EN 124
#define GCC_PCIE_MSTR_AXI_CLK 125
#define GCC_PCIE_PIPE_CLK 126
#define GCC_PCIE_PIPE_CLK_SRC 127
#define GCC_PCIE_RCHNG_PHY_CLK 128
#define GCC_PCIE_RCHNG_PHY_CLK_SRC 129
#define GCC_PCIE_SLEEP_CLK 130
#define GCC_PCIE_SLV_AXI_CLK 131
#define GCC_PCIE_SLV_Q2A_AXI_CLK 132
#define GCC_PCIE_TBU_CLK 133
#define GCC_PCIE_THROTTLE_CORE_CLK 134
#define GCC_PCIE_THROTTLE_XO_CLK 135
#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 136
#define GCC_PDM2_CLK 137
#define GCC_PDM2_CLK_SRC 138
#define GCC_PDM_AHB_CLK 139
#define GCC_PDM_XO4_CLK 140
#define GCC_PWM0_XO512_CLK 141
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 142
#define GCC_QMIP_CAMERA_RT_AHB_CLK 143
#define GCC_QMIP_DISP_AHB_CLK 144
#define GCC_QMIP_GPU_CFG_AHB_CLK 145
#define GCC_QMIP_PCIE_CFG_AHB_CLK 146
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 147
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 148
#define GCC_QUPV3_WRAP0_CORE_CLK 149
#define GCC_QUPV3_WRAP0_S0_CLK 150
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 151
#define GCC_QUPV3_WRAP0_S1_CLK 152
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 153
#define GCC_QUPV3_WRAP0_S2_CLK 154
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 155
#define GCC_QUPV3_WRAP0_S3_CLK 156
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 157
#define GCC_QUPV3_WRAP0_S4_CLK 158
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 159
#define GCC_QUPV3_WRAP0_S5_CLK 160
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 161
#define GCC_QUPV3_WRAP0_S6_CLK 162
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 163
#define GCC_QUPV3_WRAP0_S7_CLK 164
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 165
#define GCC_QUPV3_WRAP0_S8_CLK 166
#define GCC_QUPV3_WRAP0_S8_CLK_SRC 167
#define GCC_QUPV3_WRAP0_S9_CLK 168
#define GCC_QUPV3_WRAP0_S9_CLK_SRC 169
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 170
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 171
#define GCC_SDCC1_AHB_CLK 172
#define GCC_SDCC1_APPS_CLK 173
#define GCC_SDCC1_APPS_CLK_SRC 174
#define GCC_SDCC1_ICE_CORE_CLK 175
#define GCC_SDCC1_ICE_CORE_CLK_SRC 176
#define GCC_SDCC2_AHB_CLK 177
#define GCC_SDCC2_APPS_CLK 178
#define GCC_SDCC2_APPS_CLK_SRC 179
#define GCC_SYS_NOC_CPUSS_AHB_CLK 180
#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 181
#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 182
#define GCC_TSCSS_AHB_CLK 183
#define GCC_TSCSS_CLK_SRC 184
#define GCC_TSCSS_CNTR_CLK 185
#define GCC_TSCSS_ETU_CLK 186
#define GCC_UFS_CLKREF_EN 187
#define GCC_USB20_MASTER_CLK 188
#define GCC_USB20_MASTER_CLK_SRC 189
#define GCC_USB20_MOCK_UTMI_CLK 190
#define GCC_USB20_MOCK_UTMI_CLK_SRC 191
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 192
#define GCC_USB20_SLEEP_CLK 193
#define GCC_USB30_PRIM_MASTER_CLK 194
#define GCC_USB30_PRIM_MASTER_CLK_SRC 195
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 196
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 197
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 198
#define GCC_USB30_PRIM_SLEEP_CLK 199
#define GCC_USB3_PRIM_CLKREF_EN 200
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202
#define GCC_USB3_PRIM_PHY_PIPE_CLK 203
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204
#define GCC_VCODEC0_AXI_CLK 205
#define GCC_VENUS_AHB_CLK 206
#define GCC_VENUS_CTL_AXI_CLK 207
#define GCC_VIDEO_AHB_CLK 208
#define GCC_VIDEO_AXI0_CLK 209
#define GCC_VIDEO_THROTTLE_CORE_CLK 210
#define GCC_VIDEO_VCODEC0_SYS_CLK 211
#define GCC_VIDEO_VENUS_CLK_SRC 212
#define GCC_VIDEO_VENUS_CTL_CLK 213
#define GCC_VIDEO_XO_CLK 214
/* GCC power domains */
#define GCC_CAMSS_TOP_GDSC 0
#define GCC_EMAC0_GDSC 1
#define GCC_EMAC1_GDSC 2
#define GCC_PCIE_GDSC 3
#define GCC_USB20_GDSC 4
#define GCC_USB30_PRIM_GDSC 5
#define GCC_VCODEC0_GDSC 6
#define GCC_VENUS_GDSC 7
/* GCC resets */
#define GCC_CAMSS_OPE_BCR 0
#define GCC_CAMSS_TFE_BCR 1
#define GCC_CAMSS_TOP_BCR 2
#define GCC_EMAC0_BCR 3
#define GCC_EMAC1_BCR 4
#define GCC_GPU_BCR 5
#define GCC_MMSS_BCR 6
#define GCC_PCIE_BCR 7
#define GCC_PCIE_PHY_BCR 8
#define GCC_PDM_BCR 9
#define GCC_QUPV3_WRAPPER_0_BCR 10
#define GCC_QUSB2PHY_PRIM_BCR 11
#define GCC_QUSB2PHY_SEC_BCR 12
#define GCC_SDCC1_BCR 13
#define GCC_SDCC2_BCR 14
#define GCC_TSCSS_BCR 15
#define GCC_USB20_BCR 16
#define GCC_USB30_PRIM_BCR 17
#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 18
#define GCC_USB3_DP_PHY_PRIM_BCR 19
#define GCC_USB3_PHY_PRIM_SP0_BCR 20
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 21
#define GCC_VCODEC0_BCR 22
#define GCC_VENUS_BCR 23
#define GCC_VIDEO_INTERFACE_BCR 24
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __LINUX_CLK_QCOM_H
#define __LINUX_CLK_QCOM_H
#include <linux/clk-provider.h>
#include <linux/errno.h>
#include <linux/kconfig.h>
#include <linux/regmap.h>
#include <linux/types.h>
struct device;
struct platform_device;
struct regulator_bulk_data;
/**
* struct qcom_clk_ref_desc - descriptor for a clkref_en gate clock
* @name: clock name exposed to the common clock framework
* @offset: clkref_en register offset from the block base
* @regulator_names: optional supply names enabled while preparing the clock
* @num_regulators: number of entries in @regulator_names
*/
struct qcom_clk_ref_desc {
const char *name;
u32 offset;
const char * const *regulator_names;
unsigned int num_regulators;
};
/**
* struct qcom_clk_ref - per-clock data for a clkref_en gate clock
* @hw: common clock framework hardware clock handle
* @regmap: register map backing the clkref_en register
* @desc: clock descriptor copied at registration time
* @regulators: optional bulk regulator handles for @desc.regulator_names
*/
struct qcom_clk_ref {
struct clk_hw hw;
struct regmap *regmap;
struct qcom_clk_ref_desc desc;
struct regulator_bulk_data *regulators;
};
#if IS_ENABLED(CONFIG_COMMON_CLK_QCOM)
int qcom_clk_ref_probe(struct platform_device *pdev,
const struct regmap_config *config,
const struct qcom_clk_ref_desc * const *descs,
size_t num_clk_refs);
#else
static inline int
qcom_clk_ref_probe(struct platform_device *pdev,
const struct regmap_config *config,
const struct qcom_clk_ref_desc * const *descs,
size_t num_clk_refs)
{
return -EOPNOTSUPP;
}
#endif
#endif