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More Qualcomm Arm64 DeviceTree updates for v7.3

Browse Source 
Introduce the Asus Zenbook A16 (UX3607OA).
 
 Add IPQ9574 PCIe bridge descriptions and enable PCIe0 and PCIe2 for
 QCN92xx Wi-Fi cards on RDP454. Align IPQ5018, IPQ6018, and IPQ8074 PCIe
 PHY and reset descriptions with the port-node binding.
 
 Extend Shikra platform enablement with CQM and IQS SoM Wi-Fi and Bluetooth
 descriptions. Enable CDSP, LPAICP, and MPSS remote processors on CQM, CQS,
 and IQS EVKs, and add SMP2P, QUPv3, DDR bandwidth monitor, CPU frequency
 hardware, EPSS L3 interconnect, OPP tables, thermal zones, GPIO
 reservations, and display and GPU clock controllers.
 
 Enable Eliza CQS EVK audio and add its LPASS macro and SoundWire
 descriptions. Add PMIC ADC support for Hamoa, Monaco, and Lemans, and
 ADC channel macros for the third-generation ADC block. Add minidump SRAM
 configurations across affected Qualcomm platforms.
 
 Fix QMP PHY vdda-phy and vdda-pll supply assignments across Qualcomm
 platforms. Correct PCIe IOMMU mappings for QCS6490, Lemans, Monaco,
 Talos, SM, SC, and related boards. Fix the Glymur/Mahua PDC interrupt
 mapping, USB HS properties, and wakeup configuration; correct board
 identifiers, pin configuration, GPIO supplies, default bus frequency, and
 DT validation issues.
 
 Enable the X1E80100 deepest idle state, configure SPMI ADC thermal
 monitoring on SM8550 and SM8650, add the Milos GPU clock controller, and
 assign SM8650 CCI clock rates.
 -----BEGIN PGP SIGNATURE-----
 
 iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmp19sgOHGJqb3JuQGty
 eW8uc2UACgkQCx85Pw2ZrcWwUA/8Dxv0BBgDDTw7qjJ1/2ziwM2PzdQfh1JJB03G
 tlVhR+3XP3kXSoRulcPiH5d2KRdne3cOgOGsVY9H8KeonIszduvzicrrAimAiXIP
 H7ZTcAP+glqZNTND3uJv0/DV2Jdr2mW0aOoufChXdMJ4IOia0gU3ij0Z4b1wAFfk
 xlagbBS39RoVltDN7Oa8ASKyWL3DMRY74YDfbER20+iF7bkizQovXM2gfodga00m
 pToy02uU8LQ4+IjshzUsvEMDCMrTFn+1WjwHgdq+mw+dmMVnaR3aryZqBb83K30o
 yWo8baRQNVMVkTezLndWBLI87MpPQyqRQ+ivJuo2OOaE2u3LicglCimTM4uyundQ
 0a7KqtSl5fQhsWYgwaLdENr0+T84GbFU8IEu4G270ISojvmm4qIbXy/ZNlkXoYvI
 UZxV7/oqVuXE/7llHi7f0q6SK5rMFparmHelAMmraBCVD7UDpHvYS0gJbMsgMOCE
 Za3X3U7Khsz9br6dDViqWqyb9wl3bdEweu+MWG8HyhiTQAv47i+F2RNjVacJN2Nh
 yopplAHfY02T+GZ8gZaW2OPcinfbUOt1sl/TYBkab21r5BF+xreMXcJQaGGQ+Phf
 G1mxUg9AfPY8ejYmhH/YF+U6Co2Iarf6yhWk1kUhPq05S3ZlAvxINN1QgTit6U8J
 1pOevak=
 =tU3C
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5+oIACgkQmmx57+YA
 GNl3pA//dOef6GQAAJtE80UZ2AAPMzMbZRspnlYsMx/9+2bZfROUrOydovqPbHWh
 baKLTqZjuWjQbxhAhZunwBLaO0L5nWzjYwvJyKk9MgQxSR+rcJv7BoCqkhZKFH0P
 UW1W+T2xb9iOUfPuXcSUF7AEHB58QUZqJo2of1cRzbywK6CVColJiZNl08QrM0E5
 8BVOeP7sLIqY/oi6y0T+h98n3311xfszcPsHnzY7YI6IApPUa0rVu/Od16u+7avY
 YT8RKPGnVzheLzGNkSSMLMGzxd068eDBF9I4klrIIKXpeRHrZg7dyzLc577Fzfae
 3I9GgcjRMddJXGNfDTT+AcrQdhZdFdaOl3ibgXEQaZvAye/cQdBCKAnUDfGkvrC/
 +h5h4Yf+LQtu1u9TIsk491L9QE26Pv8UiyrbOiz+eoEX9COHGqZIRIAKEtnRyx37
 J915hOwqCK+e8RLyBlWm3suDNFXXQBT6OkaJr6aAPHq55N93irWRA4sFb13nfl+G
 fFRYjEL5jUGhvBBd8ZGFTCaFU6nINa+6pCEJXMgxI3s4QvtZJqI6Q24DaK7T5tbk
 DSozFDx3xbr9EdMEXSJdg9OEKd5Rii/v0sPZnLOHa6QgKVixBJAMgIHtTFiIojmB
 N5tfjr+NZvhW6Y7vRsDbqUmz09NNHrc7IkazH4HFjKXXsegvCqw=
 =AIdP
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm64-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

More Qualcomm Arm64 DeviceTree updates for v7.3

Introduce the Asus Zenbook A16 (UX3607OA).

Add IPQ9574 PCIe bridge descriptions and enable PCIe0 and PCIe2 for
QCN92xx Wi-Fi cards on RDP454. Align IPQ5018, IPQ6018, and IPQ8074 PCIe
PHY and reset descriptions with the port-node binding.

Extend Shikra platform enablement with CQM and IQS SoM Wi-Fi and Bluetooth
descriptions. Enable CDSP, LPAICP, and MPSS remote processors on CQM, CQS,
and IQS EVKs, and add SMP2P, QUPv3, DDR bandwidth monitor, CPU frequency
hardware, EPSS L3 interconnect, OPP tables, thermal zones, GPIO
reservations, and display and GPU clock controllers.

Enable Eliza CQS EVK audio and add its LPASS macro and SoundWire
descriptions. Add PMIC ADC support for Hamoa, Monaco, and Lemans, and
ADC channel macros for the third-generation ADC block. Add minidump SRAM
configurations across affected Qualcomm platforms.

Fix QMP PHY vdda-phy and vdda-pll supply assignments across Qualcomm
platforms. Correct PCIe IOMMU mappings for QCS6490, Lemans, Monaco,
Talos, SM, SC, and related boards. Fix the Glymur/Mahua PDC interrupt
mapping, USB HS properties, and wakeup configuration; correct board
identifiers, pin configuration, GPIO supplies, default bus frequency, and
DT validation issues.

Enable the X1E80100 deepest idle state, configure SPMI ADC thermal
monitoring on SM8550 and SM8650, add the Milos GPU clock controller, and
assign SM8650 CCI clock rates.

* tag 'qcom-arm64-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (117 commits)
  arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sc7280: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sc7180: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm7225-fairphone-fp4: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: qcs6490: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: qcm6490: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: qcs8550-aim300: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm8550: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm8450: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-08-10 18:19:15 +02:00
commit aeba6e4f8a
156 changed files with 5922 additions and 638 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -86,6 +86,7 @@ properties:
- items:
- enum:
- asus,zenbook-a16-ux3607oa
- qcom,glymur-crd
- const: qcom,glymur
@ -1137,6 +1138,13 @@ properties:
- sony,pdx234
- const: qcom,sm8550
- items:
- enum:
- imdt,qcs8550-sbc
- const: imdt,qcs8550-som
- const: qcom,qcs8550
- const: qcom,sm8550
- items:
- enum:
- qcom,qcs8550-aim300-aiot

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -797,6 +797,8 @@ patternProperties:
description: ILI Technology Corporation (ILITEK)
"^imagis,.*":
description: Imagis Technologies Co., Ltd.
"^imdt,.*":
description: IMD Technologies Ltd.
"^img,.*":
description: Imagination Technologies Ltd.
"^imi,.*":

1
arch/arm64/boot/dts/qcom/Makefile
View File

@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a16-ux3607oa.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb

1
arch/arm64/boot/dts/qcom/agatti.dtsi
View File

@ -2197,6 +2197,7 @@ dispcc: clock-controller@5f00000 {
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk";
power-domains = <&rpmpd QCM2290_VDDCX>;
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;

141
arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts
View File

@ -5,10 +5,151 @@
/dts-v1/;
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "eliza-cqs-som.dtsi"
#include "eliza-evk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Eliza CQS EVK";
compatible = "qcom,eliza-cqs-evk", "qcom,eliza-cqs-som", "qcom,eliza";
sound {
compatible = "qcom,eliza-sndcard", "qcom,sm8450-sndcard";
model = "eliza-cqs-evk";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"VA DMIC2", "vdd-micb",
"VA DMIC3", "vdd-micb",
"VA DMIC4", "vdd-micb",
"VA DMIC5", "vdd-micb",
"VA DMIC6", "vdd-micb",
"VA DMIC7", "vdd-micb";
va-dai-link {
link-name = "VA Capture";
codec {
sound-dai = <&lpass_vamacro 0>;
};
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wsa-dai-link {
link-name = "WSA Playback";
codec {
sound-dai = <&left_spkr>, <&right_spkr>,
<&swr0 0>, <&lpass_wsamacro 0>;
};
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
dmic_eldo: regulator-dmic-eldo {
compatible = "regulator-fixed";
regulator-name = "dmic-eldo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&pm7550_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vreg_bob>;
};
};
&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>,
<&dmic45_default>, <&dmic67_default>;
pinctrl-names = "default";
vdd-micb-supply = <&dmic_eldo>;
qcom,dmic-sample-rate = <4800000>;
};
&swr0 {
pinctrl-0 = <&wsa_swr_active>;
pinctrl-names = "default";
status = "okay";
/* WSA8845, Speaker Left */
left_spkr: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
vdd-1p8-supply = <&vreg_l7b>;
vdd-io-supply = <&vreg_l7b>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
/*
* WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
* WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
* WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
* WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
* WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
* WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
*/
qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Speaker Right */
right_spkr: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
pinctrl-0 = <&spkr_2_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
vdd-1p8-supply = <&vreg_l7b>;
vdd-io-supply = <&vreg_l7b>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
/*
* WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
* WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
* WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
* WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
* WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
* WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
*/
qcom,port-mapping = <4 5 6 7 11 13>;
};
};
&tlmm {
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio59";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
spkr_2_sd_n_active: spkr-2-sd-n-active-state {
pins = "gpio79";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};

5
arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi
View File

@ -369,6 +369,11 @@ vreg_l7k: ldo7 {
};
};
&pm7550ba_eusb2_repeater {
vdd18-supply = <&vreg_l7b>;
vdd3-supply = <&vreg_l17b>;
};
&remoteproc_adsp {
firmware-name = "qcom/eliza/adsp.mbn",
"qcom/eliza/adsp_dtb.mbn";

4
arch/arm64/boot/dts/qcom/eliza-mtp.dts
View File

@ -579,8 +579,8 @@ &usb {
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3g>;
vdda-pll-supply = <&vreg_l7k>;
vdda-phy-supply = <&vreg_l7k>;
vdda-pll-supply = <&vreg_l3g>;
status = "okay";
};

189
arch/arm64/boot/dts/qcom/eliza.dtsi
View File

@ -19,6 +19,7 @@
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
@ -2064,6 +2065,77 @@ q6prmcc: clock-controller {
};
};
lpass_wsamacro: codec@6b00000 {
compatible = "qcom,eliza-lpass-wsa-macro",
"qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06b00000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr0: soundwire@6b10000 {
compatible = "qcom,soundwire-v2.1.0",
"qcom,soundwire-v2.0.0";
reg = <0x0 0x06b10000 0x0 0x10000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsamacro>;
clock-names = "iface";
label = "WSA";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval =
/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f
0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 =
/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15
0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 =
/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f
0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart =
/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop =
/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length =
/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
qcom,ports-block-pack-mode =
/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01
0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count =
/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control =
/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,eliza-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
@ -2078,6 +2150,123 @@ lpass_lpicx_noc: interconnect@7420000 {
#interconnect-cells = <2>;
};
lpass_vamacro: codec@7660000 {
compatible = "qcom,eliza-lpass-va-macro",
"qcom,sm8550-lpass-va-macro";
reg = <0x0 0x07660000 0x0 0x2000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk",
"macro",
"dcodec";
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
};
lpass_tlmm: pinctrl@7760000 {
compatible = "qcom,eliza-lpass-lpi-pinctrl";
reg = <0x0 0x07760000 0x0 0x20000>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
dmic01_default: dmic01-default-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
dmic45_default: dmic45-default-state {
clk-pins {
pins = "gpio12";
function = "dmic3_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio13";
function = "dmic3_data";
drive-strength = <8>;
input-enable;
};
};
dmic67_default: dmic67-default-state {
clk-pins {
pins = "gpio21";
function = "dmic4_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio22";
function = "dmic4_data";
drive-strength = <8>;
input-enable;
};
};
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
};
sdhc_2: mmc@8804000 {
compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x08804000 0x0 0x1000>;

1269
arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts Normal file
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File diff suppressed because it is too large Load Diff

25
arch/arm64/boot/dts/qcom/glymur-crd.dtsi
View File

@ -679,14 +679,13 @@ &i2c8 {
status = "okay";
touchscreen@38 {
compatible = "hid-over-i2c";
compatible = "focaltech,ft3d81", "focaltech,ft8112";
reg = <0x38>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
vcc33-supply = <&vreg_misc_3p3>;
vccio-supply = <&vreg_l15b_e0_1p8>;
reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
@ -1168,8 +1167,8 @@ &usb_0_hsphy {
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l3f_e0_0p72>;
vdda-phy-supply = <&vreg_l3f_e0_0p72>;
vdda-pll-supply = <&vreg_l4h_e0_1p2>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
@ -1197,8 +1196,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l1h_e0_0p89>;
vdda-phy-supply = <&vreg_l1h_e0_0p89>;
vdda-pll-supply = <&vreg_l4h_e0_1p2>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
@ -1209,6 +1208,8 @@ &usb_1_qmpphy_out {
};
&usb_hs {
dr_mode = "host";
status = "okay";
};
@ -1242,16 +1243,16 @@ &usb_mp_hsphy1 {
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
vdda-phy-supply = <&vreg_l2h_e0_0p72>;
vdda-pll-supply = <&vreg_l4h_e0_1p2>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
vdda-phy-supply = <&vreg_l2h_e0_0p72>;
vdda-pll-supply = <&vreg_l4h_e0_1p2>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";

28
arch/arm64/boot/dts/qcom/glymur.dtsi
View File

@ -2827,7 +2827,7 @@ pcie_west_slv_noc: interconnect@1920000 {
#interconnect-cells = <2>;
};
pcie4: pci@1bf0000 {
pcie4: pcie@1bf0000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01bf0000 0x0 0x3000>,
@ -3043,7 +3043,7 @@ pcie4_phy: phy@1bf6000 {
status = "disabled";
};
pcie5: pci@1b40000 {
pcie5: pcie@1b40000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01b40000 0x0 0x3000>,
@ -3315,7 +3315,7 @@ pcie5_phy: phy@1b50000 {
status = "disabled";
};
pcie6: pci@1c00000 {
pcie6: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01c00000 0x0 0x3000>,
@ -3531,7 +3531,7 @@ pcie6_phy: phy@1c06000 {
status = "disabled";
};
pcie3b: pci@1b80000 {
pcie3b: pcie@1b80000 {
device_type = "pci";
compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
reg = <0x0 0x01b80000 0x0 0x3000>,
@ -4603,6 +4603,7 @@ usb_0: usb@a600000 {
snps,dis_enblslpm_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
@ -4678,6 +4679,7 @@ usb_1: usb@a800000 {
snps,dis_enblslpm_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
@ -4753,6 +4755,7 @@ usb_2: usb@a000000 {
snps,dis_enblslpm_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
@ -4838,10 +4841,12 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
dr_mode = "host";
maximum-speed = "high-speed";
qcom,select-utmi-as-pipe-clk;
usb-role-switch;
wakeup-source;
status = "disabled";
};
@ -4912,6 +4917,7 @@ usb_mp: usb@a400000 {
snps,dis_enblslpm_quirk;
dr_mode = "host";
wakeup-source;
status = "disabled";
};
@ -5422,9 +5428,13 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,glymur-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>;
qcom,pdc-ranges = <0 745 51>,
<51 527 47>,
<98 609 32>,
qcom,pdc-ranges = <0 745 38>,
<40 785 11>,
<51 527 4>,
<57 533 10>,
<70 546 4>,
<75 551 18>,
<108 619 22>,
<130 717 12>,
<142 251 5>,
<147 796 16>,

20
arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
View File

@ -590,8 +590,8 @@ &usb_1_ss0_hsphy {
};
&usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l1j_0p8>;
vdda-phy-supply = <&vreg_l1j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
@ -611,8 +611,8 @@ &usb_1_ss1_hsphy {
};
&usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
vdda-phy-supply = <&vreg_l2d_0p9>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
@ -632,8 +632,8 @@ &usb_1_ss2_hsphy {
};
&usb_1_ss2_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
vdda-phy-supply = <&vreg_l2d_0p9>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
@ -670,15 +670,15 @@ &usb_mp_hsphy1 {
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3c_0p8>;
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3c_0p8>;
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};

20
arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts
View File

@ -1101,8 +1101,8 @@ &usb_1_ss0_hsphy {
};
&usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l2j>;
vdda-pll-supply = <&vreg_l1j>;
vdda-phy-supply = <&vreg_l1j>;
vdda-pll-supply = <&vreg_l2j>;
status = "okay";
};
@ -1112,8 +1112,8 @@ &usb_1_ss0_qmpphy_out {
};
&usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l2j>;
vdda-pll-supply = <&vreg_l2d>;
vdda-phy-supply = <&vreg_l2d>;
vdda-pll-supply = <&vreg_l2j>;
/delete-property/ mode-switch;
/delete-property/ orientation-switch;
@ -1138,8 +1138,8 @@ usb_1_ss1_qmpphy_out_dp: endpoint@0 {
};
&usb_1_ss2_qmpphy {
vdda-phy-supply = <&vreg_l2j>;
vdda-pll-supply = <&vreg_l2d>;
vdda-phy-supply = <&vreg_l2d>;
vdda-pll-supply = <&vreg_l2j>;
/delete-property/ mode-switch;
/delete-property/ orientation-switch;
@ -1186,15 +1186,15 @@ &usb_mp_hsphy1 {
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3e>;
vdda-pll-supply = <&vreg_l3c>;
vdda-phy-supply = <&vreg_l3c>;
vdda-pll-supply = <&vreg_l3e>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3e>;
vdda-pll-supply = <&vreg_l3c>;
vdda-phy-supply = <&vreg_l3c>;
vdda-pll-supply = <&vreg_l3e>;
status = "okay";
};

158
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
View File

@ -6,7 +6,9 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/spmi/spmi.h>
#include "qcom-adc5-gen3.h"
/ {
thermal-zones {
@ -277,6 +279,134 @@ pmk8550_pwm: pwm {
status = "disabled";
};
pmk8550_vadc: adc@9000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x9000>, <0x9100>;
interrupts-extended = <&spmi_bus0 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
<&spmi_bus0 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>;
pinctrl-names = "default";
channel@3 {
reg = <ADC5_GEN3_DIE_TEMP(0)>;
label = "pmk8550_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@103 {
reg = <ADC5_GEN3_DIE_TEMP(1)>;
label = "pm8550_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@144 {
reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
label = "pm8550_therm_2";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@145 {
reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
label = "pm8550_therm_3";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@146 {
reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
label = "pm8550_therm_4";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@147 {
reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
label = "pm8550_therm_5";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@148 {
reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
label = "pm8550_therm_6";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@14a {
reg = <ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>;
label = "pm8550_gpio_01";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@14b {
reg = <ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>;
label = "pm8550_gpio_02";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
channel@18e {
reg = <ADC5_GEN3_VPH_PWR(1)>;
label = "pm8550_vph_pwr";
qcom,pre-scaling = <1 3>;
};
channel@203 {
reg = <ADC5_GEN3_DIE_TEMP(2)>;
label = "pm8550ve_2_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@303 {
reg = <ADC5_GEN3_DIE_TEMP(3)>;
label = "pmc8380_3_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@403 {
reg = <ADC5_GEN3_DIE_TEMP(4)>;
label = "pmc8380_4_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@503 {
reg = <ADC5_GEN3_DIE_TEMP(5)>;
label = "pmc8380_5_die_temp";
qcom,pre-scaling = <1 1>;
};
pmc8380_6_die_temp: channel@603 {
reg = <ADC5_GEN3_DIE_TEMP(6)>;
label = "pmc8380_6_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@803 {
reg = <ADC5_GEN3_DIE_TEMP(8)>;
label = "pm8550ve_8_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@903 {
reg = <ADC5_GEN3_DIE_TEMP(9)>;
label = "pm8550ve_9_die_temp";
qcom,pre-scaling = <1 1>;
};
};
};
/* PMC8380C */
@ -291,6 +421,8 @@ pm8550_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
io-channel-names = "thermal";
};
pm8550_gpios: gpio@8800 {
@ -301,6 +433,18 @@ pm8550_gpios: gpio@8800 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
sys_therm_0_gpio3: sys-therm-0-gpio3-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
bias-high-impedance;
};
sys_therm_1_gpio4: sys-therm-1-gpio4-state {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
bias-high-impedance;
};
};
pm8550_flash: led-controller@ee00 {
@ -329,6 +473,8 @@ pm8550ve_2_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
io-channel-names = "thermal";
};
pm8550ve_2_gpios: gpio@8800 {
@ -354,6 +500,8 @@ pmc8380_3_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
io-channel-names = "thermal";
};
pmc8380_3_gpios: gpio@8800 {
@ -378,6 +526,8 @@ pmc8380_4_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
io-channel-names = "thermal";
};
pmc8380_4_gpios: gpio@8800 {
@ -402,6 +552,8 @@ pmc8380_5_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(5)>;
io-channel-names = "thermal";
};
pmc8380_5_gpios: gpio@8800 {
@ -426,6 +578,8 @@ pmc8380_6_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
io-channel-names = "thermal";
};
pmc8380_6_gpios: gpio@8800 {
@ -451,6 +605,8 @@ pm8550ve_8_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(8)>;
io-channel-names = "thermal";
};
pm8550ve_8_gpios: gpio@8800 {
@ -476,6 +632,8 @@ pm8550ve_9_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(9)>;
io-channel-names = "thermal";
};
pm8550ve_9_gpios: gpio@8800 {

20
arch/arm64/boot/dts/qcom/hamoa.dtsi
View File

@ -300,10 +300,18 @@ cluster_cl4: cluster-sleep-0 {
cluster_cl5: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2200>;
exit-latency-us = <4000>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <7000>;
};
domain_ss3: domain-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x0200c354>;
entry-latency-us = <2500>;
exit-latency-us = <2500>;
min-residency-us = <9000>;
};
};
};
@ -462,7 +470,7 @@ cluster_pd2: power-domain-cpu-cluster2 {
system_pd: power-domain-system {
#power-domain-cells = <0>;
/* TODO: system-wide idle states */
domain-idle-states = <&domain_ss3>;
};
};
@ -3404,7 +3412,7 @@ pcie3_phy: phy@1be0000 {
status = "disabled";
};
pcie6a: pci@1bf8000 {
pcie6a: pcie@1bf8000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0 0x01bf8000 0 0x3000>,
@ -3547,7 +3555,7 @@ pcie6a_phy: phy@1bfc000 {
status = "disabled";
};
pcie5: pci@1c00000 {
pcie5: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0 0x01c00000 0 0x3000>,
@ -3684,7 +3692,7 @@ pcie5_phy: phy@1c06000 {
status = "disabled";
};
pcie4: pci@1c08000 {
pcie4: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0 0x01c08000 0 0x3000>,

8
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
View File

@ -34,9 +34,6 @@ &pcie0 {
pinctrl-0 = <&pcie0_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -44,6 +41,11 @@ &pcie0_phy {
status = "okay";
};
&pcie0_port0 {
reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";

12
arch/arm64/boot/dts/qcom/ipq5018.dtsi
View File

@ -758,9 +758,6 @@ pcie1: pcie@80000000 {
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
max-link-speed = <2>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
<0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
@ -829,6 +826,8 @@ pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -859,9 +858,6 @@ pcie0: pcie@a0000000 {
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
max-link-speed = <2>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
@ -925,11 +921,13 @@ pcie0: pcie@a0000000 {
status = "disabled";
pcie@0 {
pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;

5
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -889,9 +889,6 @@ pcie0: pcie@20000000 {
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_phy>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
<0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
@ -956,6 +953,8 @@ pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;

10
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View File

@ -54,12 +54,18 @@ &blsp1_uart5 {
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie0_port0 {
reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie1_port0 {
reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_qmp0 {

10
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
View File

@ -40,12 +40,18 @@ &blsp1_uart5 {
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie0_port0 {
reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie1_port0 {
reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie_qmp0 {

14
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -841,9 +841,6 @@ pcie1: pcie@10000000 {
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_qmp1>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
@ -902,11 +899,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"axi_m_sticky";
status = "disabled";
pcie@0 {
pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie_qmp1>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -929,9 +928,6 @@ pcie0: pcie@20000000 {
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_qmp0>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
@ -993,11 +989,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"axi_s_sticky";
status = "disabled";
pcie@0 {
pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie_qmp0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;

39
arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi
View File

@ -6,16 +6,26 @@
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&pcie1_phy {
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pcie1_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
};
&pcie2 {
pinctrl-0 = <&pcie2_default>;
pinctrl-names = "default";
status = "okay";
};
@ -23,12 +33,15 @@ &pcie2_phy {
status = "okay";
};
&pcie2 {
pinctrl-0 = <&pcie2_default>;
&pcie2_port0 {
reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -36,13 +49,9 @@ &pcie3_phy {
status = "okay";
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
&pcie3_port0 {
reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
status = "okay";
};
&tlmm {

80
arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
View File

@ -18,3 +18,83 @@ / {
&qpic_nand {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pcie0_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie0_phy {
status = "okay";
};
&pcie0_port0 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
};
&pcie2 {
pinctrl-0 = <&pcie2_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie2_phy {
status = "okay";
};
&pcie2_port0 {
reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};
&tlmm {
pcie0_default: pcie0-default-state {
clkreq-n-pins {
pins = "gpio22";
function = "pcie0_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio23";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
wake-n-pins {
pins = "gpio24";
function = "pcie0_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie2_default: pcie2-default-state {
clkreq-n-pins {
pins = "gpio28";
function = "pcie2_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
wake-n-pins {
pins = "gpio30";
function = "pcie2_wake";
drive-strength = <6>;
bias-pull-up;
};
};
};

56
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -1004,12 +1004,22 @@ pcie1: pcie@10000000 {
"aux",
"ahb";
phys = <&pcie1_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie3: pcie@18000000 {
@ -1092,12 +1102,22 @@ pcie3: pcie@18000000 {
"aux",
"ahb";
phys = <&pcie3_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
<&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie3_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie3_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie2: pcie@20000000 {
@ -1180,12 +1200,22 @@ pcie2: pcie@20000000 {
"aux",
"ahb";
phys = <&pcie2_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
<&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie2_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0: pcie@28000000 {
@ -1267,12 +1297,22 @@ pcie0: pcie@28000000 {
"aux",
"ahb";
phys = <&pcie0_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
<&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
nsscc: clock-controller@39b00000 {

4
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
View File

@ -1389,8 +1389,8 @@ &usb_hsphy {
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l1d_1p2>;
vdda-pll-supply = <&vreg_l4f_0p8>;
vdda-phy-supply = <&vreg_l4f_0p8>;
vdda-pll-supply = <&vreg_l1d_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
View File

@ -884,8 +884,8 @@ &usb_hsphy {
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l1d_1p2>;
vdda-pll-supply = <&vreg_l4f_0p8>;
vdda-phy-supply = <&vreg_l4f_0p8>;
vdda-pll-supply = <&vreg_l1d_1p2>;
status = "okay";
};

9
arch/arm64/boot/dts/qcom/kaanapali.dtsi
View File

@ -224,6 +224,7 @@ scm: scm {
qcom,dload-mode = <&tcsr 0x19000>;
interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
sram = <&minidump_config>;
};
scmi: scmi {
@ -2385,8 +2386,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
operating-points-v2 = <&pcie0_opp_table>;
iommu-map = <0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
iommu-map = <0 &apps_smmu 0x1400 0x0 0x1>,
<0x100 &apps_smmu 0x1401 0x0 0x1>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
@ -5586,6 +5587,10 @@ sram@14680000 {
#address-cells = <1>;
#size-cells = <1>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
pil-sram@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;

13
arch/arm64/boot/dts/qcom/kodiak.dtsi
View File

@ -723,6 +723,7 @@ firmware {
scm: scm {
compatible = "qcom,scm-sc7280", "qcom,scm";
qcom,dload-mode = <&tcsr_2 0x13000>;
sram = <&minidump_config>;
};
};
@ -2281,8 +2282,8 @@ pcie0: pcie@1c00000 {
"aggre0",
"aggre1";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
@ -2423,8 +2424,8 @@ pcie1: pcie@1c08000 {
dma-coherent;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>;
status = "disabled";
@ -6714,6 +6715,10 @@ sram@146a5000 {
ranges = <0 0 0x146a5000 0x6000>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
ipa_modem_tables: modem-tables@3000 {
reg = <0x3000 0x2000>;
};

22
arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
View File

@ -204,15 +204,15 @@ &mdss1_dp1_phy {
};
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
<0x208 &pcie_smmu 0x2 0x1>,
<0x210 &pcie_smmu 0x3 0x1>,
<0x218 &pcie_smmu 0x4 0x1>,
<0x300 &pcie_smmu 0x5 0x1>,
<0x400 &pcie_smmu 0x6 0x1>,
<0x500 &pcie_smmu 0x7 0x1>,
<0x501 &pcie_smmu 0x8 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x0 0x1>,
<0x208 &pcie_smmu 0x2 0x0 0x1>,
<0x210 &pcie_smmu 0x3 0x0 0x1>,
<0x218 &pcie_smmu 0x4 0x0 0x1>,
<0x300 &pcie_smmu 0x5 0x0 0x1>,
<0x400 &pcie_smmu 0x6 0x0 0x1>,
<0x500 &pcie_smmu 0x7 0x0 0x1>,
<0x501 &pcie_smmu 0x8 0x0 0x1>;
};
&pcieport0 {
@ -271,7 +271,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -279,7 +279,7 @@ pci@0,0 {
ranges;
};
pci@0,1 {
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

4
arch/arm64/boot/dts/qcom/lemans-evk.dts
View File

@ -1170,8 +1170,8 @@ &usb_0_hsphy {
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
vdda-phy-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};

93
arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
#include "qcom-adc5-gen3.h"
/ {
thermal-zones {
@ -110,6 +111,8 @@ pmm8654au_0_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>;
io-channel-names = "thermal";
};
pmm8654au_0_pon: pon@1200 {
@ -141,6 +144,27 @@ pmm8654au_0_rtc: rtc@6100 {
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
pmm8654au_0_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@3 {
reg = <ADC5_GEN3_DIE_TEMP(0)>;
label = "pmm8654au_0_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@8e {
reg = <ADC5_GEN3_VPH_PWR(0)>;
label = "pmm8654au_0_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};
pmm8654au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@ -176,6 +200,29 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>;
io-channel-names = "thermal";
};
pmm8654au_1_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@203 {
reg = <ADC5_GEN3_DIE_TEMP(2)>;
label = "pmm8654au_1_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@28e {
reg = <ADC5_GEN3_VPH_PWR(2)>;
label = "pmm8654au_1_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};
pmm8654au_1_gpios: gpio@8800 {
@ -200,6 +247,29 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>;
io-channel-names = "thermal";
};
pmm8654au_2_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
interrupts-extended = <&spmi_bus 0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@403 {
reg = <ADC5_GEN3_DIE_TEMP(4)>;
label = "pmm8654au_2_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@48e {
reg = <ADC5_GEN3_VPH_PWR(4)>;
label = "pmm8654au_2_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};
pmm8654au_2_gpios: gpio@8800 {
@ -224,6 +294,29 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>;
io-channel-names = "thermal";
};
pmm8654au_3_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
interrupts-extended = <&spmi_bus 0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@603 {
reg = <ADC5_GEN3_DIE_TEMP(6)>;
label = "pmm8654au_3_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@68e {
reg = <ADC5_GEN3_VPH_PWR(6)>;
label = "pmm8654au_3_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};
pmm8654au_3_gpios: gpio@8800 {

8
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
View File

@ -1103,8 +1103,8 @@ &usb_0_hsphy {
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
vdda-phy-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
@ -1126,8 +1126,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
vdda-phy-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};

13
arch/arm64/boot/dts/qcom/lemans.dtsi
View File

@ -514,6 +514,7 @@ firmware {
scm {
compatible = "qcom,scm-sa8775p", "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
sram = <&minidump_config>;
};
};
@ -2742,8 +2743,8 @@ pcie0: pcie@1c00000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>,
<0x100 &pcie_smmu 0x0001 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
@ -2916,8 +2917,8 @@ pcie1: pcie@1c10000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
<0x100 &pcie_smmu 0x0081 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>,
<0x100 &pcie_smmu 0x0081 0x0 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
@ -6821,6 +6822,10 @@ sram: sram@146d8000 {
#address-cells = <1>;
#size-cells = <1>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;

10
arch/arm64/boot/dts/qcom/milos.dtsi
View File

@ -1591,6 +1591,16 @@ lpass_ag_noc: interconnect@3c40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
gxclkctl: clock-controller@3d64000 {
compatible = "qcom,milos-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
power-domains = <&rpmhpd RPMHPD_GFX>,
<&gpucc GPU_CC_CX_GDSC>;
#power-domain-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,milos-gpucc";
reg = <0x0 0x03d90000 0x0 0x9800>;

4
arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
View File

@ -421,7 +421,7 @@ &pcie1 {
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pci@0,0 {
pcie@0,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -429,7 +429,7 @@ pci@0,0 {
ranges;
reg = <0x010000 0x00 0x00 0x00 0x00>;
pci@2,0 {
pcie@2,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";

22
arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso
View File

@ -50,15 +50,15 @@ nvmem-layout {
};
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
<0x208 &pcie_smmu 0x2 0x1>,
<0x210 &pcie_smmu 0x3 0x1>,
<0x218 &pcie_smmu 0x4 0x1>,
<0x300 &pcie_smmu 0x5 0x1>,
<0x400 &pcie_smmu 0x6 0x1>,
<0x500 &pcie_smmu 0x7 0x1>,
<0x501 &pcie_smmu 0x8 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x0 0x1>,
<0x208 &pcie_smmu 0x2 0x0 0x1>,
<0x210 &pcie_smmu 0x3 0x0 0x1>,
<0x218 &pcie_smmu 0x4 0x0 0x1>,
<0x300 &pcie_smmu 0x5 0x0 0x1>,
<0x400 &pcie_smmu 0x6 0x0 0x1>,
<0x500 &pcie_smmu 0x7 0x0 0x1>,
<0x501 &pcie_smmu 0x8 0x0 0x1>;
};
&pcieport0 {
@ -117,7 +117,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -125,7 +125,7 @@ pci@0,0 {
ranges;
};
pci@0,1 {
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

16
arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
View File

@ -196,14 +196,14 @@ &iris {
/* PCIe0 Gen4 x2 */
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>,
<0x200 &pcie_smmu 0x0007 0x1>,
<0x208 &pcie_smmu 0x0002 0x1>,
<0x210 &pcie_smmu 0x0003 0x1>,
<0x218 &pcie_smmu 0x0004 0x1>,
<0x300 &pcie_smmu 0x0005 0x1>,
<0x400 &pcie_smmu 0x0006 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>,
<0x100 &pcie_smmu 0x0001 0x0 0x1>,
<0x200 &pcie_smmu 0x0007 0x0 0x1>,
<0x208 &pcie_smmu 0x0002 0x0 0x1>,
<0x210 &pcie_smmu 0x0003 0x0 0x1>,
<0x218 &pcie_smmu 0x0004 0x0 0x1>,
<0x300 &pcie_smmu 0x0005 0x0 0x1>,
<0x400 &pcie_smmu 0x0006 0x0 0x1>;
status = "okay";
};

43
arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
#include "qcom-adc5-gen3.h"
&spmi_bus {
pmm8620au_0: pmic@0 {
@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 {
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
pmm8620au_0_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@3 {
reg = <ADC5_GEN3_DIE_TEMP(0)>;
label = "pmm8620au_0_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@8e {
reg = <ADC5_GEN3_VPH_PWR(0)>;
label = "pmm8620au_0_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};
pmm8620au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@ -37,6 +59,27 @@ pmm8650au_1: pmic@2 {
#address-cells = <1>;
#size-cells = <0>;
pmm8650au_1_adc: adc@8000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x8000>;
interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@203 {
reg = <ADC5_GEN3_DIE_TEMP(2)>;
label = "pmm8650au_1_die_temp";
qcom,pre-scaling = <1 1>;
};
channel@28e {
reg = <ADC5_GEN3_VPH_PWR(2)>;
label = "pmm8650au_1_vph_pwr";
qcom,pre-scaling = <1 3>;
};
};
pmm8650au_1_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;

29
arch/arm64/boot/dts/qcom/monaco.dtsi
View File

@ -614,6 +614,7 @@ firmware {
scm: scm {
compatible = "qcom,scm-qcs8300", "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
sram = <&minidump_config>;
};
};
@ -2256,7 +2257,7 @@ mmss_noc: interconnect@17a0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie0: pci@1c00000 {
pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
@ -2329,8 +2330,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "pcie-mem",
"cpu-pcie";
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>,
<0x100 &pcie_smmu 0x0001 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
@ -2435,7 +2436,7 @@ pcie0_phy: phy@1c04000 {
status = "disabled";
};
pcie1: pci@1c10000 {
pcie1: pcie@1c10000 {
device_type = "pci";
compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
reg = <0x0 0x01c10000 0x0 0x3000>,
@ -2506,8 +2507,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
&config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
<0x100 &pcie_smmu 0x0081 0x1>;
iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>,
<0x100 &pcie_smmu 0x0081 0x0 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
@ -5475,14 +5476,14 @@ cci0: cci@ac13000 {
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
@ -5512,14 +5513,14 @@ cci1: cci@ac14000 {
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci1_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
@ -5549,14 +5550,14 @@ cci2: cci@ac15000 {
cci2_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci2_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
@ -7163,6 +7164,10 @@ sram: sram@146d8000 {
#address-cells = <1>;
#size-cells = <1>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;

4
arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts
View File

@ -455,14 +455,14 @@ sdc2_cd_sleep: sdc2-cd-sleep-state {
bias-disable;
};
ts_int_default: ts-int-state {
ts_int_default: ts-int-default-state {
pins = "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
ts_int_sleep: ts-int-state {
ts_int_sleep: ts-int-sleep-state {
pins = "gpio65";
function = "gpio";
drive-strength = <2>;

4
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
View File

@ -229,10 +229,6 @@ rmi4-f11@11 {
};
};
&blsp1_i2c5_sleep {
bias-disable;
};
&blsp1_uart3 {
status = "okay";

5
arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
View File

@ -217,11 +217,6 @@ rmi4-f1a@1a {
};
};
&blsp1_i2c5_sleep {
/delete-property/ bias-pull-up;
bias-disable;
};
&blsp1_uart3 {
status = "okay";

24
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -1183,7 +1183,7 @@ blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp1_i2c2_default: blsp1-i2c2-default-state {
@ -1197,7 +1197,7 @@ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp1_i2c3_default: blsp1-i2c3-default-state {
@ -1211,7 +1211,7 @@ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp1_i2c4_default: blsp1-i2c4-default-state {
@ -1225,7 +1225,7 @@ blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp1_i2c5_default: blsp1-i2c5-default-state {
@ -1239,7 +1239,7 @@ blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp1_i2c6_default: blsp1-i2c6-default-state {
@ -1253,7 +1253,7 @@ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp1_spi_b_default: blsp1-spi-b-default-state {
@ -1318,7 +1318,7 @@ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp2_i2c2_default: blsp2-i2c2-default-state {
@ -1332,7 +1332,7 @@ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp2_i2c3_default: blsp2-i2c3-default-state {
@ -1346,7 +1346,7 @@ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp2_i2c4_default: blsp2-i2c4-default-state {
@ -1360,7 +1360,7 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp2_i2c5_default: blsp2-i2c5-default-state {
@ -1374,7 +1374,7 @@ blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp2_i2c6_default: blsp2-i2c6-default-state {
@ -1388,7 +1388,7 @@ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
blsp2_spi1_default: blsp2-spi1-default-state {

2
arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
View File

@ -46,7 +46,7 @@ trip1 {
};
};
pmh0104-l1-thermal {
pmh0104_l1_thermal: pmh0104-l1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_l_e1_temp_alarm>;

2
arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi
View File

@ -46,7 +46,7 @@ trip1 {
};
};
pmh0110-h0-thermal {
pmh0110_h0_thermal: pmh0110-h0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_h_e0_temp_alarm>;

30
arch/arm64/boot/dts/qcom/pmk8550.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include "qcom-adc5-gen3.h"
/ {
reboot-mode {
@ -64,6 +65,35 @@ reboot_reason: reboot-reason@48 {
};
};
pmk8550_vadc: adc@9000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x9000>, <0x9100>;
interrupts-extended = <&spmi_bus 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
<&spmi_bus 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
#thermal-sensor-cells = <1>;
channel@0 {
reg = <ADC5_GEN3_REF_GND(0)>;
label = "pmk8550_offset_ref";
qcom,pre-scaling = <1 1>;
};
channel@1 {
reg = <ADC5_GEN3_1P25VREF(0)>;
label = "pmk8550_vref_1p25";
qcom,pre-scaling = <1 1>;
};
channel@3 {
reg = <ADC5_GEN3_DIE_TEMP(0)>;
label = "pmk8550_die_temp";
qcom,pre-scaling = <1 1>;
};
};
pmk8550_gpios: gpio@b800 {
compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio";
reg = <0xb800>;

21
arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
View File

@ -10,6 +10,7 @@
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
/delete-node/ &pmc8380_6_die_temp;
/ {
reserved-memory {
@ -587,8 +588,8 @@ &usb_1_ss0_hsphy {
};
&usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l1j_0p8>;
vdda-phy-supply = <&vreg_l1j_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
@ -608,8 +609,8 @@ &usb_1_ss1_hsphy {
};
&usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
vdda-phy-supply = <&vreg_l2d_0p9>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
@ -629,8 +630,8 @@ &usb_1_ss2_hsphy {
};
&usb_1_ss2_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
vdda-phy-supply = <&vreg_l2d_0p9>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
@ -667,15 +668,15 @@ &usb_mp_hsphy1 {
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3c_0p8>;
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3c_0p8>;
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -1554,8 +1554,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l1b>;
vdda-phy-supply = <&vreg_l1b>;
vdda-pll-supply = <&vreg_l6b>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -1141,8 +1141,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
vdda-phy-supply = <&vreg_l1b_0p912>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
View File

@ -841,8 +841,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
vdda-phy-supply = <&vreg_l1b_0p912>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
View File

@ -975,8 +975,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l1b>;
vdda-phy-supply = <&vreg_l1b>;
vdda-pll-supply = <&vreg_l6b>;
status = "okay";
};

88
arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h Normal file
View File

@ -0,0 +1,88 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__
#define __DTS_ARM64_QCOM_ADC5_GEN3_H__
/* ADC channels for PMIC5 Gen3 */
#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan))
#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00)
#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01)
#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02)
#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03)
#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04)
#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05)
#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06)
#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07)
#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08)
#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09)
#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a)
#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b)
#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c)
#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d)
#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10)
#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11)
#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12)
#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15)
#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17)
#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18)
#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19)
#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b)
#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1)
/* 30k pull-up */
#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24)
#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25)
#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26)
#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27)
#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28)
#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29)
#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a)
#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b)
#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c)
#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d)
/* 100k pull-up */
#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44)
#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45)
#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46)
#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47)
#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48)
#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49)
#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a)
#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b)
#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c)
#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d)
/* 400k pull-up */
#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64)
#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65)
#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66)
#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67)
#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68)
#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69)
#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a)
#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b)
#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c)
#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d)
/* 1/3 Divider */
#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a)
#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b)
#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c)
#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d)
#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e)
#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f)
#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94)
#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96)
#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d)
#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */

16
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -677,11 +677,11 @@ usb3: usb@7678800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"qusb2_phy";
"qusb2_phy",
"hs_phy_irq";
status = "disabled";
@ -716,11 +716,11 @@ usb2: usb@79b8800 {
assigned-clock-rates = <19200000>, <133333333>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"hs_phy_irq",
"qusb2_phy";
"qusb2_phy",
"hs_phy_irq";
status = "disabled";

18
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
View File

@ -549,15 +549,15 @@ &pcie1 {
pinctrl-names = "default";
/* Support for QPS615 PCIe switch */
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x400 &apps_smmu 0x1c88 0x1>,
<0x500 &apps_smmu 0x1c89 0x1>,
<0x501 &apps_smmu 0x1c90 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>,
<0x208 &apps_smmu 0x1c84 0x0 0x1>,
<0x210 &apps_smmu 0x1c85 0x0 0x1>,
<0x218 &apps_smmu 0x1c86 0x0 0x1>,
<0x300 &apps_smmu 0x1c87 0x0 0x1>,
<0x400 &apps_smmu 0x1c88 0x0 0x1>,
<0x500 &apps_smmu 0x1c89 0x0 0x1>,
<0x501 &apps_smmu 0x1c90 0x0 0x1>;
status = "okay";
};

58
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
View File

@ -54,15 +54,15 @@ &pcie0 {
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x208 &apps_smmu 0x1c04 0x1>,
<0x210 &apps_smmu 0x1c05 0x1>,
<0x218 &apps_smmu 0x1c06 0x1>,
<0x300 &apps_smmu 0x1c07 0x1>,
<0x400 &apps_smmu 0x1c08 0x1>,
<0x500 &apps_smmu 0x1c09 0x1>,
<0x501 &apps_smmu 0x1c10 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>,
<0x208 &apps_smmu 0x1c04 0x0 0x1>,
<0x210 &apps_smmu 0x1c05 0x0 0x1>,
<0x218 &apps_smmu 0x1c06 0x0 0x1>,
<0x300 &apps_smmu 0x1c07 0x0 0x1>,
<0x400 &apps_smmu 0x1c08 0x0 0x1>,
<0x500 &apps_smmu 0x1c09 0x0 0x1>,
<0x501 &apps_smmu 0x1c10 0x0 0x1>;
status = "okay";
};
@ -130,7 +130,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -138,7 +138,7 @@ pci@0,0 {
ranges;
};
pci@0,1 {
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -151,22 +151,22 @@ pci@0,1 {
};
&pcie1 {
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x408 &apps_smmu 0x1c90 0x1>,
<0x410 &apps_smmu 0x1c91 0x1>,
<0x418 &apps_smmu 0x1c92 0x1>,
<0x500 &apps_smmu 0x1c93 0x1>,
<0x600 &apps_smmu 0x1c94 0x1>,
<0x700 &apps_smmu 0x1c95 0x1>,
<0x701 &apps_smmu 0x1c96 0x1>,
<0x800 &apps_smmu 0x1c97 0x1>,
<0x900 &apps_smmu 0x1c98 0x1>,
<0x901 &apps_smmu 0x1c99 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>,
<0x208 &apps_smmu 0x1c84 0x0 0x1>,
<0x210 &apps_smmu 0x1c85 0x0 0x1>,
<0x218 &apps_smmu 0x1c86 0x0 0x1>,
<0x300 &apps_smmu 0x1c87 0x0 0x1>,
<0x408 &apps_smmu 0x1c90 0x0 0x1>,
<0x410 &apps_smmu 0x1c91 0x0 0x1>,
<0x418 &apps_smmu 0x1c92 0x0 0x1>,
<0x500 &apps_smmu 0x1c93 0x0 0x1>,
<0x600 &apps_smmu 0x1c94 0x0 0x1>,
<0x700 &apps_smmu 0x1c95 0x0 0x1>,
<0x701 &apps_smmu 0x1c96 0x0 0x1>,
<0x800 &apps_smmu 0x1c97 0x0 0x1>,
<0x900 &apps_smmu 0x1c98 0x0 0x1>,
<0x901 &apps_smmu 0x1c99 0x0 0x1>;
};
&pcie1_switch0_dsp1 {
@ -225,7 +225,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -233,7 +233,7 @@ pci@0,0 {
ranges;
};
pci@0,1 {
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

26
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@ -844,15 +844,15 @@ &pcie1 {
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x400 &apps_smmu 0x1c88 0x1>,
<0x500 &apps_smmu 0x1c89 0x1>,
<0x501 &apps_smmu 0x1c90 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>,
<0x208 &apps_smmu 0x1c84 0x0 0x1>,
<0x210 &apps_smmu 0x1c85 0x0 0x1>,
<0x218 &apps_smmu 0x1c86 0x0 0x1>,
<0x300 &apps_smmu 0x1c87 0x0 0x1>,
<0x400 &apps_smmu 0x1c88 0x0 0x1>,
<0x500 &apps_smmu 0x1c89 0x0 0x1>,
<0x501 &apps_smmu 0x1c90 0x0 0x1>;
status = "okay";
};
@ -954,7 +954,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -962,7 +962,7 @@ pci@0,0 {
ranges;
};
pci@0,1 {
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -1419,8 +1419,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
vdda-phy-supply = <&vreg_l1b_0p912>;
vdda-pll-supply = <&vreg_l6b_1p2>;
mode-switch;
orientation-switch;

26
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
View File

@ -714,15 +714,15 @@ &pcie1 {
<&pcie1_wake_n>;
pinctrl-names = "default";
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x400 &apps_smmu 0x1c88 0x1>,
<0x500 &apps_smmu 0x1c89 0x1>,
<0x501 &apps_smmu 0x1c90 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>,
<0x208 &apps_smmu 0x1c84 0x0 0x1>,
<0x210 &apps_smmu 0x1c85 0x0 0x1>,
<0x218 &apps_smmu 0x1c86 0x0 0x1>,
<0x300 &apps_smmu 0x1c87 0x0 0x1>,
<0x400 &apps_smmu 0x1c88 0x0 0x1>,
<0x500 &apps_smmu 0x1c89 0x0 0x1>,
<0x501 &apps_smmu 0x1c90 0x0 0x1>;
status = "okay";
};
@ -790,7 +790,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
pcie@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -798,7 +798,7 @@ pci@0,0 {
ranges;
};
pci@0,1 {
pcie@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@ -1065,8 +1065,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
vdda-phy-supply = <&vreg_l1b_0p912>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
View File

@ -1111,8 +1111,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
vdda-phy-supply = <&vreg_l1b_0p912>;
vdda-pll-supply = <&vreg_l6b_1p2>;
status = "okay";
};

2
arch/arm64/boot/dts/qcom/qcs8300-ride.dts
View File

@ -837,7 +837,7 @@ bluetooth: bluetooth {
vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
};
};

4
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
View File

@ -412,8 +412,8 @@ &usb_1_hsphy {
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
vdda-phy-supply = <&vreg_l3f_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
};
&xo_board {

5
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -171,6 +171,7 @@ cluster_sleep_1: cluster-sleep-1 {
firmware {
scm {
compatible = "qcom,scm-qdu1000", "qcom,scm";
sram = <&minidump_config>;
};
};
@ -1369,6 +1370,10 @@ sram@14680000 {
#address-cells = <1>;
#size-cells = <1>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;

8
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -1424,8 +1424,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p92>;
vdda-phy-supply = <&vreg_l18a_0p92>;
vdda-pll-supply = <&vreg_l9a_1p2>;
};
&usb_1_qmpphy_out {
@ -1451,8 +1451,8 @@ &usb_2_hsphy {
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p92>;
vdda-phy-supply = <&vreg_l18a_0p92>;
vdda-pll-supply = <&vreg_l9a_1p2>;
};
&vamacro {

8
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View File

@ -428,8 +428,8 @@ &ufs_mem_hc {
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vreg_l8c_1p2>;
vdda-pll-supply = <&vreg_l5a_0p88>;
vdda-phy-supply = <&vreg_l5a_0p88>;
vdda-pll-supply = <&vreg_l8c_1p2>;
};
&usb_1 {
@ -474,8 +474,8 @@ &usb_2_hsphy {
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l8c_1p2>;
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
vdda-phy-supply = <&vdda_usb_ss_dp_core_1>;
vdda-pll-supply = <&vreg_l8c_1p2>;
};
&pcie0 {

16
arch/arm64/boot/dts/qcom/sa8295p-adp.dts
View File

@ -612,8 +612,8 @@ &usb_0_hsphy {
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l3a>;
vdda-pll-supply = <&vreg_l5a>;
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
};
@ -636,8 +636,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4c>;
vdda-pll-supply = <&vreg_l1c>;
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l4c>;
status = "okay";
};
@ -679,15 +679,15 @@ &usb_2_hsphy3 {
};
&usb_2_qmpphy0 {
vdda-phy-supply = <&vreg_l3a>;
vdda-pll-supply = <&vreg_l5a>;
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
};
&usb_2_qmpphy1 {
vdda-phy-supply = <&vreg_l3a>;
vdda-pll-supply = <&vreg_l5a>;
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
};

8
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
View File

@ -482,8 +482,8 @@ &usb_0_hsphy {
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l3a>;
vdda-pll-supply = <&vreg_l5a>;
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
};
@ -497,8 +497,8 @@ &usb_2_hsphy0 {
};
&usb_2_qmpphy0 {
vdda-phy-supply = <&vreg_l3a>;
vdda-pll-supply = <&vreg_l5a>;
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
View File

@ -551,8 +551,8 @@ &usb_1_hsphy {
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p91>;
vdda-phy-supply = <&vreg_l1a_0p91>;
vdda-pll-supply = <&vreg_l3a_1p2>;
status = "okay";
};

8
arch/arm64/boot/dts/qcom/sar2130p.dtsi
View File

@ -1329,8 +1329,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
&config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
@ -1455,8 +1455,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
&config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>,
<0x100 &apps_smmu 0x1e01 0x0 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;

4
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
View File

@ -631,8 +631,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l4a_0p8>;
vdda-phy-supply = <&vreg_l4a_0p8>;
vdda-pll-supply = <&vreg_l3c_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts
View File

@ -563,8 +563,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l4a_0p8>;
vdda-phy-supply = <&vreg_l4a_0p8>;
vdda-pll-supply = <&vreg_l3c_1p2>;
/delete-property/ mode-switch;
/delete-property/ orientation-switch;

4
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@ -461,8 +461,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l4a_0p8>;
vdda-phy-supply = <&vreg_l4a_0p8>;
vdda-pll-supply = <&vreg_l3c_1p2>;
};
&venus {

4
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@ -998,8 +998,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb_ss_dp_1p2>;
vdda-pll-supply = <&vdda_usb_ss_dp_core>;
vdda-phy-supply = <&vdda_usb_ss_dp_core>;
vdda-pll-supply = <&vdda_usb_ss_dp_1p2>;
};
&venus {

5
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -385,6 +385,7 @@ cluster_aoss_sleep: cluster-sleep-2 {
firmware {
scm: scm {
compatible = "qcom,scm-sc7180", "qcom,scm";
sram = <&minidump_config>;
};
};
@ -3596,6 +3597,10 @@ sram@14680000 {
ranges = <0 0 0x14680000 0x2e000>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
ipa_modem_tables: modem-tables@28000 {
reg = <0x28000 0x2000>;
};

4
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -545,8 +545,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p8>;
vdda-phy-supply = <&vreg_l1b_0p8>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&uart7 {

4
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View File

@ -465,8 +465,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>;
vdda-pll-supply = <&vdd_a_usbssdp_0_core>;
vdda-phy-supply = <&vdd_a_usbssdp_0_core>;
vdda-pll-supply = <&vdd_a_usbssdp_0_1p2>;
};
&usb_2_hsphy {

16
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
View File

@ -611,15 +611,15 @@ &usb_mp_hsphy1 {
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
status = "okay";
};
@ -633,8 +633,8 @@ &usb_prim_hsphy {
};
&usb_prim_qmpphy {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
orientation-switch;
@ -674,8 +674,8 @@ &usb_sec_hsphy {
};
&usb_sec_qmpphy {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
orientation-switch;

16
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
View File

@ -703,15 +703,15 @@ &usb_mp_hsphy1 {
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
status = "okay";
};
@ -725,8 +725,8 @@ &usb_prim_hsphy {
};
&usb_prim_qmpphy {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
orientation-switch;
@ -762,8 +762,8 @@ &usb_sec_hsphy {
};
&usb_sec_qmpphy {
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
orientation-switch;

16
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -1767,8 +1767,8 @@ pcie0: pcie@1c00000 {
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x0 0x1>,
<0x100 &apps_smmu 0x1d81 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
@ -1886,8 +1886,8 @@ pcie3: pcie@1c08000 {
assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>,
<0x100 &apps_smmu 0x1e01 0x0 0x1>;
resets = <&gcc GCC_PCIE_3_BCR>;
reset-names = "pci";
@ -2006,8 +2006,8 @@ pcie1: pcie@1c10000 {
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
@ -2126,8 +2126,8 @@ pcie2: pcie@1c18000 {
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
<0x100 &apps_smmu 0x1d01 0x1>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x0 0x1>,
<0x100 &apps_smmu 0x1d01 0x0 0x1>;
resets = <&gcc GCC_PCIE_2_BCR>;
reset-names = "pci";

6
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -56,6 +56,8 @@ pmic-glink {
#address-cells = <1>;
#size-cells = <0>;
orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>,
<&tlmm 49 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
@ -182,7 +184,7 @@ vreg_misc_3p3: regulator-misc-3p3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>;
gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
@ -919,7 +921,7 @@ kypd_vol_up_n: kypd-vol-up-n-state {
};
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio2";
pins = "gpio1";
function = "normal";
};
};

8
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
View File

@ -996,8 +996,8 @@ &usb_0_hsphy {
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l4d>;
vdda-pll-supply = <&vreg_l9d>;
vdda-phy-supply = <&vreg_l9d>;
vdda-pll-supply = <&vreg_l4d>;
orientation-switch;
@ -1033,8 +1033,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l3b>;
vdda-pll-supply = <&vreg_l4b>;
vdda-phy-supply = <&vreg_l4b>;
vdda-pll-supply = <&vreg_l3b>;
orientation-switch;

2
arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts
View File

@ -130,7 +130,7 @@ led-controller@36 {
led: led@1 {
reg = <1>;
default-trigger = "backlight";
linux,default-trigger = "backlight";
function = LED_FUNCTION_BACKLIGHT;
led-sources = <0 1 2>;
};

8
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@ -1121,8 +1121,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p875>;
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
};
&usb_2 {
@ -1147,8 +1147,8 @@ &usb_2_hsphy {
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p875>;
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
};
&ufs_mem_hc {

4
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
View File

@ -571,8 +571,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p875>;
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
View File

@ -674,8 +674,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
vdda-phy-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_usb1_ss_1p2>;
status = "okay";
};

8
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View File

@ -727,8 +727,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
vdda-phy-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_usb1_ss_1p2>;
};
&usb_2 {
@ -759,8 +759,8 @@ &usb_2_hsphy {
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
vdda-phy-supply = <&vdda_usb2_ss_core>;
vdda-pll-supply = <&vdda_usb2_ss_1p2>;
};
&venus {

4
arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts
View File

@ -947,8 +947,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
vdda-phy-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_usb1_ss_1p2>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View File

@ -874,8 +874,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p875>;
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
};
&venus {

4
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
View File

@ -643,8 +643,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p875>;
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
};
&venus {

4
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
View File

@ -666,8 +666,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-pll-supply = <&vreg_l1a_0p875>;
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l26a_1p2>;
vdda-phy-supply = <&vreg_l1a_0p875>;
status = "okay";
};

69
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -363,6 +363,7 @@ cluster_sleep_0: cluster-sleep-0 {
firmware {
scm {
compatible = "qcom,scm-sdm845", "qcom,scm";
sram = <&minidump_config>;
};
};
@ -2372,22 +2373,22 @@ pcie0: pcie@1c00000 {
"slave_q2a",
"tbu";
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
<0x100 &apps_smmu 0x1c11 0x1>,
<0x200 &apps_smmu 0x1c12 0x1>,
<0x300 &apps_smmu 0x1c13 0x1>,
<0x400 &apps_smmu 0x1c14 0x1>,
<0x500 &apps_smmu 0x1c15 0x1>,
<0x600 &apps_smmu 0x1c16 0x1>,
<0x700 &apps_smmu 0x1c17 0x1>,
<0x800 &apps_smmu 0x1c18 0x1>,
<0x900 &apps_smmu 0x1c19 0x1>,
<0xa00 &apps_smmu 0x1c1a 0x1>,
<0xb00 &apps_smmu 0x1c1b 0x1>,
<0xc00 &apps_smmu 0x1c1c 0x1>,
<0xd00 &apps_smmu 0x1c1d 0x1>,
<0xe00 &apps_smmu 0x1c1e 0x1>,
<0xf00 &apps_smmu 0x1c1f 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c10 0x0 0x1>,
<0x100 &apps_smmu 0x1c11 0x0 0x1>,
<0x200 &apps_smmu 0x1c12 0x0 0x1>,
<0x300 &apps_smmu 0x1c13 0x0 0x1>,
<0x400 &apps_smmu 0x1c14 0x0 0x1>,
<0x500 &apps_smmu 0x1c15 0x0 0x1>,
<0x600 &apps_smmu 0x1c16 0x0 0x1>,
<0x700 &apps_smmu 0x1c17 0x0 0x1>,
<0x800 &apps_smmu 0x1c18 0x0 0x1>,
<0x900 &apps_smmu 0x1c19 0x0 0x1>,
<0xa00 &apps_smmu 0x1c1a 0x0 0x1>,
<0xb00 &apps_smmu 0x1c1b 0x0 0x1>,
<0xc00 &apps_smmu 0x1c1c 0x0 0x1>,
<0xd00 &apps_smmu 0x1c1d 0x0 0x1>,
<0xe00 &apps_smmu 0x1c1e 0x0 0x1>,
<0xf00 &apps_smmu 0x1c1f 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
@ -2502,22 +2503,22 @@ pcie1: pcie@1c08000 {
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x200 &apps_smmu 0x1c02 0x1>,
<0x300 &apps_smmu 0x1c03 0x1>,
<0x400 &apps_smmu 0x1c04 0x1>,
<0x500 &apps_smmu 0x1c05 0x1>,
<0x600 &apps_smmu 0x1c06 0x1>,
<0x700 &apps_smmu 0x1c07 0x1>,
<0x800 &apps_smmu 0x1c08 0x1>,
<0x900 &apps_smmu 0x1c09 0x1>,
<0xa00 &apps_smmu 0x1c0a 0x1>,
<0xb00 &apps_smmu 0x1c0b 0x1>,
<0xc00 &apps_smmu 0x1c0c 0x1>,
<0xd00 &apps_smmu 0x1c0d 0x1>,
<0xe00 &apps_smmu 0x1c0e 0x1>,
<0xf00 &apps_smmu 0x1c0f 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>,
<0x200 &apps_smmu 0x1c02 0x0 0x1>,
<0x300 &apps_smmu 0x1c03 0x0 0x1>,
<0x400 &apps_smmu 0x1c04 0x0 0x1>,
<0x500 &apps_smmu 0x1c05 0x0 0x1>,
<0x600 &apps_smmu 0x1c06 0x0 0x1>,
<0x700 &apps_smmu 0x1c07 0x0 0x1>,
<0x800 &apps_smmu 0x1c08 0x0 0x1>,
<0x900 &apps_smmu 0x1c09 0x0 0x1>,
<0xa00 &apps_smmu 0x1c0a 0x0 0x1>,
<0xb00 &apps_smmu 0x1c0b 0x0 0x1>,
<0xc00 &apps_smmu 0x1c0c 0x0 0x1>,
<0xd00 &apps_smmu 0x1c0d 0x0 0x1>,
<0xe00 &apps_smmu 0x1c0e 0x0 0x1>,
<0xf00 &apps_smmu 0x1c0f 0x0 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
@ -5195,6 +5196,10 @@ sram@14680000 {
ranges = <0 0 0x14680000 0x40000>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
ipa_modem_tables: modem-tables@3d000 {
reg = <0x3d000 0x2000>;
};

8
arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts
View File

@ -870,8 +870,8 @@ &usb_1_hsphy {
};
&usb_1_qmpphy {
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
vdda-phy-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_usb1_ss_1p2>;
status = "okay";
};
@ -896,8 +896,8 @@ &usb_2_hsphy {
};
&usb_2_qmpphy {
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
vdda-phy-supply = <&vdda_usb2_ss_core>;
vdda-pll-supply = <&vdda_usb2_ss_1p2>;
status = "okay";
};

8
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View File

@ -858,8 +858,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
vdda-phy-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_usb1_ss_1p2>;
};
&usb_1_qmpphy_out {
@ -951,8 +951,8 @@ &usb_2_hsphy {
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
vdda-phy-supply = <&vdda_usb2_ss_core>;
vdda-pll-supply = <&vdda_usb2_ss_1p2>;
};
&venus {

8
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
View File

@ -608,8 +608,8 @@ &usb_1_hsphy {
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
vdda-phy-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_usb1_ss_1p2>;
};
&usb_2 {
@ -634,8 +634,8 @@ &usb_2_hsphy {
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
vdda-phy-supply = <&vdda_usb2_ss_core>;
vdda-pll-supply = <&vdda_usb2_ss_1p2>;
};
&venus {

19
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
View File

@ -23,6 +23,25 @@ chosen {
};
};
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
status = "okay";
};
&remoteproc_lpaicp {
firmware-name = "qcom/shikra/lpaicp.mbn",
"qcom/shikra/lpaicp_dtb.mbn";
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;

80
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
View File

@ -11,6 +11,10 @@
#include "pm8005.dtsi"
/ {
aliases {
serial1 = &uart8;
};
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@ -27,6 +31,42 @@ key-volume-up {
linux,can-disable;
};
};
wcn3988-pmu {
compatible = "qcom,wcn3988-pmu";
pinctrl-0 = <&sw_ctrl_default>;
pinctrl-names = "default";
swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
vddio-supply = <&pm4125_l7>;
vddxo-supply = <&pm4125_l13>;
vddrf-supply = <&pm4125_l10>;
vddch0-supply = <&pm4125_l22>;
regulators {
vreg_pmu_io: ldo0 {
regulator-name = "vreg_pmu_io";
};
vreg_pmu_xo: ldo1 {
regulator-name = "vreg_pmu_xo";
};
vreg_pmu_rf: ldo2 {
regulator-name = "vreg_pmu_rf";
};
vreg_pmu_ch0: ldo3 {
regulator-name = "vreg_pmu_ch0";
};
vreg_pmu_ch1: ldo4 {
regulator-name = "vreg_pmu_ch1";
};
};
};
};
&pm4125_gpios {
@ -154,3 +194,43 @@ pm4125_l22: l22 {
};
};
};
&tlmm {
gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */
<14 4>, /* eSE SPI */
<30 2>, /* NFC SPI */
<138 1>, /* NFC Secure IO */
<155 11>; /* eMMC Boot */
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio88";
function = "gpio";
bias-pull-down;
};
};
&uart8 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3988-bt";
max-speed = <3200000>;
vddio-supply = <&vreg_pmu_io>;
vddxo-supply = <&vreg_pmu_xo>;
vddrf-supply = <&vreg_pmu_rf>;
vddch0-supply = <&vreg_pmu_ch0>;
};
};
&wifi {
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
vdd-1.8-xo-supply = <&vreg_pmu_xo>;
vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
qcom,calibration-variant = "Shikra_EVK";
firmware-name = "shikra";
status = "okay";
};

19
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
View File

@ -23,6 +23,25 @@ chosen {
};
};
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
status = "okay";
};
&remoteproc_lpaicp {
firmware-name = "qcom/shikra/lpaicp.mbn",
"qcom/shikra/lpaicp_dtb.mbn";
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;

19
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
View File

@ -23,6 +23,25 @@ chosen {
};
};
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
status = "okay";
};
&remoteproc_lpaicp {
firmware-name = "qcom/shikra/lpaicp.mbn",
"qcom/shikra/lpaicp_dtb.mbn";
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;

88
arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi
View File

@ -10,6 +10,10 @@
#include "pm8150.dtsi"
/ {
aliases {
serial1 = &uart8;
};
gpio-key {
compatible = "gpio-keys";
label = "gpio-keys";
@ -26,6 +30,50 @@ key-volume-up {
linux,can-disable;
};
};
vreg_wcn_3p3: regulator-wcn-3p3 {
compatible = "regulator-fixed";
regulator-name = "wcn_3p3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
wcn3988-pmu {
compatible = "qcom,wcn3988-pmu";
pinctrl-0 = <&sw_ctrl_default>;
pinctrl-names = "default";
swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
vddio-supply = <&pm8150_s4>;
vddxo-supply = <&pm8150_l12>;
vddrf-supply = <&pm8150_l8>;
vddch0-supply = <&vreg_wcn_3p3>;
regulators {
vreg_pmu_io: ldo0 {
regulator-name = "vreg_pmu_io";
};
vreg_pmu_xo: ldo1 {
regulator-name = "vreg_pmu_xo";
};
vreg_pmu_rf: ldo2 {
regulator-name = "vreg_pmu_rf";
};
vreg_pmu_ch0: ldo3 {
regulator-name = "vreg_pmu_ch0";
};
vreg_pmu_ch1: ldo4 {
regulator-name = "vreg_pmu_ch1";
};
};
};
};
&pm8150_gpios {
@ -168,3 +216,43 @@ pm8150_l18: l18 {
};
};
};
&tlmm {
gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */
<14 4>, /* eSE SPI */
<30 2>, /* NFC SPI */
<138 1>, /* NFC Secure IO */
<155 11>; /* eMMC Boot */
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio88";
function = "gpio";
bias-pull-down;
};
};
&uart8 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3988-bt";
max-speed = <3200000>;
vddio-supply = <&vreg_pmu_io>;
vddxo-supply = <&vreg_pmu_xo>;
vddrf-supply = <&vreg_pmu_rf>;
vddch0-supply = <&vreg_pmu_ch0>;
};
};
&wifi {
vdd-0.8-cx-mx-supply = <&pm8150_s4>;
vdd-1.8-xo-supply = <&vreg_pmu_xo>;
vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
qcom,calibration-variant = "Shikra_EVK";
firmware-name = "shikra";
status = "okay";
};

1692
arch/arm64/boot/dts/qcom/shikra.dtsi
View File

File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi
View File

@ -133,6 +133,8 @@ connector {
typec-power-opmode = "default";
pd-disable;
vbus-supply = <&pmi632_vbus>;
port {
pmi632_hs_in: endpoint {
remote-endpoint = <&usb_dwc3_hs>;

5
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -363,6 +363,7 @@ big_cpu_sleep_1: cpu-sleep-1-1 {
firmware {
scm: scm {
compatible = "qcom,scm-sm6350", "qcom,scm";
sram = <&minidump_config>;
#reset-cells = <1>;
};
};
@ -2820,6 +2821,10 @@ sram@14680000 {
ranges = <0 0 0x14680000 0x2e000>;
minidump_config: minidump-sram@1c {
reg = <0x1c 0x4>;
};
ipa_modem_tables: modem-tables@28000 {
reg = <0x28000 0x2000>;
};

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