From c8748463283738aacf323eb3f7853e6533d941dc Mon Sep 17 00:00:00 2001 From: Stanislav Zaikin Date: Thu, 30 Jul 2026 10:54:21 +0200 Subject: [PATCH 001/117] arm64: dts: qcom: taoyao: Drop adsp_rpc_remote_heap_mem override taoyao originally redefined adsp_rpc_remote_heap_mem at a fixed address to avoid overlapping with cdsp_mem, since kodiak.dtsi's version was a fixed-address at the time. kodiak.dtsi now defines adsp_rpc_remote_heap_mem as a dynamically allocated "shared-dma-pool" region instead, which removes the fixed address entirely and so cannot overlap with cdsp_mem. This makes the override unnecessary. Remove the taoyao-local /delete-node/ and static reg-based redefinition, and inherit the definition from kodiak.dtsi instead. Fixes: 28705df5d0df ("arm64: dts: qcom: sm7325: Add Xiaomi 12 Lite 5G (taoyao) DTS") Signed-off-by: Stanislav Zaikin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260730085422.631896-1-zstaseg@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts index 6f8bc65bb99b..87f267aaeec0 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts @@ -27,7 +27,6 @@ /* The following reserved memory regions have different addresses or sizes */ /delete-node/ &adsp_mem; -/delete-node/ &adsp_rpc_remote_heap_mem; /delete-node/ &cdsp_mem; /delete-node/ &rmtfs_mem; @@ -203,11 +202,6 @@ neuron_block_1_mem: neuron-block@d7f80000 { no-map; }; - adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@e0400000 { - reg = <0x0 0xe0400000 0x0 0x800000>; - no-map; - }; - framebuffer_reserved: framebuffer@e1000000 { reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; no-map; From 882bb27c61610f16e54caa2dc75bacf977f614c9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 17 Apr 2026 09:07:46 +0200 Subject: [PATCH 002/117] arm64: dts: qcom: milos: Add GX clock controller Add a node for the GX clock controller, which provides a power domain to consumers. Reviewed-by: Konrad Dybcio Reviewed-by: Jagadeesh Kona Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260417-milos-gxclkctl-v3-3-08f5988c43a2@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index e91c0cf5e093..aad8bf678916 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1591,6 +1591,16 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,milos-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,milos-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; From 58ce9a2b9099bb26aed55d4e350c32af94930532 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 12:59:58 +0200 Subject: [PATCH 003/117] arm64: dts: qcom: msm8998: Don't pull-up I2C pins by default in sleep When the I2C controller is disabled, no communication is expected to take place. Without traffic on the bus, the pull-up is unnecessary. Both the vendor kernel for this platform and DTs of other SoCs in upstream concur this logic. Change the default and clean up now-NOP overrides. Fixes: 0fee55fc0de7 ("arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-1-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ---- .../boot/dts/qcom/msm8998-xiaomi-sagit.dts | 5 ---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 24 +++++++++---------- 3 files changed, 12 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 3650f2501886..04d4741cdb5f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -229,10 +229,6 @@ rmi4-f11@11 { }; }; -&blsp1_i2c5_sleep { - bias-disable; -}; - &blsp1_uart3 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index 30222f6608da..69528771eda2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -217,11 +217,6 @@ rmi4-f1a@1a { }; }; -&blsp1_i2c5_sleep { - /delete-property/ bias-pull-up; - bias-disable; -}; - &blsp1_uart3 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 347706011637..5038d0009c1a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1183,7 +1183,7 @@ blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c2_default: blsp1-i2c2-default-state { @@ -1197,7 +1197,7 @@ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { pins = "gpio32", "gpio33"; function = "blsp_i2c2"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c3_default: blsp1-i2c3-default-state { @@ -1211,7 +1211,7 @@ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c4_default: blsp1-i2c4-default-state { @@ -1225,7 +1225,7 @@ blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { pins = "gpio10", "gpio11"; function = "blsp_i2c4"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c5_default: blsp1-i2c5-default-state { @@ -1239,7 +1239,7 @@ blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { pins = "gpio87", "gpio88"; function = "blsp_i2c5"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c6_default: blsp1-i2c6-default-state { @@ -1253,7 +1253,7 @@ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { pins = "gpio43", "gpio44"; function = "blsp_i2c6"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_spi_b_default: blsp1-spi-b-default-state { @@ -1318,7 +1318,7 @@ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c2_default: blsp2-i2c2-default-state { @@ -1332,7 +1332,7 @@ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c3_default: blsp2-i2c3-default-state { @@ -1346,7 +1346,7 @@ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c4_default: blsp2-i2c4-default-state { @@ -1360,7 +1360,7 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { pins = "gpio67", "gpio68"; function = "blsp_i2c10"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c5_default: blsp2-i2c5-default-state { @@ -1374,7 +1374,7 @@ blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c6_default: blsp2-i2c6-default-state { @@ -1388,7 +1388,7 @@ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { pins = "gpio83", "gpio84"; function = "blsp_i2c12"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_spi1_default: blsp2-spi1-default-state { From bd0bb7d97773026c9f5d5f8ff1dcf987f8051045 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 12:59:59 +0200 Subject: [PATCH 004/117] arm64: dts: qcom: msm8976-longcheer-l9360: Fix accidental node override The active and sleep pinctrl states for the touchscreen interrupt pin shared the same node name, creating a single node, accidentally overridden immediately after the definition. Alter the names to make them distinct and to silence DT checker warnings. Fixes: 79b896e7da7e ("arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-2-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts index 18832a3b9a1c..57f549f06f73 100644 --- a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts +++ b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts @@ -455,14 +455,14 @@ sdc2_cd_sleep: sdc2-cd-sleep-state { bias-disable; }; - ts_int_default: ts-int-state { + ts_int_default: ts-int-default-state { pins = "gpio65"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - ts_int_sleep: ts-int-state { + ts_int_sleep: ts-int-sleep-state { pins = "gpio65"; function = "gpio"; drive-strength = <2>; From c82ea31fb783d9ce4080eca1a7bb855f4648fc28 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 13:00:00 +0200 Subject: [PATCH 005/117] arm64: dts: qcom: sdm632-motorola-ocean: Fix LED default trigger property The correct property name is "linux,default-trigger", not "default-trigger". Fix it to avoid DT checker warnings and let the OSes consume the intended information. Fixes: 3176c4d6b9be ("arm64: dts: qcom: sdm632: Add device tree for Motorola G7 Power") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-3-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts index 2f55db0c8ce3..9ea3e5e76bf9 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts @@ -130,7 +130,7 @@ led-controller@36 { led: led@1 { reg = <1>; - default-trigger = "backlight"; + linux,default-trigger = "backlight"; function = LED_FUNCTION_BACKLIGHT; led-sources = <0 1 2>; }; From a3b31d7e12e60f40cd4ea1f54126c38dd666fbe4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 13:00:01 +0200 Subject: [PATCH 006/117] arm64: dts: qcom: qcs8300-ride: Fix BT RFA supply name Fix up the supply name to align with qcom,wcn6855-bt bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-4-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index e9a8553a8d82..1ff39530ea3d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -837,7 +837,7 @@ bluetooth: bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From c680d03c73d17235b8e5fdaa9086e35c15855146 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 13:00:02 +0200 Subject: [PATCH 007/117] arm64: dts: qcom: talos-evk-som: Fix BT RFA supply name Fix up the supply name to align with qcom,wcn6855-bt bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-5-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 6d2cff3cf23c..a057a7271480 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -535,7 +535,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From 9812d0a3077489f67afaca84dcc7e01a440ee106 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 23 Jul 2026 13:47:04 +0530 Subject: [PATCH 008/117] arm64: dts: qcom: qcs404: Fix DTBS Check errors in usb controller nodes The following errors pop up when DTBS check is done for qcs404 based platforms: arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@79b8800 (qcom,qcs404- dwc3): interrupt-names:1: 'qusb2_phy' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@79b8800 (qcom,qcs404- dwc3): interrupt-names:2: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@7678800 (qcom,qcs404- dwc3): interrupt-names:2: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@7678800 (qcom,qcs404- dwc3): interrupt-names:1: 'qusb2_phy' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml Modify ordering of hs_phy and qusb2_phy interrupts to fix the errors. Fixes: 927173bf8a0e ("arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260723-qcs404_dtbs_fix-v1-1-c9ca0dd69f23@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 4328c1dda898..736accfc34f9 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -677,11 +677,11 @@ usb3: usb@7678800 { assigned-clock-rates = <19200000>, <200000000>; interrupts = , - , - ; + , + ; interrupt-names = "pwr_event", - "hs_phy_irq", - "qusb2_phy"; + "qusb2_phy", + "hs_phy_irq"; status = "disabled"; @@ -716,11 +716,11 @@ usb2: usb@79b8800 { assigned-clock-rates = <19200000>, <133333333>; interrupts = , - , - ; + , + ; interrupt-names = "pwr_event", - "hs_phy_irq", - "qusb2_phy"; + "qusb2_phy", + "hs_phy_irq"; status = "disabled"; From 0cd1b39cf234321fb5c2450dc788ef296cb02cb2 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 22 Jul 2026 16:01:55 +0530 Subject: [PATCH 009/117] arm64: dts: qcom: Update spmi-pmic-arb interrupt trigger for shikra SPMI interrupts are not working after suspend/resume on Shikra. Update the spmi-pmic-arb top-level interrupt trigger type from IRQ_TYPE_EDGE_RISING to IRQ_TYPE_LEVEL_HIGH, as recommended by the hardware design team. Signed-off-by: Rakesh Kota Link: https://lore.kernel.org/r/20260722-fix_shikra_spmi_interrupt_trigger_type-v1-1-1f8a13528cd7@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4e5bc9e17c8e..80e8045282d8 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -511,7 +511,7 @@ spmi_bus: spmi@1c40000 { "obsrvr", "intr", "cnfg"; - interrupts-extended = <&mpm 86 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; #interrupt-cells = <4>; From 67b5818ecadeb75e29c14add973b8cada2a73788 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Fri, 17 Jul 2026 17:28:35 +0530 Subject: [PATCH 010/117] arm64: dts: qcom: glymur-crd: Add FocalTech ft3d81 touchscreen support The touchscreen module on Glymur/Mahua CRDs is different from the one used on Hamoa CRDs and requires the reset-gpios to be wired to the device. Without this in place the reset line will remain permanently asserted during resume leaving the device offline and causing all I2C transactions to fail with -ENXIO. i2c_hid_of 3-0038: failed to change power setting. i2c_hid_of 3-0038: PM: dpm_run_callback(): i2c_hid_core_pm_resume [i2c_hid] returns -6 i2c_hid_of 3-0038: PM: failed to resume async: error -6 The touchscreen on Glymur/Mahua-CRD is a focaltech ft3d81, which is hardware-compatible with the ft8112. we have added the required change in DT. Fixes: e6bf559f7eb9 ("arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen") Fixes: f64ef325f1d9 ("arm64: dts: glymur-crd: Add reset GPIO to touchscreen node") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Pradyot Kumar Nayak Link: https://lore.kernel.org/r/20260717-add_focaltech_ft3d81_touchscreen_support-v4-2-5dd091e25801@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index ddf9902e1c4f..22f8011eb447 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -679,14 +679,13 @@ &i2c8 { status = "okay"; touchscreen@38 { - compatible = "hid-over-i2c"; + compatible = "focaltech,ft3d81", "focaltech,ft8112"; reg = <0x38>; - hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; + vcc33-supply = <&vreg_misc_3p3>; + vccio-supply = <&vreg_l15b_e0_1p8>; reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; From e806c63ba51a70aa8e19f749eb36b4d81760f705 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 12:32:37 +0200 Subject: [PATCH 011/117] arm64: dts: qcom: Rename pci@ nodes to pcie@ PCIe hosts/devices commonly use the 'pcie' for their node name to reflect they're not legacy PCI. Every couple months someone comes around to clean this up because people keep introducing new uses of 'pci@'. Seems like it's my turn now, so do that for RCs and the downstream devices (switches etc.) defined in board files. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260701-topic-dts_pci_pcie-v1-1-aab8de213b39@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/hamoa.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 4 ++-- arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++-- .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 8 ++++---- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++-- 9 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 6356f977f720..72c23aef1207 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2827,7 +2827,7 @@ pcie_west_slv_noc: interconnect@1920000 { #interconnect-cells = <2>; }; - pcie4: pci@1bf0000 { + pcie4: pcie@1bf0000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01bf0000 0x0 0x3000>, @@ -3043,7 +3043,7 @@ pcie4_phy: phy@1bf6000 { status = "disabled"; }; - pcie5: pci@1b40000 { + pcie5: pcie@1b40000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01b40000 0x0 0x3000>, @@ -3315,7 +3315,7 @@ pcie5_phy: phy@1b50000 { status = "disabled"; }; - pcie6: pci@1c00000 { + pcie6: pcie@1c00000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01c00000 0x0 0x3000>, @@ -3531,7 +3531,7 @@ pcie6_phy: phy@1c06000 { status = "disabled"; }; - pcie3b: pci@1b80000 { + pcie3b: pcie@1b80000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01b80000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 09527dcf9576..86168e445340 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3404,7 +3404,7 @@ pcie3_phy: phy@1be0000 { status = "disabled"; }; - pcie6a: pci@1bf8000 { + pcie6a: pcie@1bf8000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01bf8000 0 0x3000>, @@ -3547,7 +3547,7 @@ pcie6a_phy: phy@1bfc000 { status = "disabled"; }; - pcie5: pci@1c00000 { + pcie5: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01c00000 0 0x3000>, @@ -3684,7 +3684,7 @@ pcie5_phy: phy@1c06000 { status = "disabled"; }; - pcie4: pci@1c08000 { + pcie4: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01c08000 0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 44bd9b1a1765..4fc5f482a18f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -271,7 +271,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -279,7 +279,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index d1346ca5dd4e..299d0da15a15 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -421,7 +421,7 @@ &pcie1 { &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pci@0,0 { + pcie@0,0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -429,7 +429,7 @@ pci@0,0 { ranges; reg = <0x010000 0x00 0x00 0x00 0x00>; - pci@2,0 { + pcie@2,0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index e6beb4393430..77c28c19d17a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -117,7 +117,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -125,7 +125,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index efe1e74fe509..a2daef463c3d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2256,7 +2256,7 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, @@ -2435,7 +2435,7 @@ pcie0_phy: phy@1c04000 { status = "disabled"; }; - pcie1: pci@1c10000 { + pcie1: pcie@1c10000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c10000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 83908db335af..937b63eae3ba 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -130,7 +130,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -138,7 +138,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -225,7 +225,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -233,7 +233,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e9a932c90d14..1acbfe7baa13 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -954,7 +954,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -962,7 +962,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index c8eed8ba93f5..4f6932dd1139 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -790,7 +790,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -798,7 +798,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; From 91721a3f37ab4caf8441f0205497bcd478315433 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 17:43:15 +0200 Subject: [PATCH 012/117] arm64: dts: qcom: sc8280xp-crd: Add pmic-glink orientation GPIOs The PMIC_GLINK USB-C setup on SC8280XP requires that an orientation GPIO is passed for each port, the value of which communicates the normal/reversed state of the plug. Add the missing references to let the OS access that information. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260701-topic-8280crd_fixups-v1-1-3fe92ee9636b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 67f0576f2824..b8b5cf217764 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -56,6 +56,8 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From 0e05c183f3b97427f00d619132ba5984494f6886 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 17:43:16 +0200 Subject: [PATCH 013/117] arm64: dts: qcom: sc8280xp-crd: Fix the pin index for misc_3p3_reg_en The correct pin is GPIO1. Fix it. Fixes: ccd3517faf18 ("arm64: dts: qcom: sc8280xp: Add reference device") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260701-topic-8280crd_fixups-v1-2-3fe92ee9636b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index b8b5cf217764..1eea9d710d5b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -184,7 +184,7 @@ vreg_misc_3p3: regulator-misc-3p3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>; + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -921,7 +921,7 @@ kypd_vol_up_n: kypd-vol-up-n-state { }; misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio2"; + pins = "gpio1"; function = "normal"; }; }; From f1b63ded8bff1e6277a2b9f6e96c789ddcf90656 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:20 +0530 Subject: [PATCH 014/117] arm64: dts: qcom: ipq8074: move PCIe phys and PERST# to port node To align with the newer style of binding, move the phys, PERST# to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-1-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 10 ++++++++-- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++-------- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 5cf07caf4103..dea5ece600d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -54,12 +54,18 @@ &blsp1_uart5 { &pcie0 { status = "okay"; - perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie_qmp0 { diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 34e2f80514a3..f5c125e20ada 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -40,12 +40,18 @@ &blsp1_uart5 { &pcie0 { status = "okay"; - perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie_qmp0 { diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 256e12cf6d54..75a5ae30d966 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -841,9 +841,6 @@ pcie1: pcie@10000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_qmp1>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ @@ -902,11 +899,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky"; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_qmp1>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -929,9 +928,6 @@ pcie0: pcie@20000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_qmp0>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ @@ -993,11 +989,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_s_sticky"; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_qmp0>; + #address-cells = <3>; #size-cells = <2>; ranges; From 1198b7ff1fdd2ae77ab2e5b3cddd4fa2aa9f38bd Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:21 +0530 Subject: [PATCH 015/117] arm64: dts: qcom: ipq6018: move PCIe phys to port node To align with the newer style of binding, move the phys property to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-2-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7866844cc09f..0701517275d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -889,9 +889,6 @@ pcie0: pcie@20000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_phy>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; @@ -956,6 +953,8 @@ pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From a95758e9718ad686e9e7e8addcc181bea853e5a2 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:22 +0530 Subject: [PATCH 016/117] arm64: dts: qcom: ipq5018: move PCIe phys and PERST# to port node To align with the newer style of binding, move the phys, PERST# to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-3-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 8 +++++--- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 12 +++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index df3cbb7c79c4..33eef92b19b1 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -34,9 +34,6 @@ &pcie0 { pinctrl-0 = <&pcie0_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -44,6 +41,11 @@ &pcie0_phy { status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index b5bfd5dcabad..4fc627b47fe7 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -758,9 +758,6 @@ pcie1: pcie@80000000 { /* The controller supports Gen3, but the connected PHY is Gen2-capable */ max-link-speed = <2>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; @@ -829,6 +826,8 @@ pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -859,9 +858,6 @@ pcie0: pcie@a0000000 { /* The controller supports Gen3, but the connected PHY is Gen2-capable */ max-link-speed = <2>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; @@ -925,11 +921,13 @@ pcie0: pcie@a0000000 { status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From b99a594cfdd0862709ec54bdc356360e332377f6 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:23 +0530 Subject: [PATCH 017/117] arm64: dts: qcom: ipq9574: Add PCIe bridge node The PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, to align with the newer style of binding, move the phys and perst to port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-4-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/ipq9574-rdp433-common.dtsi | 39 ++++++++----- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 56 ++++++++++++++++--- 2 files changed, 72 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi index 3422058ac480..ad3a82c50e22 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi @@ -6,16 +6,26 @@ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ -&pcie1_phy { - status = "okay"; -}; - &pcie1 { pinctrl-0 = <&pcie1_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + pinctrl-0 = <&pcie2_default>; + pinctrl-names = "default"; + status = "okay"; }; @@ -23,12 +33,15 @@ &pcie2_phy { status = "okay"; }; -&pcie2 { - pinctrl-0 = <&pcie2_default>; +&pcie2_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -36,13 +49,9 @@ &pcie3_phy { status = "okay"; }; -&pcie3 { - pinctrl-0 = <&pcie3_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; +&pcie3_port0 { + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; - status = "okay"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 451c2076f6a7..5a5bda5f21a1 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -1004,12 +1004,22 @@ pcie1: pcie@10000000 { "aux", "ahb"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie1_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie1_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3: pcie@18000000 { @@ -1092,12 +1102,22 @@ pcie3: pcie@18000000 { "aux", "ahb"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie3_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@20000000 { @@ -1180,12 +1200,22 @@ pcie2: pcie@20000000 { "aux", "ahb"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie2_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie2_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0: pcie@28000000 { @@ -1267,12 +1297,22 @@ pcie0: pcie@28000000 { "aux", "ahb"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie0_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie0_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; nsscc: clock-controller@39b00000 { From 1290c03dc2d1e45928b427c616bc24a536e7601a Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:24 +0530 Subject: [PATCH 018/117] arm64: dts: qcom: ipq9574: enable the PCIe support on RDP454 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the PCIe0 (x1) and PCIe2 (x2) instances to connect QCN92xx Wi‑Fi cards. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-5-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 80 +++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts index f2334b9e0ed4..146422aede7d 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts @@ -18,3 +18,83 @@ / { &qpic_nand { status = "okay"; }; + +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + pinctrl-0 = <&pcie2_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; +}; + +&tlmm { + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio22"; + function = "pcie0_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio24"; + function = "pcie0_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins = "gpio28"; + function = "pcie2_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio30"; + function = "pcie2_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; From 95f827ceb21e2885f40eec5d93a340abbcc22d13 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 15 Jul 2026 18:31:30 +0530 Subject: [PATCH 019/117] arm64: dts: qcom: x1e80100: Add deepest idle state CPU subsystem deepest idle state can lead SoC to low power mode like CxPC (chip rail power collapse). SoC deepest low power mode requires the PDC interrupt controller to wake up the SoC as the GIC interrupt controller is on Cx (chip rail) and will not be functional to wake up the CPU. PDC monitors both direct SPI interrupts and GPIOs used as interrupts in SoC low power mode. Further all wake up capable interrupts gets routed via PDC to GIC when SoC is out of low power mode. The wake up capable GPIOs used as interrupts were by passing PDC on x1e with commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now") as a result CPU deepest idle state was not added so far. The blocker for enabling deepest idle state was GPIO IRQ wakeup support. The x1e80100 PDC can operate in two modes: pass-through mode (GPIO IRQs forwarded directly to GIC without latching at PDC) and secondary controller mode (PDC latches GPIO IRQs and sends them as level IRQs to GIC). All the SoCs on Linux so far worked in pass-through mode of PDC. On some x1e boards the firmware configures the PDC in secondary controller mode, which caused GPIO interrupt storms as the level latched at PDC gets never cleared. The secondary mode is originally a requirement for windows SW platforms (which could not work with all types of interrupts and require level interrupts for GPIOs). Initially shipped windows firmware did not have SCM interface to configure PDC back to pass-through mode if with such firmware Linux is booted up. PDC irqchip has got secondary mode and SCM interface support to configure PDC irqchip mode to pass-through mode on newer firmware where SCM interface is available and for older firmware on which SCM interface is not present PDC irqchip works in secondary irqchip mode [1]. Above mentioned commit is also reverted via [1]. With PDC now working on older firmware as well add the CPU deepest idle state domain_ss3. The newly added domain_ss3 state has entry/exit latencies of 2500 us. The shallower cluster_cl5 state had entry/exit latencies of 2200/4000 us which are higher than the deeper state. This create an inconsistency that would confuse the idle governor. Correct cluster_cl5 latencies to 2000 us each to match production configuration values. [1] https://lore.kernel.org/linux-arm-msm/20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com/#t Tested-by: Daniel J Blueman Signed-off-by: Maulik Shah Link: https://lore.kernel.org/r/20260715-hamoa_pdc_v3-v5-1-00440cfaf711@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 86168e445340..8a96ea1bdb9c 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -300,10 +300,18 @@ cluster_cl4: cluster-sleep-0 { cluster_cl5: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x01000054>; - entry-latency-us = <2200>; - exit-latency-us = <4000>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; min-residency-us = <7000>; }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2500>; + exit-latency-us = <2500>; + min-residency-us = <9000>; + }; }; }; @@ -462,7 +470,7 @@ cluster_pd2: power-domain-cpu-cluster2 { system_pd: power-domain-system { #power-domain-cells = <0>; - /* TODO: system-wide idle states */ + domain-idle-states = <&domain_ss3>; }; }; From a44338975cf80aa0aed629f5c6495aa18250897f Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Sat, 18 Jul 2026 15:21:25 +0000 Subject: [PATCH 020/117] arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add vbus-supply in Type-C connector VBUS supply property was moved from pmi632 typec node to USB-C connector. This fixes the following warning in kernel message. pmic@2:typec@1500: supply vdd-vbus not found, using dummy regulator Fixes: c1da9374c3e0 ("arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add PMI632 Type-C property") Signed-off-by: Biswapriyo Nath Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260718-ginkgo-vbus-typec-v1-1-d5ed0aa6b78b@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi index a5458ab41629..59042a593753 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -133,6 +133,8 @@ connector { typec-power-opmode = "default"; pd-disable; + vbus-supply = <&pmi632_vbus>; + port { pmi632_hs_in: endpoint { remote-endpoint = <&usb_dwc3_hs>; From 8ed8ee7499f2de55e3f63457936aaeb0ccbe0d72 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 21 Jul 2026 19:11:26 +0200 Subject: [PATCH 021/117] dt-bindings: arm: qcom: Add Asus Zenbook A16 (UX3607OA) UX3607OA is a variant of the Asus Zenbook A16 built on the Qualcomm Glymur platform. It comes with an 18-core X2 Elite Extreme SoC, 48GiB of RAM, NVMe storage, a 2880 x 1800 OLED screen, and the other typical Glymur platform capabilities. The hardware wiring is very different versus the 14" SKU. Add a compatible for this machine. [1] https://www.asus.com/us/laptops/for-home/zenbook/asus-zenbook-a16-ux3607/techspec/ Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260721-topic-a16_submission-v1-1-8ea213130d05@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f8c37096df46..f8ee354070d0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -86,6 +86,7 @@ properties: - items: - enum: + - asus,zenbook-a16-ux3607oa - qcom,glymur-crd - const: qcom,glymur From 1c2935b75f78fa74ef9cc37d95c4f734cbc0c15f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 23 Jul 2026 13:48:44 +0200 Subject: [PATCH 022/117] arm64: dts: monaco: Fix CSI I2C controllers default bus frequency 1 MHz is quite fast for an I2C bus and not necessarly reliable, change this to 400 KHz which is a more reasonable default. Signed-off-by: Hans de Goede Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260723114844.63093-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index a2daef463c3d..0e484b704fda 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5475,14 +5475,14 @@ cci0: cci@ac13000 { cci0_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci0_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5512,14 +5512,14 @@ cci1: cci@ac14000 { cci1_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci1_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5549,14 +5549,14 @@ cci2: cci@ac15000 { cci2_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci2_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; From e78c5e9d79e3c024e9b80ec067e62477c29aa29f Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 23 Jul 2026 23:02:25 +0530 Subject: [PATCH 023/117] arm64: dts: qcom: glymur: Fix properties of usb_hs node The High-speed only controller is DRD capable. Hence move the dr_mode property to platform DTS and mark the controller as role switch capable. While at it, since its high-speed only controller, disable pipe clock requirement. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260723-glymur-usb-fixes-v1-1-816357d5319c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 2 ++ arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 22f8011eb447..47fa3ae301ac 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -1208,6 +1208,8 @@ &usb_1_qmpphy_out { }; &usb_hs { + dr_mode = "host"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 72c23aef1207..e6dfd196bd52 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4838,10 +4838,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - dr_mode = "host"; - maximum-speed = "high-speed"; + qcom,select-utmi-as-pipe-clk; + usb-role-switch; + status = "disabled"; }; From 5ac32106d3c2ea94abd236fe3ad3897925640289 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 23 Jul 2026 23:02:26 +0530 Subject: [PATCH 024/117] arm64: dts: qcom: glymur: Configure USB controllers are wakeup-capable All USB controller on Glymur are wakeup-capable device. Add wakeup-source property for each of them indicating the same. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260723-glymur-usb-fixes-v1-2-816357d5319c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e6dfd196bd52..8708416451a4 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4603,6 +4603,7 @@ usb_0: usb@a600000 { snps,dis_enblslpm_quirk; usb-role-switch; + wakeup-source; status = "disabled"; @@ -4678,6 +4679,7 @@ usb_1: usb@a800000 { snps,dis_enblslpm_quirk; usb-role-switch; + wakeup-source; status = "disabled"; @@ -4753,6 +4755,7 @@ usb_2: usb@a000000 { snps,dis_enblslpm_quirk; usb-role-switch; + wakeup-source; status = "disabled"; @@ -4842,6 +4845,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,select-utmi-as-pipe-clk; usb-role-switch; + wakeup-source; status = "disabled"; }; @@ -4913,6 +4917,7 @@ usb_mp: usb@a400000 { snps,dis_enblslpm_quirk; dr_mode = "host"; + wakeup-source; status = "disabled"; }; From e418346f4eb314a4b11fc7eb46cf2b4825d15aee Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 28 Jul 2026 21:19:41 +0530 Subject: [PATCH 025/117] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Add macro definitions for virtual channels (combination of ADC channel number and PMIC SID number), to be used in devicetree by clients of ADC5 GEN3 device and in the "reg" property of ADC channels. Reviewed-by: Konrad Dybcio Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-1-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h new file mode 100644 index 000000000000..aa8e54d7e786 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__ +#define __DTS_ARM64_QCOM_ADC5_GEN3_H__ + +/* ADC channels for PMIC5 Gen3 */ + +#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan)) + +#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00) +#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01) +#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02) +#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03) + +#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04) +#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05) +#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06) +#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07) +#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08) +#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09) +#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a) +#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b) +#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c) +#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d) + +#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10) +#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11) +#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12) +#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15) +#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17) +#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18) +#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19) +#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b) +#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1) + +/* 30k pull-up */ +#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24) +#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25) +#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26) +#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27) +#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28) +#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29) +#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a) +#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b) +#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c) +#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d) + +/* 100k pull-up */ +#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44) +#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45) +#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46) +#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47) +#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48) +#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49) +#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a) +#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b) +#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c) +#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d) + +/* 400k pull-up */ +#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64) +#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65) +#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66) +#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67) +#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68) +#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69) +#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a) +#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b) +#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c) +#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d) + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a) +#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b) +#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c) +#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d) + +#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e) +#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f) + +#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94) +#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96) +#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d) + +#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */ From 4a118c175bdd93198961320111642c66693ed26c Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 28 Jul 2026 21:19:42 +0530 Subject: [PATCH 026/117] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through pmm8654au_3) on the Lemans platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Also add the io-channels and io-channel-names properties under the temp-alarm nodes so that they can get temperature reading from the ADC die_temp channels. Signed-off-by: Ayyagari Ushasreevalli Reviewed-by: Konrad Dybcio Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-2-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-pmics.dtsi | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi index 341119fc8244..500f715931aa 100644 --- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi @@ -5,6 +5,7 @@ #include #include +#include "qcom-adc5-gen3.h" / { thermal-zones { @@ -110,6 +111,8 @@ pmm8654au_0_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>; + io-channel-names = "thermal"; }; pmm8654au_0_pon: pon@1200 { @@ -141,6 +144,27 @@ pmm8654au_0_rtc: rtc@6100 { interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; + pmm8654au_0_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@3 { + reg = ; + label = "pmm8654au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@8e { + reg = ; + label = "pmm8654au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -176,6 +200,29 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; + }; + + pmm8654au_1_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@203 { + reg = ; + label = "pmm8654au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@28e { + reg = ; + label = "pmm8654au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_1_gpios: gpio@8800 { @@ -200,6 +247,29 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; + }; + + pmm8654au_2_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@403 { + reg = ; + label = "pmm8654au_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@48e { + reg = ; + label = "pmm8654au_2_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_2_gpios: gpio@8800 { @@ -224,6 +294,29 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; + }; + + pmm8654au_3_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@603 { + reg = ; + label = "pmm8654au_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@68e { + reg = ; + label = "pmm8654au_3_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_3_gpios: gpio@8800 { From 198bb8bf8b9053cad7dfc6553c46d112ae2a9a34 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 28 Jul 2026 21:19:43 +0530 Subject: [PATCH 027/117] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2) present on the Monaco platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Signed-off-by: Ayyagari Ushasreevalli Tested-by: Loic Poulain Reviewed-by: Konrad Dybcio Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-3-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-pmics.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi index e990d7367719..6e096b9b7546 100644 --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi @@ -5,6 +5,7 @@ #include #include +#include "qcom-adc5-gen3.h" &spmi_bus { pmm8620au_0: pmic@0 { @@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 { interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; + pmm8620au_0_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@3 { + reg = ; + label = "pmm8620au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@8e { + reg = ; + label = "pmm8620au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8620au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -37,6 +59,27 @@ pmm8650au_1: pmic@2 { #address-cells = <1>; #size-cells = <0>; + pmm8650au_1_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@203 { + reg = ; + label = "pmm8650au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@28e { + reg = ; + label = "pmm8650au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8650au_1_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From f969097d49663c1943b39c04f8e8b7c57bf8a456 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 28 Jul 2026 21:19:44 +0530 Subject: [PATCH 028/117] arm64: dts: qcom: hamoa-pmics: Add ADC support Add ADC node and define channels for: - Die temperature for PMK8550, PM8550VE* and PMC8380* PMICs. - PM8550: Die temperature, VPH power, and system thermistors. Add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the ADC die_temp channels. Remove die_temp channel of PMC8380_6 for Purwa boards where this PMIC is not present. Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-4-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 158 ++++++++++++++++++ arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 1 + .../dts/qcom/x1p42100-asus-vivobook-s15.dts | 1 + .../dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 1 + arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 1 + .../dts/qcom/x1p42100-hp-omnibook-x14.dts | 1 + .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 1 + 7 files changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 6a31a0adf8be..17d754d57e18 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -6,7 +6,9 @@ #include #include #include +#include #include +#include "qcom-adc5-gen3.h" / { thermal-zones { @@ -277,6 +279,134 @@ pmk8550_pwm: pwm { status = "disabled"; }; + + pmk8550_vadc: adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts-extended = <&spmi_bus0 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <&spmi_bus0 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>; + pinctrl-names = "default"; + + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_therm_2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@145 { + reg = ; + label = "pm8550_therm_3"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@146 { + reg = ; + label = "pm8550_therm_4"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@147 { + reg = ; + label = "pm8550_therm_5"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@148 { + reg = ; + label = "pm8550_therm_6"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@14a { + reg = ; + label = "pm8550_gpio_01"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@14b { + reg = ; + label = "pm8550_gpio_02"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@203 { + reg = ; + label = "pm8550ve_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@303 { + reg = ; + label = "pmc8380_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@403 { + reg = ; + label = "pmc8380_4_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@503 { + reg = ; + label = "pmc8380_5_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmc8380_6_die_temp: channel@603 { + reg = ; + label = "pmc8380_6_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@803 { + reg = ; + label = "pm8550ve_8_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@903 { + reg = ; + label = "pm8550ve_9_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; }; /* PMC8380C */ @@ -291,6 +421,8 @@ pm8550_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; }; pm8550_gpios: gpio@8800 { @@ -301,6 +433,18 @@ pm8550_gpios: gpio@8800 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + sys_therm_0_gpio3: sys-therm-0-gpio3-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + sys_therm_1_gpio4: sys-therm-1-gpio4-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; }; pm8550_flash: led-controller@ee00 { @@ -329,6 +473,8 @@ pm8550ve_2_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; }; pm8550ve_2_gpios: gpio@8800 { @@ -354,6 +500,8 @@ pmc8380_3_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; }; pmc8380_3_gpios: gpio@8800 { @@ -378,6 +526,8 @@ pmc8380_4_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; }; pmc8380_4_gpios: gpio@8800 { @@ -402,6 +552,8 @@ pmc8380_5_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(5)>; + io-channel-names = "thermal"; }; pmc8380_5_gpios: gpio@8800 { @@ -426,6 +578,8 @@ pmc8380_6_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; }; pmc8380_6_gpios: gpio@8800 { @@ -451,6 +605,8 @@ pm8550ve_8_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(8)>; + io-channel-names = "thermal"; }; pm8550ve_8_gpios: gpio@8800 { @@ -476,6 +632,8 @@ pm8550ve_9_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(9)>; + io-channel-names = "thermal"; }; pm8550ve_9_gpios: gpio@8800 { diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index ff8621f87505..fb2dcbc7c393 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -10,6 +10,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { reserved-memory { diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts index 63e29d2cc4ab..c754104adac7 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts @@ -11,6 +11,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "ASUS Vivobook S 15 X1P-42-100"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi index 7f5860d2b6cc..b5226c1ae370 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -11,6 +11,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { wcn6855-pmu { diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index 7ed4116b9590..5de91bca3fd5 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -10,6 +10,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "Qualcomm Technologies, Inc. X1P42100 CRD"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts index 0f338e457abd..0e4dfb0f0a2a 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -7,6 +7,7 @@ #include "x1-hp-omnibook-x14.dtsi" /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "HP Omnibook X 14-fe1"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 500809772097..9e6f679758a9 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -18,6 +18,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "Lenovo ThinkBook 16 Gen 7 QOY"; From da0343ba8c1f4275b1ce8127d5b6cee24d988868 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:24 +0200 Subject: [PATCH 029/117] arm64: dts: qcom: pmk8550: add VADC node Add the VADC node and the initial pmk8550 adc channels. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-1-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 3049eb6b46d7..3a9d9f7c3742 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "qcom-adc5-gen3.h" / { reboot-mode { @@ -64,6 +65,35 @@ reboot_reason: reboot-reason@48 { }; }; + pmk8550_vadc: adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts-extended = <&spmi_bus 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <&spmi_bus 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + channel@0 { + reg = ; + label = "pmk8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "pmk8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + pmk8550_gpios: gpio@b800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; From c50667eab2d6482f6397c00735d429428e2b3c81 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:25 +0200 Subject: [PATCH 030/117] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-2-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index f2effa55d819..144e105b734f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -205,6 +205,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -995,27 +1081,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &pon_pwrkey { status = "okay"; }; From 972848c36912ec8cbe79d68e5b2875a889375ebf Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:26 +0200 Subject: [PATCH 031/117] arm64: dts: qcom: sm8550-hdk: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-3-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index b79558938552..58c71ac67da5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -280,6 +280,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + wcn7850-pmu { compatible = "qcom,wcn7850-pmu"; @@ -1100,27 +1186,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &pon_pwrkey { status = "okay"; }; From b857a25ce399b9f49a2152d78d1a3893751e7cc4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:27 +0200 Subject: [PATCH 032/117] arm64: dts: qcom: sm8650-qrd: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-4-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index a28d70c85fa3..5709cfea1bfd 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -158,6 +158,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -1039,27 +1125,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; From 09d35331b7a94e30e30afb36b37a98513a2f60f7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:28 +0200 Subject: [PATCH 033/117] arm64: dts: qcom: sm8650-hdk: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-5-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 80bd2437f154..71c0355ece4b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -220,6 +220,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -1040,27 +1126,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &pon_pwrkey { status = "okay"; }; From b3938d240803b2b114f19f8375493033376d5dba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 30 Jul 2026 11:23:57 +0200 Subject: [PATCH 034/117] arm64: dts: qcom: eliza-cqs-som: Add eUSB2 repeater supplies Hardware works better when it's powered. Wire up the associated regulators. Fixes: 85a1eb421dfa ("arm64: dts: qcom: eliza: Add Eliza CQS SoM platform") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260730-topic-eliza_som_eusb2-v1-1-288bcda1fee2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi index 318ae3c22351..5ef6c51618bf 100644 --- a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi @@ -369,6 +369,11 @@ vreg_l7k: ldo7 { }; }; +&pm7550ba_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; +}; + &remoteproc_adsp { firmware-name = "qcom/eliza/adsp.mbn", "qcom/eliza/adsp_dtb.mbn"; From 1b0b6ddd0299efa29d18f68a2d7152ad67cb9576 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Jul 2026 16:08:32 +0200 Subject: [PATCH 035/117] arm64: dts: qcom: glymur: Fix PDC IRQ mapping Some of the sub-ranges are inconsistent with HW docs. Fix them. They are valid for both Glymur and Mahua. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Gopikrishna Garmidi Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260729-topic-glymur_pdc-v1-1-8747789e35aa@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 8708416451a4..400ad218a459 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5428,9 +5428,13 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,glymur-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>; - qcom,pdc-ranges = <0 745 51>, - <51 527 47>, - <98 609 32>, + qcom,pdc-ranges = <0 745 38>, + <40 785 11>, + <51 527 4>, + <57 533 10>, + <70 546 4>, + <75 551 18>, + <108 619 22>, <130 717 12>, <142 251 5>, <147 796 16>, From f2eb18c66b98fbfcbab4daef42c04f4becba7d79 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 30 Jul 2026 15:45:10 +0530 Subject: [PATCH 036/117] arm64: dts: qcom: talos: Fix cpu6 1094.4MHz OPP frequency typo opp-1094400000 in cpu6_opp_table has a typo in opp-hz, missing a trailing zero. Fix it to resolve the following OPP update failures: cpu cpu6: Voltage update failed freq=1094400 cpu cpu6: failed to update OPP for freq=1094400 Fixes: 44562f591890 ("arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260730-talos-cpu6-opp-fix-v1-1-f4886fdff13f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index bdfb70ca9740..bef3e2e5fcdc 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -352,7 +352,7 @@ opp-1017600000 { }; opp-1094400000 { - opp-hz = /bits/ 64 <109440000>; + opp-hz = /bits/ 64 <1094400000>; opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; }; From 299731d4fbeaaa141ce2e8226ca00cb30d6ab647 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dawid=20Wro=CC=81bel?= Date: Thu, 30 Jul 2026 15:44:07 +0200 Subject: [PATCH 037/117] arm64: dts: qcom: sm8250-xiaomi-elish: correct the board ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit elish declares the same qcom,msm-id and qcom,board-id pair as sm8250-sony-xperia-edo.dtsi, so a bootloader choosing between appended device trees cannot tell the two boards apart. 0x10008 is Sony's value. The downstream device tree for this board, elish-sm8250-overlay.dts, uses qcom,board-id = <47 0>, i.e. platform type 0x2f. Fixes: a41b617530bf ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro") Signed-off-by: Dawid Wróbel Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-elish-board-id-v1-1-92f99e9722ec@dawidwrobel.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 19aff83ecf7b..945127dacc82 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -29,7 +29,7 @@ / { /* required for bootloader to select correct board */ qcom,msm-id = ; /* SM8250 v2.1 */ - qcom,board-id = <0x10008 0>; + qcom,board-id = <0x2f 0>; aliases { serial0 = &uart6; From 35eda0e5f87d52ed9f015f8a44155e8ab2ad9c5a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:42 +0200 Subject: [PATCH 038/117] arm64: dts: qcom: kaanapali: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-1-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 74699bc3eadb..128d46a39e22 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2385,8 +2385,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, operating-points-v2 = <&pcie0_opp_table>; - iommu-map = <0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, From 52dac5bda29a3acd896fab2567605683d34970db Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:43 +0200 Subject: [PATCH 039/117] arm64: dts: qcom: kodiak: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: f8328b7549e1 ("arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-2-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 7e73348fe0d0..f74fa66f1a67 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2281,8 +2281,8 @@ pcie0: pcie@1c00000 { "aggre0", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2423,8 +2423,8 @@ pcie1: pcie@1c08000 { dma-coherent; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; status = "disabled"; From f605087abc70ecac53757a7ae0d2d8068342ec4b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:44 +0200 Subject: [PATCH 040/117] arm64: dts: qcom: sar2130p: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: be9115bfe5bf ("arm64: dts: qcom: sar2130p: add support for SAR2130P") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-3-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 767f7cc218f1..a2d93fd68299 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1329,8 +1329,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1455,8 +1455,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>, + <0x100 &apps_smmu 0x1e01 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From a4548204821a56c23cd711cfad2a637ca055ff47 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:45 +0200 Subject: [PATCH 041/117] arm64: dts: qcom: sc8180x: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-4-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b532e33a2639..de1b72b64d96 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1767,8 +1767,8 @@ pcie0: pcie@1c00000 { assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, - <0x100 &apps_smmu 0x1d81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x0 0x1>, + <0x100 &apps_smmu 0x1d81 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1886,8 +1886,8 @@ pcie3: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>, + <0x100 &apps_smmu 0x1e01 0x0 0x1>; resets = <&gcc GCC_PCIE_3_BCR>; reset-names = "pci"; @@ -2006,8 +2006,8 @@ pcie1: pcie@1c10000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; @@ -2126,8 +2126,8 @@ pcie2: pcie@1c18000 { assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, - <0x100 &apps_smmu 0x1d01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x0 0x1>, + <0x100 &apps_smmu 0x1d01 0x0 0x1>; resets = <&gcc GCC_PCIE_2_BCR>; reset-names = "pci"; From deaea7e982bc353c8d3c406774970f16ed901adb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:46 +0200 Subject: [PATCH 042/117] arm64: dts: qcom: sdm845: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-5-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 64 ++++++++++++++-------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 745ca60fc8ed..562d411ed256 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2372,22 +2372,22 @@ pcie0: pcie@1c00000 { "slave_q2a", "tbu"; - iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, - <0x100 &apps_smmu 0x1c11 0x1>, - <0x200 &apps_smmu 0x1c12 0x1>, - <0x300 &apps_smmu 0x1c13 0x1>, - <0x400 &apps_smmu 0x1c14 0x1>, - <0x500 &apps_smmu 0x1c15 0x1>, - <0x600 &apps_smmu 0x1c16 0x1>, - <0x700 &apps_smmu 0x1c17 0x1>, - <0x800 &apps_smmu 0x1c18 0x1>, - <0x900 &apps_smmu 0x1c19 0x1>, - <0xa00 &apps_smmu 0x1c1a 0x1>, - <0xb00 &apps_smmu 0x1c1b 0x1>, - <0xc00 &apps_smmu 0x1c1c 0x1>, - <0xd00 &apps_smmu 0x1c1d 0x1>, - <0xe00 &apps_smmu 0x1c1e 0x1>, - <0xf00 &apps_smmu 0x1c1f 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c10 0x0 0x1>, + <0x100 &apps_smmu 0x1c11 0x0 0x1>, + <0x200 &apps_smmu 0x1c12 0x0 0x1>, + <0x300 &apps_smmu 0x1c13 0x0 0x1>, + <0x400 &apps_smmu 0x1c14 0x0 0x1>, + <0x500 &apps_smmu 0x1c15 0x0 0x1>, + <0x600 &apps_smmu 0x1c16 0x0 0x1>, + <0x700 &apps_smmu 0x1c17 0x0 0x1>, + <0x800 &apps_smmu 0x1c18 0x0 0x1>, + <0x900 &apps_smmu 0x1c19 0x0 0x1>, + <0xa00 &apps_smmu 0x1c1a 0x0 0x1>, + <0xb00 &apps_smmu 0x1c1b 0x0 0x1>, + <0xc00 &apps_smmu 0x1c1c 0x0 0x1>, + <0xd00 &apps_smmu 0x1c1d 0x0 0x1>, + <0xe00 &apps_smmu 0x1c1e 0x0 0x1>, + <0xf00 &apps_smmu 0x1c1f 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2502,22 +2502,22 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>, - <0x200 &apps_smmu 0x1c02 0x1>, - <0x300 &apps_smmu 0x1c03 0x1>, - <0x400 &apps_smmu 0x1c04 0x1>, - <0x500 &apps_smmu 0x1c05 0x1>, - <0x600 &apps_smmu 0x1c06 0x1>, - <0x700 &apps_smmu 0x1c07 0x1>, - <0x800 &apps_smmu 0x1c08 0x1>, - <0x900 &apps_smmu 0x1c09 0x1>, - <0xa00 &apps_smmu 0x1c0a 0x1>, - <0xb00 &apps_smmu 0x1c0b 0x1>, - <0xc00 &apps_smmu 0x1c0c 0x1>, - <0xd00 &apps_smmu 0x1c0d 0x1>, - <0xe00 &apps_smmu 0x1c0e 0x1>, - <0xf00 &apps_smmu 0x1c0f 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>, + <0x200 &apps_smmu 0x1c02 0x0 0x1>, + <0x300 &apps_smmu 0x1c03 0x0 0x1>, + <0x400 &apps_smmu 0x1c04 0x0 0x1>, + <0x500 &apps_smmu 0x1c05 0x0 0x1>, + <0x600 &apps_smmu 0x1c06 0x0 0x1>, + <0x700 &apps_smmu 0x1c07 0x0 0x1>, + <0x800 &apps_smmu 0x1c08 0x0 0x1>, + <0x900 &apps_smmu 0x1c09 0x0 0x1>, + <0xa00 &apps_smmu 0x1c0a 0x0 0x1>, + <0xb00 &apps_smmu 0x1c0b 0x0 0x1>, + <0xc00 &apps_smmu 0x1c0c 0x0 0x1>, + <0xd00 &apps_smmu 0x1c0d 0x0 0x1>, + <0xe00 &apps_smmu 0x1c0e 0x0 0x1>, + <0xf00 &apps_smmu 0x1c0f 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From d2e56fb42e3d10d7e711063cdc00523ddb31d544 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:47 +0200 Subject: [PATCH 043/117] arm64: dts: qcom: sm8150: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-6-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 661848ef5eee..94a3b02cb289 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1893,8 +1893,8 @@ pcie0: pcie@1c00000 { "bus_slave", "slave_q2a"; - iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, - <0x100 &apps_smmu 0x1d81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x0 0x1>, + <0x100 &apps_smmu 0x1d81 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2011,8 +2011,8 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>, + <0x100 &apps_smmu 0x1e01 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From c41749e9554d4e03e7074f5d1e46140bc4ac77bd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:48 +0200 Subject: [PATCH 044/117] arm64: dts: qcom: sm8250: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-7-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f11da2ca4181..90f8b091634e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2199,8 +2199,8 @@ pcie0: pcie@1c00000 { "tbu", "ddrss_sf_tbu"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2326,8 +2326,8 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; @@ -2453,8 +2453,8 @@ pcie2: pcie@1c10000 { assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, - <0x100 &apps_smmu 0x1d01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x0 0x1>, + <0x100 &apps_smmu 0x1d01 0x0 0x1>; resets = <&gcc GCC_PCIE_2_BCR>; reset-names = "pci"; From 80337ea3a154230621c0b4e3c831f5d81712ba18 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:49 +0200 Subject: [PATCH 045/117] arm64: dts: qcom: sm8350: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-8-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 72ecfaeefdd3..524693ec31c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1577,8 +1577,8 @@ pcie0: pcie@1c00000 { "aggre1", "aggre0"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1686,8 +1686,8 @@ pcie1: pcie@1c08000 { "ddrss_sf_tbu", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From 9b10e56647fa8f7ab62c7e45ebf4b168f7befa7f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:50 +0200 Subject: [PATCH 046/117] arm64: dts: qcom: sm8450: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 7b09b1b47335 ("arm64: dts: qcom: sm8450: add PCIe0 RC device") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-9-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2488928656d9..c3e22f6a69e4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2008,8 +2008,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "aggre0", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2173,8 +2173,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "ddrss_sf_tbu", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From 16d98ee918d63018eaa6cc260791b71319aa4faa Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:51 +0200 Subject: [PATCH 047/117] arm64: dts: qcom: sm8550: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-10-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7599b7b7e645..2888ec109ef7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2388,8 +2388,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, msi-map = <0x0 &gic_its 0x1400 0x1>, <0x100 &gic_its 0x1401 0x1>; - iommu-map = <0x0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0x0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2573,8 +2573,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, msi-map = <0x0 &gic_its 0x1480 0x1>, <0x100 &gic_its 0x1481 0x1>; - iommu-map = <0x0 &apps_smmu 0x1480 0x1>, - <0x100 &apps_smmu 0x1481 0x1>; + iommu-map = <0x0 &apps_smmu 0x1480 0x0 0x1>, + <0x100 &apps_smmu 0x1481 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From 8ccba7b44609d58db088447a771f6f30cfa8739e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:52 +0200 Subject: [PATCH 048/117] arm64: dts: qcom: sm8650: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-11-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index d9b2c88a130a..799d549a9019 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3682,8 +3682,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, operating-points-v2 = <&pcie0_opp_table>; - iommu-map = <0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, @@ -3875,8 +3875,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, operating-points-v2 = <&pcie1_opp_table>; - iommu-map = <0 &apps_smmu 0x1480 0x1>, - <0x100 &apps_smmu 0x1481 0x1>; + iommu-map = <0 &apps_smmu 0x1480 0x0 0x1>, + <0x100 &apps_smmu 0x1481 0x0 0x1>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, From 366a540432a38c1c1533a319bc07b333f53752b6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:53 +0200 Subject: [PATCH 049/117] arm64: dts: qcom: sm8750: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 19f1395333f8 ("arm64: dts: qcom: sm8750: Add PCIe PHY and controller node") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-12-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3496f00ac4f5..dd738d13df8e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5516,8 +5516,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0x0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; From f7e687d6050f27a03847abadc12d6821576d06ee Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:54 +0200 Subject: [PATCH 050/117] arm64: dts: qcom: talos: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 718cc7542a00 ("arm64: dts: qcom: qcs615: enable pcie") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-13-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index bef3e2e5fcdc..07ba5733ca92 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1358,8 +1358,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x400 0x1>, - <0x100 &apps_smmu 0x401 0x1>; + iommu-map = <0x0 &apps_smmu 0x400 0x0 0x1>, + <0x100 &apps_smmu 0x401 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; From 19b4c47fc9733a953e9586bc0906a3be378b4cd5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:55 +0200 Subject: [PATCH 051/117] arm64: dts: qcom: lemans: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-14-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 3b0539e27b51..17bc5bcd9d09 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2742,8 +2742,8 @@ pcie0: pcie@1c00000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; @@ -2916,8 +2916,8 @@ pcie1: pcie@1c10000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, + <0x100 &pcie_smmu 0x0081 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From 2e455d9278550c8886a94e30a906437a26c79581 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:56 +0200 Subject: [PATCH 052/117] arm64: dts: qcom: monaco: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 46a7c01e7e9d ("arm64: dts: qcom: qcs8300: enable pcie0") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-15-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 0e484b704fda..d839f3683535 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2329,8 +2329,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; @@ -2506,8 +2506,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, + <0x100 &pcie_smmu 0x0081 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From d7ae79013e6c9b2374948d70856045cc84c9261d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:57 +0200 Subject: [PATCH 053/117] arm64: dts: qcom: monaco-monza-som: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5238f4e7169f ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-16-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi index 9b5ed55939b8..36af1ad2105d 100644 --- a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -196,14 +196,14 @@ &iris { /* PCIe0 Gen4 x2 */ &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>, - <0x200 &pcie_smmu 0x0007 0x1>, - <0x208 &pcie_smmu 0x0002 0x1>, - <0x210 &pcie_smmu 0x0003 0x1>, - <0x218 &pcie_smmu 0x0004 0x1>, - <0x300 &pcie_smmu 0x0005 0x1>, - <0x400 &pcie_smmu 0x0006 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>, + <0x200 &pcie_smmu 0x0007 0x0 0x1>, + <0x208 &pcie_smmu 0x0002 0x0 0x1>, + <0x210 &pcie_smmu 0x0003 0x0 0x1>, + <0x218 &pcie_smmu 0x0004 0x0 0x1>, + <0x300 &pcie_smmu 0x0005 0x0 0x1>, + <0x400 &pcie_smmu 0x0006 0x0 0x1>; status = "okay"; }; From b35b58535b45441a4521d50215b5668731857c7d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:58 +0200 Subject: [PATCH 054/117] arm64: dts: qcom: monaco-evk-ifp-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5a67924d2fc5 ("arm64: dts: qcom: monaco-evk: Add IFP Mezzanine") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-17-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/monaco-evk-ifp-mezzanine.dtso | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index 77c28c19d17a..ca5bf0fe5ec6 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -50,15 +50,15 @@ nvmem-layout { }; &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0 0x1>, - <0x100 &pcie_smmu 0x1 0x1>, - <0x208 &pcie_smmu 0x2 0x1>, - <0x210 &pcie_smmu 0x3 0x1>, - <0x218 &pcie_smmu 0x4 0x1>, - <0x300 &pcie_smmu 0x5 0x1>, - <0x400 &pcie_smmu 0x6 0x1>, - <0x500 &pcie_smmu 0x7 0x1>, - <0x501 &pcie_smmu 0x8 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x0 0x1>, + <0x208 &pcie_smmu 0x2 0x0 0x1>, + <0x210 &pcie_smmu 0x3 0x0 0x1>, + <0x218 &pcie_smmu 0x4 0x0 0x1>, + <0x300 &pcie_smmu 0x5 0x0 0x1>, + <0x400 &pcie_smmu 0x6 0x0 0x1>, + <0x500 &pcie_smmu 0x7 0x0 0x1>, + <0x501 &pcie_smmu 0x8 0x0 0x1>; }; &pcieport0 { From 6ee8ab6ca91dcea05793809df8a1dcfa94bcf3f0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:59 +0200 Subject: [PATCH 055/117] arm64: dts: qcom: lemans-evk-ifp-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: b64abb26a291 ("arm64: dts: qcom: lemans-evk: Add IFP Mezzanine") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-18-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 4fc5f482a18f..6cfa0bc1440e 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -204,15 +204,15 @@ &mdss1_dp1_phy { }; &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0 0x1>, - <0x100 &pcie_smmu 0x1 0x1>, - <0x208 &pcie_smmu 0x2 0x1>, - <0x210 &pcie_smmu 0x3 0x1>, - <0x218 &pcie_smmu 0x4 0x1>, - <0x300 &pcie_smmu 0x5 0x1>, - <0x400 &pcie_smmu 0x6 0x1>, - <0x500 &pcie_smmu 0x7 0x1>, - <0x501 &pcie_smmu 0x8 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x0 0x1>, + <0x208 &pcie_smmu 0x2 0x0 0x1>, + <0x210 &pcie_smmu 0x3 0x0 0x1>, + <0x218 &pcie_smmu 0x4 0x0 0x1>, + <0x300 &pcie_smmu 0x5 0x0 0x1>, + <0x400 &pcie_smmu 0x6 0x0 0x1>, + <0x500 &pcie_smmu 0x7 0x0 0x1>, + <0x501 &pcie_smmu 0x8 0x0 0x1>; }; &pcieport0 { From 82a10eb6aeab412abd83a57cc3a605213d1dc1d5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:00 +0200 Subject: [PATCH 056/117] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: ef254b12ec60 ("arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-19-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 82ebd88f9aba..41d60c87f5bd 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -549,15 +549,15 @@ &pcie1 { pinctrl-names = "default"; /* Support for QPS615 PCIe switch */ - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x400 &apps_smmu 0x1c88 0x1>, - <0x500 &apps_smmu 0x1c89 0x1>, - <0x501 &apps_smmu 0x1c90 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x400 &apps_smmu 0x1c88 0x0 0x1>, + <0x500 &apps_smmu 0x1c89 0x0 0x1>, + <0x501 &apps_smmu 0x1c90 0x0 0x1>; status = "okay"; }; From fc3c550b3847636f6c0732dc6c94e879ab5ff578 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:01 +0200 Subject: [PATCH 057/117] arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 1cde54c54b83 ("arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-20-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 4f6932dd1139..172dc0cbb532 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -714,15 +714,15 @@ &pcie1 { <&pcie1_wake_n>; pinctrl-names = "default"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x400 &apps_smmu 0x1c88 0x1>, - <0x500 &apps_smmu 0x1c89 0x1>, - <0x501 &apps_smmu 0x1c90 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x400 &apps_smmu 0x1c88 0x0 0x1>, + <0x500 &apps_smmu 0x1c89 0x0 0x1>, + <0x501 &apps_smmu 0x1c90 0x0 0x1>; status = "okay"; }; From 485dc5e557a8fef1374669f4ebe027c947187325 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:02 +0200 Subject: [PATCH 058/117] arm64: dts: qcom: qcs6490-rb3gen2: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 267643b3e3a4 ("arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-21-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 1acbfe7baa13..90f2eebc349f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -844,15 +844,15 @@ &pcie1 { pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x400 &apps_smmu 0x1c88 0x1>, - <0x500 &apps_smmu 0x1c89 0x1>, - <0x501 &apps_smmu 0x1c90 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x400 &apps_smmu 0x1c88 0x0 0x1>, + <0x500 &apps_smmu 0x1c89 0x0 0x1>, + <0x501 &apps_smmu 0x1c90 0x0 0x1>; status = "okay"; }; From 770d1448435bca2b1cd00854dc9401320b584d5b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:03 +0200 Subject: [PATCH 059/117] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 4559b435f741 ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-22-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 937b63eae3ba..46bb52c667a4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -54,15 +54,15 @@ &pcie0 { pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>, - <0x208 &apps_smmu 0x1c04 0x1>, - <0x210 &apps_smmu 0x1c05 0x1>, - <0x218 &apps_smmu 0x1c06 0x1>, - <0x300 &apps_smmu 0x1c07 0x1>, - <0x400 &apps_smmu 0x1c08 0x1>, - <0x500 &apps_smmu 0x1c09 0x1>, - <0x501 &apps_smmu 0x1c10 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>, + <0x208 &apps_smmu 0x1c04 0x0 0x1>, + <0x210 &apps_smmu 0x1c05 0x0 0x1>, + <0x218 &apps_smmu 0x1c06 0x0 0x1>, + <0x300 &apps_smmu 0x1c07 0x0 0x1>, + <0x400 &apps_smmu 0x1c08 0x0 0x1>, + <0x500 &apps_smmu 0x1c09 0x0 0x1>, + <0x501 &apps_smmu 0x1c10 0x0 0x1>; status = "okay"; }; @@ -151,22 +151,22 @@ pcie@0,1 { }; &pcie1 { - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x408 &apps_smmu 0x1c90 0x1>, - <0x410 &apps_smmu 0x1c91 0x1>, - <0x418 &apps_smmu 0x1c92 0x1>, - <0x500 &apps_smmu 0x1c93 0x1>, - <0x600 &apps_smmu 0x1c94 0x1>, - <0x700 &apps_smmu 0x1c95 0x1>, - <0x701 &apps_smmu 0x1c96 0x1>, - <0x800 &apps_smmu 0x1c97 0x1>, - <0x900 &apps_smmu 0x1c98 0x1>, - <0x901 &apps_smmu 0x1c99 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x408 &apps_smmu 0x1c90 0x0 0x1>, + <0x410 &apps_smmu 0x1c91 0x0 0x1>, + <0x418 &apps_smmu 0x1c92 0x0 0x1>, + <0x500 &apps_smmu 0x1c93 0x0 0x1>, + <0x600 &apps_smmu 0x1c94 0x0 0x1>, + <0x700 &apps_smmu 0x1c95 0x0 0x1>, + <0x701 &apps_smmu 0x1c96 0x0 0x1>, + <0x800 &apps_smmu 0x1c97 0x0 0x1>, + <0x900 &apps_smmu 0x1c98 0x0 0x1>, + <0x901 &apps_smmu 0x1c99 0x0 0x1>; }; &pcie1_switch0_dsp1 { From e8fbbca94db752ab94d9dadf2f65872905eafecd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 21 Jul 2026 19:11:27 +0200 Subject: [PATCH 060/117] arm64: dts: qcom: glymur: Add Asus Zenbook A16 (UX3607OA) UX3607OA is a variant of the Asus Zenbook A16 built on the Qualcomm Glymur platform. It comes with an 18-core X2 Elite Extreme SoC, 48GiB of RAM, NVMe storage, a 2880 x 1800 OLED screen, and the other typical Glymur platform capabilities. The hardware wiring is very different versus the 14" SKU - the larger one is based on the System-In-Package reference design, unlike the smaller one, which derives from a more common Chip-On-Board base. Currently working: - Audio playback (4 speakers) - GPU, Display - HDMI port - Keyboard, touchpad, lid switch - Privacy LEDs (camera-use, camera-block, mic-mute) - Charging, Type-C, Type-A port - Onboard SD Card slot (RTS5329) - Wi-Fi, Bluetooth (QCC2072) - Touchscreen should work on the SKUs that have it, but it remains untested due to lack of access to such a device Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260721-topic-a16_submission-v1-2-8ea213130d05@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/glymur-asus-zenbook-a16-ux3607oa.dts | 1269 +++++++++++++++++ arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 2 +- 4 files changed, 1272 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e05414290d8e..1c86e7e98f55 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a16-ux3607oa.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts new file mode 100644 index 000000000000..939e1a927a79 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts @@ -0,0 +1,1269 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "glymur.dtsi" + +#include "pmcx0102.dtsi" +#include "pmh0101.dtsi" +#include "pmh0110-glymur.dtsi" +#include "pmh0104-glymur.dtsi" +#include "pmk8850.dtsi" +#include "smb2370.dtsi" + +#include +#include +#include +#include + +/delete-node/ &pmh0104_l_e1; +/delete-node/ &pmh0104_l1_thermal; +/delete-node/ &pmh0110_h_e0; +/delete-node/ &pmh0110_h0_thermal; + +/ { + compatible = "asus,zenbook-a16-ux3607oa", "qcom,glymur"; + model = "ASUS Zenbook A16 (UX3607OA)"; + + aliases { + i2c0 = &i2c0; + i2c5 = &i2c5; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c13 = &i2c13; + i2c19 = &i2c19; + + serial0 = &uart21; + serial1 = &uart14; + }; + + chosen { + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&usb2_dp_hot_plug_detect>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&usb_2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>, + <&keyboard_cam_led>, + <&keyboard_mic_led>; + pinctrl-names = "default"; + + keyboard-camera-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + keyboard-mic-led { + function = LED_FUNCTION_MICMUTE; + color = ; + gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + default-state = "off"; + panic-indicator; + }; + + privacy-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 111 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + /* Left side display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + /* Left side user-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp: regulator-edp { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_pwr_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-ASUS-Zenbook-A16-UX3607OA"; + + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wlan-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; + vpcie1v8-supply = <&vreg_l15b_e0>; + + w-disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie4_port0_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart14_ep>; + }; + }; + }; + }; +}; + +&apps_rsc { + /* PMCX0104 */ + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_l1b_e0: ldo1 { + regulator-name = "vreg_l1b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + /* Unused */ + vreg_l2b_e0: ldo2 { + regulator-name = "vreg_l2b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l6b_e0: ldo6 { + regulator-name = "vreg_l6b_e0"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l7b_e0: ldo7 { + regulator-name = "vreg_l7b_e0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l8b_e0: ldo8 { + regulator-name = "vreg_l8b_e0"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + /* Unused */ + vreg_l9b_e0: ldo9 { + regulator-name = "vreg_l9b_e0"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10b_e0: ldo10 { + regulator-name = "vreg_l10b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b_e0: ldo11 { + regulator-name = "vreg_l11b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + /* Unused */ + vreg_l12b_e0: ldo12 { + regulator-name = "vreg_l12b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l15b_e0: ldo15 { + regulator-name = "vreg_l15b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + /* Provides reference voltage for many undescribed components */ + regulator-always-on; + }; + + /* Unused */ + vreg_l17b_e0: ldo17 { + regulator-name = "vreg_l17b_e0"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + }; + + vreg_l18b_e0: ldo18 { + regulator-name = "vreg_l18b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + + /* Provides reference voltage for many undescribed components */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E0"; + + vreg_l1c_e0: ldo1 { + regulator-name = "vreg_l1c_e0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e0: ldo2 { + regulator-name = "vreg_l2c_e0"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e0: ldo4 { + regulator-name = "vreg_l4c_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* PMCX0101 */ + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0: smps7 { + regulator-name = "vreg_s7f_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s8f_e0: smps8 { + regulator-name = "vreg_s8f_e0"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e0: ldo2 { + regulator-name = "vreg_l2f_e0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + }; + + vreg_l3f_e0: ldo3 { + regulator-name = "vreg_l3f_e0"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1: ldo1 { + regulator-name = "vreg_l1c_e1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e1: ldo2 { + regulator-name = "vreg_l2c_e1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3c_e1: ldo3 { + regulator-name = "vreg_l3c_e1"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e1: ldo4 { + regulator-name = "vreg_l4c_e1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + /* PMCX0101 */ + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_l1f_e1: ldo1 { + regulator-name = "vreg_l1f_e1"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e1: ldo2 { + regulator-name = "vreg_l2f_e1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e1: ldo4 { + regulator-name = "vreg_l4f_e1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + /* 2808:0219 */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_1: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0>; + vdd1v8-supply = <&vreg_l15b_e0>; + + #phy-cells = <0>; + }; + + ptn3222_0: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0>; + vdd1v8-supply = <&vreg_l15b_e0>; + + #phy-cells = <0>; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + /* EC subdevice @ 0x5b */ + /* EC @ 0x76 */ +}; + +&i2c10 { + clock-frequency = <400000>; + + status = "okay"; + + /* ASUSTek 0B05:4543 */ + hid@17 { + compatible = "hid-over-i2c"; + reg = <0x17>; + interrupts-extended = <&tlmm 43 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x1>; + wakeup-source; + + pinctrl-0 = <&hid_int_a_default>; + pinctrl-names = "default"; + }; +}; + +&i2c13 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c19 { + clock-frequency = <400000>; + + status = "okay"; + + /* ASUSTek 0B05:4B42 */ + keyboard@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + }; +}; + +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&lpass_vamacro { + vdd-micb-supply = <&vreg_l1b_e0>; + + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie4_port0_ep { + remote-endpoint = <&m2_e_pcie_ep>; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmk8850_rtc { + qcom,uefi-rtc-info; + qcom,no-alarm; +}; + +&remoteproc_adsp { + firmware-name = "qcom/glymur/ASUSTeK/UX3607OA/qcadsp8480.mbn", + "qcom/glymur/ASUSTeK/UX3607OA/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/ASUSTeK/UX3607OA/qccdsp8480.mbn", + "qcom/glymur/ASUSTeK/UX3607OA/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_soccp { + firmware-name = "qcom/glymur/ASUSTeK/UX3607OA/soccp.mbn", + "qcom/glymur/ASUSTeK/UX3607OA/soccp_dtb.mbn"; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, left woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, left tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, right woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, right tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2c_e0>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2c_e0>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx4-0p9-supply = <&vreg_l2c_e0>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0>; + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0>; + vdda-qreftx0-1p2-supply = <&vreg_l4c_e0>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1>; + vdda-refgen3-0p9-supply = <&vreg_l2f_e0>; + vdda-refgen3-1p2-supply = <&vreg_l4c_e0>; + vdda-refgen4-0p9-supply = <&vreg_l1f_e1>; + vdda-refgen4-1p2-supply = <&vreg_l4f_e1>; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>, /* TPM */ + <65 1>, /* EC reset */ + <90 1>; /* TPM */ + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hid_int_a_default: hid-int-a-default-state { + pins = "gpio43"; + function = "gpio"; + bias-disable; + }; + + ts_default: ts-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + bias-disable; + }; + + int-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + edp_pwr_en: edp-pwr-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + keyboard_mic_led: keyboard-mic-led-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp0_hpd_default: edp0-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + + keyboard_cam_led: keyboard-cam-led-state { + pins = "gpio120"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_dp_hot_plug_detect: usb2-dp-hot-plug-detect-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&uart14 { + status = "okay"; + + port { + uart14_ep: endpoint { + remote-endpoint = <&m2_e_uart_ep>; + }; + }; +}; + +&uart21 { + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l3f_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l2f_e0>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l2f_e0>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vreg_l4c_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + refgen-supply = <&vreg_l4f_e1>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_in>; + }; + }; + }; +}; + +&usb_mp { + status = "okay"; +}; + +/* MP0 (eUSB3 + USBSS3) -> Type-A port */ +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2c_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +/* MP1 (eUSB6 + USBSS4) -> RTS5329 SD Card reader */ +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2c_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l2c_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l2c_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi index 6b4747025b9f..30e2d8caa0ed 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; - pmh0104-l1-thermal { + pmh0104_l1_thermal: pmh0104-l1-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0104_l_e1_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi index 7655bc030348..c2d0b9597818 100644 --- a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; - pmh0110-h0-thermal { + pmh0110_h0_thermal: pmh0110-h0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0110_h_e0_temp_alarm>; From d01693e992b8faebe61612208096e5937684aaf2 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:17 +0530 Subject: [PATCH 061/117] arm64: dts: qcom: kaanapali: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-7-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 128d46a39e22..131fd2a16c54 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -224,6 +224,7 @@ scm: scm { qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + sram = <&minidump_config>; }; scmi: scmi { @@ -5586,6 +5587,10 @@ sram@14680000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-sram@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 90a6f902c8de56a2e32f8c458c10e42b29a4394a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:18 +0530 Subject: [PATCH 062/117] arm64: dts: qcom: sm8450: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-8-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index c3e22f6a69e4..b8793482b181 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -479,6 +479,7 @@ scm: scm { compatible = "qcom,scm-sm8450", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -4964,6 +4965,10 @@ sram@146aa000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 1243108ae31de2de25ba08d08debad4bf8afe3ad Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:19 +0530 Subject: [PATCH 063/117] arm64: dts: qcom: sa8775p: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-9-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 17bc5bcd9d09..695eae1b7256 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -514,6 +514,7 @@ firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; }; }; @@ -6821,6 +6822,10 @@ sram: sram@146d8000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 8106cb30725baca6568cc8f54dffdbef792d52bf Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:20 +0530 Subject: [PATCH 064/117] arm64: dts: qcom: qcs8300: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-10-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d839f3683535..0812ed997381 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -614,6 +614,7 @@ firmware { scm: scm { compatible = "qcom,scm-qcs8300", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; }; }; @@ -7163,6 +7164,10 @@ sram: sram@146d8000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 27ba11afe4aeeed7d9aa31179fdc46656d6f335d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:21 +0530 Subject: [PATCH 065/117] arm64: dts: qcom: qdu1000: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-11-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 26cc86d12f72..af106aebd30d 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -171,6 +171,7 @@ cluster_sleep_1: cluster-sleep-1 { firmware { scm { compatible = "qcom,scm-qdu1000", "qcom,scm"; + sram = <&minidump_config>; }; }; @@ -1369,6 +1370,10 @@ sram@14680000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From a1db65c7980a5567396a74ce94272d26f0bcb86a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:22 +0530 Subject: [PATCH 066/117] arm64: dts: qcom: sm8550: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-12-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 2888ec109ef7..0e701e709235 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -391,6 +391,7 @@ scm: scm { qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + sram = <&minidump_config>; }; }; @@ -5551,6 +5552,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2c000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@8000 { reg = <0x8000 0x2000>; }; From f0259f721e1870177a949d56fc6970454c452d23 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:24 +0530 Subject: [PATCH 067/117] arm64: dts: qcom: sc7280: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-14-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index f74fa66f1a67..f2da3706d5c8 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -723,6 +723,7 @@ firmware { scm: scm { compatible = "qcom,scm-sc7280", "qcom,scm"; qcom,dload-mode = <&tcsr_2 0x13000>; + sram = <&minidump_config>; }; }; @@ -6714,6 +6715,10 @@ sram@146a5000 { ranges = <0 0 0x146a5000 0x6000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@3000 { reg = <0x3000 0x2000>; }; From e030c56e38fcd5d30fb57f0db3388d13e29872b4 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:25 +0530 Subject: [PATCH 068/117] arm64: dts: qcom: sm8350: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-15-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 524693ec31c9..32b47f5ec1f6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -295,6 +295,7 @@ firmware { scm: scm { compatible = "qcom,scm-sm8350", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -3535,6 +3536,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x40000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@3d000 { reg = <0x3d000 0x2000>; }; From 9d2f33d8ceacde93631319f06243bfc5ed41e2d7 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:26 +0530 Subject: [PATCH 069/117] arm64: dts: qcom: sc7180: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-16-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 18f9cb82639a..70fbfb31d4a4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -385,6 +385,7 @@ cluster_aoss_sleep: cluster-sleep-2 { firmware { scm: scm { compatible = "qcom,scm-sc7180", "qcom,scm"; + sram = <&minidump_config>; }; }; @@ -3596,6 +3597,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2e000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@28000 { reg = <0x28000 0x2000>; }; From 4e9b6041bbdddde93369df47ba44c759e29c0972 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:27 +0530 Subject: [PATCH 070/117] arm64: dts: qcom: sm6350: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-17-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 51e0cb5cce66..15d38b7e803c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -363,6 +363,7 @@ big_cpu_sleep_1: cpu-sleep-1-1 { firmware { scm: scm { compatible = "qcom,scm-sm6350", "qcom,scm"; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -2820,6 +2821,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2e000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@28000 { reg = <0x28000 0x2000>; }; From aadae3dbd5ae8c98ee1e6c8b6636f18b006cb905 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:28 +0530 Subject: [PATCH 071/117] arm64: dts: qcom: sm6375: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-18-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index ccf572bb1549..71a228597093 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -307,6 +307,7 @@ scm { compatible = "qcom,scm-sm6375", "qcom,scm"; clocks = <&rpmcc RPM_SMD_CE1_CLK>; clock-names = "core"; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -1645,6 +1646,10 @@ sram@c125000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 32df14ece3e5c92bd2ddf1eebb3f193df3b7a701 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:29 +0530 Subject: [PATCH 072/117] arm64: dts: qcom: qcs615: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-19-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 07ba5733ca92..eedfdce3c479 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -474,6 +474,7 @@ firmware { scm { compatible = "qcom,scm-qcs615", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; }; }; @@ -4722,6 +4723,10 @@ sram@14680000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@2a94c { compatible = "qcom,pil-reloc-info"; reg = <0x2a94c 0xc8>; From 6fb55156f44ae3fd8e2a308167ed8dad1249492a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:30 +0530 Subject: [PATCH 073/117] arm64: dts: qcom: sdm845: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260624190830.3131112-20-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 562d411ed256..b1f6782a3ad9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -363,6 +363,7 @@ cluster_sleep_0: cluster-sleep-0 { firmware { scm { compatible = "qcom,scm-sdm845", "qcom,scm"; + sram = <&minidump_config>; }; }; @@ -5195,6 +5196,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x40000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@3d000 { reg = <0x3d000 0x2000>; }; From b4387e476fb2fdcc2c4697bd607833ea567db747 Mon Sep 17 00:00:00 2001 From: William Bright Date: Thu, 23 Jul 2026 19:18:07 +0100 Subject: [PATCH 074/117] dt-bindings: vendor-prefixes: Add IMDT Add IMDT (IMD Technologies Ltd) to the vendor prefixes list. Acked-by: Rob Herring (Arm) Signed-off-by: William Bright Link: https://lore.kernel.org/r/20260723-imdt-qcs8550-sbc-rfc-v5-1-2fb988854623@imd-tec.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 7b0d79ebf9bd..5c74da791c13 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -791,6 +791,8 @@ patternProperties: description: ILI Technology Corporation (ILITEK) "^imagis,.*": description: Imagis Technologies Co., Ltd. + "^imdt,.*": + description: IMD Technologies Ltd. "^img,.*": description: Imagination Technologies Ltd. "^imi,.*": From d15c4f0eff1e7b6fc23ea2e37a32633642ce4b85 Mon Sep 17 00:00:00 2001 From: William Bright Date: Thu, 23 Jul 2026 19:18:08 +0100 Subject: [PATCH 075/117] dt-bindings: arm: qcom: Document IMDT QCS8550 SBC/SoM Document the IMDT QCS8550 SBC which consists of an IMDT QCS8550 SoM soldered onto an IMDT QCS8550 carrier board. Acked-by: Rob Herring (Arm) Signed-off-by: William Bright Link: https://lore.kernel.org/r/20260723-imdt-qcs8550-sbc-rfc-v5-2-2fb988854623@imd-tec.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f8ee354070d0..b035557283e1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1138,6 +1138,13 @@ properties: - sony,pdx234 - const: qcom,sm8550 + - items: + - enum: + - imdt,qcs8550-sbc + - const: imdt,qcs8550-som + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - qcom,qcs8550-aim300-aiot From b9f1f97846bcb1989bb52b6cbd1205ecc22c8e43 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Fri, 31 Jul 2026 14:10:31 +0530 Subject: [PATCH 076/117] arm64: dts: qcom: eliza: Add LPASS macro and SoundWire support Add SoC-level LPASS WSA macro, VA macro, SoundWire controller and LPASS LPI pin controller nodes. DMIC and WSA SoundWire pinctrl states are defined inside the LPASS LPI pin controller node. The hardware is similar to the SM8750 platform. The SoundWire controller is kept disabled so board DTS files can selectively enable and configure it. Signed-off-by: Ravi Hothi Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260731084032.3106477-2-ravi.hothi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 189 ++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 83b8d80545e9..0d4629b2ded8 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -2064,6 +2065,77 @@ q6prmcc: clock-controller { }; }; + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,eliza-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06b00000 0x0 0x1000>; + + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.1.0", + "qcom,soundwire-v2.0.0"; + reg = <0x0 0x06b10000 0x0 0x10000>; + interrupts = ; + + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + + label = "WSA"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = + /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f + 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = + /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 + 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = + /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f + 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = + /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 + 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,eliza-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -2078,6 +2150,123 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + lpass_vamacro: codec@7660000 { + compatible = "qcom,eliza-lpass-va-macro", + "qcom,sm8550-lpass-va-macro"; + reg = <0x0 0x07660000 0x0 0x2000>; + + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,eliza-lpass-lpi-pinctrl"; + reg = <0x0 0x07760000 0x0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic45_default: dmic45-default-state { + clk-pins { + pins = "gpio12"; + function = "dmic3_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio13"; + function = "dmic3_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic67_default: dmic67-default-state { + clk-pins { + pins = "gpio21"; + function = "dmic4_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio22"; + function = "dmic4_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x08804000 0x0 0x1000>; From f016b7e86137f6a83de84f660b6bb3d7b955de25 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Fri, 31 Jul 2026 14:10:32 +0530 Subject: [PATCH 077/117] arm64: dts: qcom: eliza-cqs-evk: Enable sound card support with WSA8845 and DMIC Enable the sound card on the Eliza CQS EVK platform, including the WSA8845 external speaker path and DMIC microphone capture via VA macro. Enable the required LPASS WSA macro, VA macro and SoundWire controller along with the necessary pinctrl configurations for DMIC and WSA SoundWire interfaces. Signed-off-by: Ravi Hothi Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260731084032.3106477-3-ravi.hothi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts | 141 +++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts index 43d428a4ed2d..5e4175291f05 100644 --- a/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts @@ -5,10 +5,151 @@ /dts-v1/; +#include + #include "eliza-cqs-som.dtsi" #include "eliza-evk.dtsi" / { model = "Qualcomm Technologies, Inc. Eliza CQS EVK"; compatible = "qcom,eliza-cqs-evk", "qcom,eliza-cqs-som", "qcom,eliza"; + + sound { + compatible = "qcom,eliza-sndcard", "qcom,sm8450-sndcard"; + model = "eliza-cqs-evk"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb", + "VA DMIC4", "vdd-micb", + "VA DMIC5", "vdd-micb", + "VA DMIC6", "vdd-micb", + "VA DMIC7", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + dmic_eldo: regulator-dmic-eldo { + compatible = "regulator-fixed"; + regulator-name = "dmic-eldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm7550_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>, + <&dmic45_default>, <&dmic67_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&dmic_eldo>; + qcom,dmic-sample-rate = <4800000>; +}; + +&swr0 { + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; + vdd-1p8-supply = <&vreg_l7b>; + vdd-io-supply = <&vreg_l7b>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + vdd-1p8-supply = <&vreg_l7b>; + vdd-io-supply = <&vreg_l7b>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio79"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; From 2cc1076501887746f20bdcca40ae703c8c13bc7a Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 29 Jul 2026 14:27:19 +0300 Subject: [PATCH 078/117] arm64: dts: qcom: sm8650: Assign CCI clock rates to 37.5MHz Setting CCI supply clock rate to higher value of 37.5MHz allows to program the controller to configure its I2C bus speed to Fast-mode plus. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Neil Armstrong Reviewed-by: Loic Poulain Link: https://lore.kernel.org/r/20260729112719.1151700-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 799d549a9019..893a7a6f0c28 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5351,6 +5351,8 @@ cci0: cci@ac15000 { clock-names = "camnoc_axi", "cpas_ahb", "cci"; + assigned-clocks = <&camcc CAM_CC_CCI_0_CLK>; + assigned-clock-rates = <37500000>; pinctrl-0 = <&cci0_0_default &cci0_1_default>; pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; pinctrl-names = "default", "sleep"; @@ -5384,6 +5386,8 @@ cci1: cci@ac16000 { clock-names = "camnoc_axi", "cpas_ahb", "cci"; + assigned-clocks = <&camcc CAM_CC_CCI_1_CLK>; + assigned-clock-rates = <37500000>; pinctrl-0 = <&cci1_0_default &cci1_1_default>; pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; pinctrl-names = "default", "sleep"; @@ -5417,6 +5421,8 @@ cci2: cci@ac17000 { clock-names = "camnoc_axi", "cpas_ahb", "cci"; + assigned-clocks = <&camcc CAM_CC_CCI_2_CLK>; + assigned-clock-rates = <37500000>; pinctrl-0 = <&cci2_0_default &cci2_1_default>; pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; pinctrl-names = "default", "sleep"; From 3e6a70436d363dec92b3e6c089ab3d2d5f11d8b9 Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Mon, 3 Aug 2026 16:56:30 +0530 Subject: [PATCH 079/117] arm64: dts: qcom: shikra: Add QUPv3 configuration Add device tree support for QUPv3 serial engine protocols on Shikra. Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-1-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++ 1 file changed, 951 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 80e8045282d8..524c88615d08 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -348,6 +349,161 @@ tlmm: pinctrl@500000 { gpio-ranges = <&tlmm 0 0 165>; wakeup-parent = <&mpm>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio2", "gpio3"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio10", "gpio11"; + function = "qup0_se3_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup0_se4_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio18", "gpio19"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup0_se7_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio22", "gpio23"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio27", "gpio26"; + function = "qup0_se9_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio1"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio2", "gpio3", "gpio0"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio9"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio6", "gpio7", "gpio8"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio17"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio16"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio29"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio18", "gpio19", "gpio28"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio25"; + function = "qup0_se8"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio22", "gpio23", "gpio24"; + function = "qup0_se8"; + drive-strength = <6>; + bias-disable; + }; + qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1"; function = "qup0_se0"; @@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; + qup_uart1_default: qup-uart1-default-state { + pins = "gpio4", "gpio5"; + function = "qup0_se1_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + /* TX, RX */ + pins = "gpio8", "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart2_cts_rts: qup-uart2-cts-rts-state { + /* CTS, RTS */ + pins = "gpio6", "gpio7"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart3_default: qup-uart3-default-state { + pins = "gpio10", "gpio11"; + function = "qup0_se3_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup0_se4_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio16", "gpio17"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins = "gpio14", "gpio15"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins = "gpio28", "gpio29"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins = "gpio18", "gpio19"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart7_default: qup-uart7-default-state { + pins = "gpio20", "gpio21"; + function = "qup0_se7_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + /* TX, RX */ + pins = "gpio24", "gpio25"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart8_cts_rts: qup-uart8-cts-rts-state { + /* CTS, RTS */ + pins = "gpio22", "gpio23"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart9_default: qup-uart9-default-state { + pins = "gpio26", "gpio27"; + function = "qup0_se9_23"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -604,6 +859,34 @@ opp-384000000 { }; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x04a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <16>; + dma-channel-mask = <0xff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xf6 0x0>; + }; + qupv3_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x04ac0000 0x0 0x2000>; @@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 { clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; #size-cells = <2>; ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart0: serial@4a80000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; @@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, status = "disabled"; }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart1: serial@4a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart2: serial@4a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a88000 0x0 0x4000>; + + interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>, + <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart3: serial@4a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@4a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c6: i2c@4a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@4a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart6: serial@4a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c7: i2c@4a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart7: serial@4a9c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c8: i2c@4aa0000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>, + <&gpi_dma0 1 8 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@4aa0000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>, + <&gpi_dma0 1 8 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart8: serial@4aa0000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c9: i2c@4aa4000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4aa4000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>, + <&gpi_dma0 1 9 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart9: serial@4aa4000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04aa4000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; }; sram@c11e000 { From 9e5bbfecb523aef0d01241b13d705ca8a48d7d7d Mon Sep 17 00:00:00 2001 From: Sayantan Chakraborty Date: Mon, 3 Aug 2026 16:56:31 +0530 Subject: [PATCH 080/117] arm64: dts: qcom: shikra: Add DDR BWMON support Add CPU-to-DDR BWMON nodes and their corresponding opp tables for Shikra SoC. This is necessary to enable power management and optimize system performance from the perspective of dynamically changing DDR frequencies. Signed-off-by: Sayantan Chakraborty Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-2-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 524c88615d08..3582352dcff7 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -661,6 +661,46 @@ rclk-pins { }; }; + pmu@c91000 { + compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x00c91000 0x0 0x1000>; + + interrupts = ; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <1200000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <3072000>; + }; + + opp-3 { + opp-peak-kBps = <4068000>; + }; + + opp-4 { + opp-peak-kBps = <6220000>; + }; + + opp-5 { + opp-peak-kBps = <7216000>; + }; + }; + }; + mem_noc: interconnect@d00000 { compatible = "qcom,shikra-mem-noc-core"; reg = <0x0 0x00d00000 0x0 0x43080>; From aadafe002c9836da43a890f3bcba0a7ab8a69a1e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:32 +0530 Subject: [PATCH 081/117] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs. Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables required to scale DDR and L3 per freq-domain on Shikra SoC. Co-developed-by: Aastha Pandey Signed-off-by: Aastha Pandey Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sayantan Chakraborty Signed-off-by: Sayantan Chakraborty Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-3-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 140 +++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 3582352dcff7..a01e26d9ee6d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,14 @@ cpu0: cpu@0 { next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu1: cpu@100 { @@ -54,6 +63,14 @@ cpu1: cpu@100 { next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu2: cpu@200 { @@ -64,6 +81,14 @@ cpu2: cpu@200 { next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu3: cpu@300 { @@ -74,6 +99,14 @@ cpu3: cpu@300 { next-level-cache = <&l2_3>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <489>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; @@ -132,6 +165,86 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <1200000 17817600>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <3072000 30105600>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 38707200>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <7216000 43622400>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <7216000 43622400>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible = "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <1200000 17817600>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <3072000 30105600>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 38707200>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <7216000 43622400>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <7216000 43622400>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = ; @@ -1820,6 +1933,33 @@ frame@f42d000 { status = "disabled"; }; }; + + epss_l3: interconnect@fd90000 { + compatible = "qcom,shikra-epss-l3"; + reg = <0x0 0x0fd90000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,shikra-epss"; + reg = <0x0 0x0fd91000 0x0 0x1000>, + <0x0 0x0fd92000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; }; timer { From 4a0123734f43acef97cf4e7e05ec33f530e2dbe5 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Mon, 3 Aug 2026 16:56:33 +0530 Subject: [PATCH 082/117] arm64: dts: qcom: shikra: Add SMP2P nodes Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable inter-processor signalling for remoteproc state management. Signed-off-by: Vishnu Santhosh Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-4-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a01e26d9ee6d..42a17ffc040f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -428,6 +428,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 { }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apcs_glb 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-lmcu { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + + interrupts = ; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <26>; + + lmcu_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + lmcu_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; From 8b6f81f7801a44c0ad141c3bda5537daa5611993 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 3 Aug 2026 16:56:34 +0530 Subject: [PATCH 083/117] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem. Signed-off-by: Bibek Kumar Patro Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-5-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 42a17ffc040f..570505c927bb 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1813,6 +1813,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,shikra-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&mpss_wlan_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 12>; + qcom,remote-pid = <1>; + label = "mpss"; + }; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,fastrpc"; + #address-cells = <1>; + #size-cells = <0>; + label = "cdsp"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0201 0x0000>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0202 0x0000>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0203 0x0000>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0204 0x0000>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0205 0x0000>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0206 0x0000>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x0209 0x0000>; + }; + }; + }; + }; + + remoteproc_lpaicp: remoteproc@b800000 { + compatible = "qcom,shikra-lpaicp-pas"; + reg = <0x0 0x0b800000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>, + <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; + + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&lmcu_mem &lmcu_dtb_mem>; + + qcom,smem-states = <&lmcu_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 9>; + qcom,remote-pid = <26>; + label = "lpaicp"; + }; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "mmio-sram"; reg = <0x0 0x0c11e000 0x0 0x1000>; From 1db66deb4af8c4121172dfd13aff4cabfacf4534 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 3 Aug 2026 16:56:35 +0530 Subject: [PATCH 084/117] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and IQS EVK board. Signed-off-by: Bibek Kumar Patro Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-6-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 0a52ab9b7a4c..b112b21b1d79 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index b3f19a64d7ae..e62ba5aef71f 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 3003a47bd759..727809430fd1 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm8150_l17>; vqmmc-supply = <&pm8150_s4>; From adf87a37cfc9bbdcac4951bdccfb258a1a44ac0f Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Mon, 3 Aug 2026 16:56:36 +0530 Subject: [PATCH 085/117] arm64: dts: qcom: shikra: Enable TSENS and thermal zones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The shikra includes one TSENS instance, with a total of 14 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 120°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110°C and critical trip at 115°C. Signed-off-by: Gaurav Kohli Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-7-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++ 1 file changed, 267 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 570505c927bb..fb0391bef460 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -998,6 +999,18 @@ spmi_bus: spmi@1c40000 { qcom,ee = <0>; }; + tsens0: thermal-sensor@4411000 { + compatible = "qcom,shikra-tsens", "qcom,tsens-v2"; + reg = <0x0 0x04411000 0x0 0x1000>, + <0x0 0x04410000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <14>; + #thermal-sensor-cells = <1>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; @@ -2195,6 +2208,260 @@ cpufreq_hw: cpufreq@fd91000 { }; }; + thermal_zones: thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu00-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu01-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu10-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu11-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsp-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss0-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss1-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu02-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; From a04957d5ef041059d26fabe8d1a754e6c408fe2a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:37 +0530 Subject: [PATCH 086/117] arm64: dts: qcom: shikra: add WiFi node support Introduce the WiFi hardware description in shikra.dtsi, including register space, interrupts, IOMMU configuration and reserved memory. The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-8-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index fb0391bef460..efb02e8719e9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2079,6 +2079,29 @@ apps_smmu: iommu@c600000 { ; }; + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x0c800000 0x0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + + status = "disabled"; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf200000 0x0 0x10000>, From 320670a802179ac0851f010f78053da0731c6da8 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:38 +0530 Subject: [PATCH 087/117] arm64: dts: qcom: shikra: Enable WiFi/BT on SoMs Shikra SoM cards include WCN3988 WiFi/Bluetooth chip, with supplies provided by on-card PMICs. Enable both interfaces and provide the required supply and calibration data. Co-developed-by: Yepuri Siddu Signed-off-by: Yepuri Siddu Co-developed-by: Miaoqing Pan Signed-off-by: Miaoqing Pan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-9-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 74 ++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 82 ++++++++++++++++++++ 2 files changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index dc3861489f64..2fff5fe9f6d2 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -11,6 +11,10 @@ #include "pm8005.dtsi" / { + aliases { + serial1 = &uart8; + }; + gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; @@ -27,6 +31,42 @@ key-volume-up { linux,can-disable; }; }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm4125_l7>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &pm4125_gpios { @@ -154,3 +194,37 @@ pm4125_l22: l22 { }; }; }; + +&tlmm { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart8 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + max-speed = <3200000>; + + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "shikra"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index 73945bf42112..657a14ca9606 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -10,6 +10,10 @@ #include "pm8150.dtsi" / { + aliases { + serial1 = &uart8; + }; + gpio-key { compatible = "gpio-keys"; label = "gpio-keys"; @@ -26,6 +30,50 @@ key-volume-up { linux,can-disable; }; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + regulator-name = "wcn_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm8150_s4>; + vddxo-supply = <&pm8150_l12>; + vddrf-supply = <&pm8150_l8>; + vddch0-supply = <&vreg_wcn_3p3>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &pm8150_gpios { @@ -168,3 +216,37 @@ pm8150_l18: l18 { }; }; }; + +&tlmm { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart8 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + max-speed = <3200000>; + + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm8150_s4>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "shikra"; + + status = "okay"; +}; From 779aead2dace11c7a514c0b94f87c0f2dcf59ca3 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:39 +0530 Subject: [PATCH 088/117] arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm Add gpio-reserved-ranges property to the TLMM node for both Shikra SoM variants (CQM and IQS). These reserved GPIOs are inaccessible from the non-secure world and dedicated to fixed functions. Co-developed-by: Anurag Pateriya Signed-off-by: Anurag Pateriya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-10-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 2fff5fe9f6d2..8ac42ff625a0 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -196,6 +196,12 @@ pm4125_l22: l22 { }; &tlmm { + gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */ + <14 4>, /* eSE SPI */ + <30 2>, /* NFC SPI */ + <138 1>, /* NFC Secure IO */ + <155 11>; /* eMMC Boot */ + sw_ctrl_default: sw-ctrl-default-state { pins = "gpio88"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index 657a14ca9606..4ff97945274d 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -218,6 +218,12 @@ pm8150_l18: l18 { }; &tlmm { + gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */ + <14 4>, /* eSE SPI */ + <30 2>, /* NFC SPI */ + <138 1>, /* NFC Secure IO */ + <155 11>; /* eMMC Boot */ + sw_ctrl_default: sw-ctrl-default-state { pins = "gpio88"; function = "gpio"; From 26d7b23caa4b1d8208e28c5981a85cf83e658e7c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Sat, 18 Jul 2026 18:26:19 +0530 Subject: [PATCH 089/117] arm64: dts: qcom: agatti: Add missing CX power domain to DISPCC Add the missing power-domains property to associate DISPCC with CX rail. This is to ensure the genpd performance state votes on the GDSC to get propagated to the CX rail and to avoid the rail under-voltage conditions. Fixes: a2b32096709d ("arm64: dts: qcom: qcm2290: Add display nodes") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-12-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index f0b6ae9b8152..590bd2432d85 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2197,6 +2197,7 @@ dispcc: clock-controller@5f00000 { "gcc_disp_gpll0_div_clk_src", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk"; + power-domains = <&rpmpd QCM2290_VDDCX>; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; From 58a273157af32b7d8e6fbd7930db3a5044c2ad10 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Sat, 18 Jul 2026 18:26:23 +0530 Subject: [PATCH 090/117] arm64: dts: qcom: shikra: Add support for DISPCC/GPUCC nodes Add support for Display clock controller and GPU clock controller nodes on Qualcomm Shikra SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-16-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index efb02e8719e9..92d22e3b6931 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -3,6 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include #include #include #include @@ -1990,6 +1992,40 @@ glink-edge { }; }; + gpucc: clock-controller@5990000 { + compatible = "qcom,shikra-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; + reg = <0x0 0x05f00000 0x0 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, + <0>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk"; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "mmio-sram"; reg = <0x0 0x0c11e000 0x0 0x1000>; From ff7155df9a9543af1eb9722563e6dcda33c1a97d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:00 +0200 Subject: [PATCH 091/117] arm64: dts: qcom: sc8280xp-blackrock: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 16a7fed11714 ("arm64: dts: qcom: sc8280xp-blackrock: dt definition for WDK2023") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-2-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 9da2ffb318d0..4f4b5f4285ec 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -996,8 +996,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4d>; - vdda-pll-supply = <&vreg_l9d>; + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; orientation-switch; @@ -1033,8 +1033,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3b>; - vdda-pll-supply = <&vreg_l4b>; + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; orientation-switch; From 1960614611142e4b57f8a4e276f36ff8b6db2a1d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:01 +0200 Subject: [PATCH 092/117] arm64: dts: qcom: sa8540p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 519183af39b2 ("arm64: dts: qcom: add SA8540P and ADP") Fixes: 6be310347c9c ("arm64: dts: qcom: add SA8540P ride(Qdrive-3)") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-3-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 16 ++++++++-------- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 512de3597581..6ea60cdf1823 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -612,8 +612,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; @@ -636,8 +636,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l4c>; - vdda-pll-supply = <&vreg_l1c>; + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4c>; status = "okay"; }; @@ -679,15 +679,15 @@ &usb_2_hsphy3 { }; &usb_2_qmpphy0 { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; &usb_2_qmpphy1 { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 83d5f1d9e79b..c72faaa0ae7a 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -482,8 +482,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; @@ -497,8 +497,8 @@ &usb_2_hsphy0 { }; &usb_2_qmpphy0 { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; From ce18e4c1cfc77c2eda5f0b9839edac1b0e929c54 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:02 +0200 Subject: [PATCH 093/117] arm64: dts: qcom: sdm845: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Fixes: a678adbf2d22 ("arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL") Fixes: 28ae8aa3923c ("arm64: dts: qcom: add device tree for LG G7 and LG V35") Fixes: cfe10d38aa1a ("arm64: dts: qcom: sdm845-mtp: Add nodes for USB") Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Fixes: 45882459159d ("arm64: dts: qcom: sdm845: add device tree for SHIFT6mq") Fixes: dd6459a0890a ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Fixes: be497abe19bf ("arm64: dts: qcom: Add support for Xiaomi Mi Mix2s") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-4-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 4 ++-- .../boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 4 ++-- 8 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 02416812b6a7..846138149b2c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1121,8 +1121,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &usb_2 { @@ -1147,8 +1147,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index 9368fd6b8751..9e952f9862f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -571,8 +571,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 5ac2e058827c..b030a10009c5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -674,8 +674,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 97c79b51ff42..c66df45eee64 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -727,8 +727,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; }; &usb_2 { @@ -759,8 +759,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index a404a23086d4..bd59f1dcd96d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -947,8 +947,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index e31c784eff3d..1b0eaeafbd51 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -874,8 +874,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index cc14d9fa3b05..080f5294988d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -643,8 +643,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 96d4f7496f2f..d3162e444453 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -666,8 +666,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-pll-supply = <&vreg_l1a_0p875>; - vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l26a_1p2>; + vdda-phy-supply = <&vreg_l1a_0p875>; status = "okay"; }; From ef7b567f54c72a91dec3fb0bd5d80b8e956f7cd8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:03 +0200 Subject: [PATCH 094/117] arm64: dts: qcom: sdm850: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: aab69794b55d ("arm64: dts: qcom: Add support for Huawei MateBook E 2019") Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Fixes: d4b341269efb ("arm64: dts: qcom: Add support for Samsung Galaxy Book2") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-5-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index e38b768d16a1..9b217580e1d5 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -870,8 +870,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; status = "okay"; }; @@ -896,8 +896,8 @@ &usb_2_hsphy { }; &usb_2_qmpphy { - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 981074a40e38..2bad7297cb7f 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -858,8 +858,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; }; &usb_1_qmpphy_out { @@ -951,8 +951,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 1dab0582eae6..d6a1d2542c1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -608,8 +608,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; }; &usb_2 { @@ -634,8 +634,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; }; &venus { From 3a0c5af9fb0e835e90c4f2439dc4534301be8856 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:04 +0200 Subject: [PATCH 095/117] arm64: dts: qcom: sm8150: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0ab1b2d10afe ("arm64: dts: qcom: add sm8150 hdk dts") Fixes: b33d2868e8d3 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes") Fixes: d1f781db47a8 ("arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo") Fixes: d0a6ce59ea4e ("arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform)") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-6-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 4 ++-- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 8fb04ce72f91..cdced5c848d3 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -801,8 +801,8 @@ &usb_2_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l18a_0p8>; + vdda-phy-supply = <&vreg_l18a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; }; @@ -812,8 +812,8 @@ &usb_1_qmpphy_out { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p875>; + vdda-phy-supply = <&vreg_l5a_0p875>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 835ef929ff2d..f37e11bde067 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -520,8 +520,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + vdda-phy-supply = <&vdda_usb_ss_dp_core_1>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 0f2d511624a8..6a6564d8d7f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -438,8 +438,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + vdda-phy-supply = <&vdda_usb_ss_dp_core_1>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index 70fd6455518b..6c2e2bf869d0 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -869,6 +869,6 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l18a_0p8>; + vdda-phy-supply = <&vreg_l18a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; From d57a10f2ebcf327bdecf8bb26e9f330b17b0b1a6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:05 +0200 Subject: [PATCH 096/117] arm64: dts: qcom: sm8250: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 91ed0e90fc49 ("arm64: dts: qcom: add sm8250 hdk dts") Fixes: 221f0ef37f55 ("arm64: dts: sm8250-mtp: enable USB host nodes") Fixes: 69cdb97ef652 ("arm64: dts: qcom: sm8250: Add support for SONY Xperia 1 II / 5 II (Edo platform)") Fixes: 264beb3cbd0d ("arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree") Fixes: 52c90664f122 ("arm64: dts: qcom: qrb5165-rb5: Add USB support") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-7-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts | 4 ++-- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 690b484352ed..d6af679abe1a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1424,8 +1424,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_1_qmpphy_out { @@ -1451,8 +1451,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &vamacro { diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 3ea9d2b1a7d5..c1c673086df5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -438,14 +438,14 @@ &usb_2_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 51779b99176d..14c8ca602110 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -862,8 +862,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_2 { @@ -885,8 +885,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index d8289b2698f3..51c0caaf4ea1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -715,8 +715,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index 078ba13f8762..f11e4e244dff 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -515,8 +515,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &ufs_mem_hc { From 65cd57115c379ff0d0a200ad5a857afb8042a63c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:06 +0200 Subject: [PATCH 097/117] arm64: dts: qcom: sm8350: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 9208c19f2124 ("arm64: dts: qcom: Introduce SM8350 HDK") Fixes: c16160cfa565 ("arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2") Fixes: 054b40a6111f ("arm64: dts: qcom: sm8350-mtp: enable USB nodes") Fixes: 5a077120bcf6 ("arm64: dts: qcom: sm8350-sagami: Wire up USB regulators and fix USB3") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-8-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 ++++---- .../arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 4 ++-- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index d98ec4bcfd87..bb93c3e9417b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -866,8 +866,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p88>; + vdda-phy-supply = <&vreg_l1b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_1_qmpphy_out { @@ -896,8 +896,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l5b_0p88>; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; /* PINCTRL - additions to nodes defined in sm8350.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 6b10464e8774..442405ba5f6a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -356,8 +356,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p88>; + vdda-phy-supply = <&vreg_l1b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_2 { @@ -375,6 +375,6 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l5b_0p88>; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index b25f223d6190..410bb0befeea 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -354,8 +354,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p88>; + vdda-phy-supply = <&vreg_l1b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_2 { @@ -373,8 +373,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l5b_0p88>; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &ipa { diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index ba862b4f9890..4b62ee50da7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -916,6 +916,6 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&pm8350_l6>; - vdda-pll-supply = <&pm8350_l1>; + vdda-phy-supply = <&pm8350_l1>; + vdda-pll-supply = <&pm8350_l6>; }; From 6469731fb66f40ab873bf4c9fd97d295b390e87f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:07 +0200 Subject: [PATCH 098/117] arm64: dts: qcom: sm8450: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.91V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 067b2b3616cd ("arm64: dts: qcom: Add SM8450 HDK DTS") Fixes: 27a0d0b846d9 ("arm64: dts: qcom: sm8450-qrd: Enable USB nodes") Fixes: 1620676b85f1 ("arm64: dts: qcom: sm8450-nagara: Separate out Nagara platform dtsi") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-9-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index b37998cd9a2c..4ade28f40cae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1214,8 +1214,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p91>; + vdda-phy-supply = <&vreg_l1b_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 56db5f79f59d..4993059483e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -527,8 +527,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p91>; + vdda-phy-supply = <&vreg_l1b_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 6bd315e10992..4fb5627d8126 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -793,7 +793,7 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&pm8350_l6>; - vdda-pll-supply = <&pm8350_l1>; + vdda-phy-supply = <&pm8350_l1>; + vdda-pll-supply = <&pm8350_l6>; status = "okay"; }; From f35723d6b6a2f6d6fc3cf2fc3ff556436f76ebd4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:08 +0200 Subject: [PATCH 099/117] arm64: dts: qcom: sm8550: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 772e6bc4a0a9 ("arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodes") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-10-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 58c71ac67da5..82fb10ed6b6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1649,8 +1649,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p88>; + vdda-phy-supply = <&vreg_l3f_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5769be83cfbd..7c634572c6b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -971,8 +971,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p91>; + vdda-phy-supply = <&vreg_l3f_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 144e105b734f..473ec4e27daf 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1549,8 +1549,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p88>; + vdda-phy-supply = <&vreg_l3f_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 0e6ed6fce614..367f6eae5e65 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -766,8 +766,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&pm8550vs_2_l3>; - vdda-pll-supply = <&pm8550ve_l3>; + vdda-phy-supply = <&pm8550ve_l3>; + vdda-pll-supply = <&pm8550vs_2_l3>; status = "okay"; }; From c0ea3b6339881c2a5fff0830557b1279d9681036 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:09 +0200 Subject: [PATCH 100/117] arm64: dts: qcom: qcs8550-aim300: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-11-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ebb643203b..ae301d78e071 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -412,8 +412,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p88>; + vdda-phy-supply = <&vreg_l3f_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; }; &xo_board { From f6a787a5e238599f3543c3dccf0abd6030dd48e3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:10 +0200 Subject: [PATCH 101/117] arm64: dts: qcom: qcm6490: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 9af6a9f32ad0 ("arm64: dts: qcom: Add base qcm6490 idp board dts") Fixes: a319cf4a4b09 ("arm64: dts: qcom: qcm6490: Introduce the Particle Tachyon") Fixes: eee9602ad649 ("arm64: dts: qcom: qcm6490: Add device-tree for Fairphone 5") Fixes: 249666e34c24 ("arm64: dts: qcom: add QCM6490 SHIFTphone 8") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-12-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index f072bd96c7d4..f41ad446a39e 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1554,8 +1554,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b>; - vdda-pll-supply = <&vreg_l1b>; + vdda-phy-supply = <&vreg_l1b>; + vdda-pll-supply = <&vreg_l6b>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index bdc02260f902..58cce89a0c1c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -1141,8 +1141,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index 94eebb7de7b9..5bb33a8a9830 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -841,8 +841,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index e5366cfd3a02..cf74b3664cf5 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -975,8 +975,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b>; - vdda-pll-supply = <&vreg_l1b>; + vdda-phy-supply = <&vreg_l1b>; + vdda-pll-supply = <&vreg_l6b>; status = "okay"; }; From 83185fc5f51e7fa2d02f02e2504ad7b002c2d1d8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:11 +0200 Subject: [PATCH 102/117] arm64: dts: qcom: qcs6490: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 04cf333afc75 ("arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts") Fixes: 1cde54c54b83 ("arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT") Fixes: f055a39f6874 ("arm64: dts: qcom: Add qcs6490-rubikpi3 board dts") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-13-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 90f2eebc349f..a13315bf0fb0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1419,8 +1419,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; mode-switch; orientation-switch; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 172dc0cbb532..31bafa2cf51d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -1065,8 +1065,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index d8a9a7e47bdc..13e8e62f6205 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -1111,8 +1111,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; From a3b3a060b696d964c769a7d9dc5835c79e4fe964 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:12 +0200 Subject: [PATCH 103/117] arm64: dts: qcom: sm7225-fairphone-fp4: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 4cbea668767d ("arm64: dts: qcom: sm7225: Add device tree for Fairphone 4") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-14-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 711a120753ad..5d20ad93b0c5 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -1246,8 +1246,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l22a>; - vdda-pll-supply = <&vreg_l16a>; + vdda-phy-supply = <&vreg_l16a>; + vdda-pll-supply = <&vreg_l22a>; status = "okay"; }; From 2c45c4df3079acba14920b14286cebfea24ec603 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:13 +0200 Subject: [PATCH 104/117] arm64: dts: qcom: sc7180: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Fixes: 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") Fixes: 4a9f8f8f2ada ("arm64: dts: qcom: Add Acer Aspire 1") Fixes: de8eed359759 ("arm64: dts: qcom: Add support for ECS LIVA QC710") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-15-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index 1514da636269..d9c70897b6f1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -631,8 +631,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; + vdda-phy-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts index b84da371581b..3100fab18787 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts @@ -563,8 +563,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; + vdda-phy-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 0bce3eefca2e..acfb9937651d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -461,8 +461,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; + vdda-phy-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index cd4a0e281cf8..0e0bc8543f71 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -998,8 +998,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; + vdda-phy-supply = <&vdda_usb_ss_dp_core>; + vdda-pll-supply = <&vdda_usb_ss_dp_1p2>; }; &venus { From b3038aac412d14538f135e6509e657997fd6825d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:14 +0200 Subject: [PATCH 105/117] arm64: dts: qcom: sc7280: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 97a5b73b7058 ("arm64: dts: qcom: sc7280-idp: Add device tree files for IDP2") Fixes: 116f7cc43d28 ("arm64: dts: qcom: sc7280: Add herobrine-r1") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-16-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 6bb806931b79..96a7327f00a8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -545,8 +545,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p8>; + vdda-phy-supply = <&vreg_l1b_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 9ae9af40f4d2..264029ff3f90 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -465,8 +465,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>; - vdda-pll-supply = <&vdd_a_usbssdp_0_core>; + vdda-phy-supply = <&vdd_a_usbssdp_0_core>; + vdda-pll-supply = <&vdd_a_usbssdp_0_1p2>; }; &usb_2_hsphy { From 8e1877c41c2ee4ad245e1c26c98f3b4cb2585162 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:15 +0200 Subject: [PATCH 106/117] arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 2ce38cc1e8fe ("arm64: dts: qcom: sc8180x: Introduce Primus") Fixes: 20dea72a393c ("arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-17-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++++++-------- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 7601afc3d7bf..565e5a9979b1 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -611,15 +611,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; @@ -633,8 +633,8 @@ &usb_prim_hsphy { }; &usb_prim_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; @@ -674,8 +674,8 @@ &usb_sec_hsphy { }; &usb_sec_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index e34f4758ebe2..c10a936b320a 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -703,15 +703,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; @@ -725,8 +725,8 @@ &usb_prim_hsphy { }; &usb_prim_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; @@ -762,8 +762,8 @@ &usb_sec_hsphy { }; &usb_sec_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; From 4458dcd38295c8bd13957637ba98132ba3f089b0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:16 +0200 Subject: [PATCH 107/117] arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 5098ae93ce44 ("arm64: dts: qcom: Add HAMOA-IOT-SOM platform") Fixes: af241225893a ("arm64: dts: qcom: Add the Lenovo IdeaCentre Mini X") Fixes: ae5cee8e7349 ("arm64: dts: qcom: x1e80100-crd: Fix USB PHYs regulators") Fixes: 20676f7819d7 ("arm64: dts: qcom: x1e80100-qcp: Fix USB PHYs regulators") Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Fixes: 6516961352a1 ("arm64: dts: qcom: Add support for X1-based Asus Zenbook A14") Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Fixes: 0d72ccaa1e84 ("arm64: dts: qcom: Add support for X1-based Surface Pro 11") Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices") Fixes: 8cf65490cdb0 ("arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1") Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345") Fixes: 7b8a31e82b87 ("arm64: dts: qcom: Add X1E001DE Snapdragon Devkit for Windows") Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6") Fixes: e7733b42111c ("arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-18-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 20 +++++++++---------- .../hamoa-lenovo-ideacentre-mini-01q8x10.dts | 20 +++++++++---------- .../boot/dts/qcom/x1-asus-vivobook-s15.dtsi | 20 +++++++++---------- .../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 20 +++++++++---------- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 20 +++++++++---------- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 16 +++++++-------- .../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 12 +++++------ .../boot/dts/qcom/x1-microsoft-denali.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 20 +++++++++---------- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 20 +++++++++---------- .../dts/qcom/x1e80100-dell-xps13-9345.dts | 16 +++++++-------- .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 12 +++++------ .../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 16 +++++++-------- .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 16 +++++++-------- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 20 +++++++++---------- 15 files changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 9c5e77df0054..bc70fe5db96f 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -590,8 +590,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -611,8 +611,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -632,8 +632,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -670,15 +670,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts index bfb7cea56df9..284825008389 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts @@ -1101,8 +1101,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l1j>; + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1112,8 +1112,8 @@ &usb_1_ss0_qmpphy_out { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1138,8 +1138,8 @@ usb_1_ss1_qmpphy_out_dp: endpoint@0 { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1186,15 +1186,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi index 48c4ad648354..0dc7c1b5a14a 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -1226,8 +1226,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1256,8 +1256,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1277,8 +1277,8 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1342,15 +1342,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 66d566808f58..59cbbfbce490 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -1454,8 +1454,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1484,8 +1484,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1505,8 +1505,8 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1551,15 +1551,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 9602d65c8b3d..60db83b8985f 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1750,8 +1750,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1780,8 +1780,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1810,8 +1810,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1852,15 +1852,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index d6de4da02dcd..4cda708455d8 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1570,8 +1570,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1600,8 +1600,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1639,8 +1639,8 @@ &usb_mp_hsphy0 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1653,8 +1653,8 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index 02708f23a865..dba8cee43e29 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1466,8 +1466,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1496,8 +1496,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1533,8 +1533,8 @@ &usb_mp_hsphy0 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi index 7559557610ed..ce7d958ca687 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -1268,8 +1268,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1298,8 +1298,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 2e38402e2c14..be1a8ac8c699 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1382,8 +1382,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1413,8 +1413,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1443,8 +1443,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1486,15 +1486,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 5d49df41be02..0bee2a3d6e7a 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1601,8 +1601,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1631,8 +1631,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1652,8 +1652,8 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1717,15 +1717,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index ce7b10ea89b6..2be5a37c00cc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -1286,8 +1286,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1316,8 +1316,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1357,15 +1357,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index beb1475d7fa0..9eb2dfd99f20 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1564,8 +1564,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1594,8 +1594,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1624,8 +1624,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index f95b1f9f439d..e4a0b86847cd 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -1407,8 +1407,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1428,8 +1428,8 @@ &usb_1_ss0_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1497,16 +1497,16 @@ &usb_mp_hsphy1 { /* Right side USB-A (USB-SS 3) */ &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; /* Left side USB-A (USB-SS 4) */ &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 28342cb84ded..13d0f09e0c2a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1491,8 +1491,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l1j>; + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1521,8 +1521,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1565,15 +1565,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 8afbac349cc9..78380fec8839 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1416,8 +1416,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1446,8 +1446,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1476,8 +1476,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1519,15 +1519,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; From 7c1d0ef2969e16a97bd03e8340f35a78c889120d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:17 +0200 Subject: [PATCH 108/117] arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 64a0277c9876 ("arm64: dts: qcom: Add PURWA-IOT-SOM platform") Fixes: d3f600dc452d ("arm64: dts: qcom: Add Lenovo ThinkBook 16 G7 QOY device tree") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-19-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 20 +++++++++---------- .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 20 +++++++++---------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index fb2dcbc7c393..488e98413c3a 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -588,8 +588,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -609,8 +609,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -630,8 +630,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -668,15 +668,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 9e6f679758a9..c2f21fcb1b09 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -1562,8 +1562,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1592,8 +1592,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1632,8 +1632,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1686,8 +1686,8 @@ &usb_mp_hsphy0 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1702,8 +1702,8 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; From 464fba94ac2e35b336e19c34336a07946da7128f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:18 +0200 Subject: [PATCH 109/117] arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Fixes: df260487f33c ("arm64: dts: qcom: add basic devicetree for Ayaneo Pocket S2 gaming console") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-20-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 0dc994f4e48d..6ddf30ecabfe 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1536,8 +1536,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 71c0355ece4b..41d0c7edc433 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1614,8 +1614,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index dd6e33d2dc5d..26045430d34a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -886,8 +886,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 5709cfea1bfd..1fb78588a504 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1633,8 +1633,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; From 50c9658bc622888f9664a052fd98ef6026883ea5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:19 +0200 Subject: [PATCH 110/117] arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 2340f29e2b06 ("arm64: dts: qcom: sm8750: Add USB support for SM8750 MTP platform") Fixes: 530f824a4e18 ("arm64: dts: qcom: sm8750: Add USB support for SM8750 QRD platform") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-21-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 3837f6785320..9b5fbc004df4 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -1404,8 +1404,8 @@ &usb { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3g_1p2>; - vdda-pll-supply = <&vreg_l2d_0p88>; + vdda-phy-supply = <&vreg_l2d_0p88>; + vdda-pll-supply = <&vreg_l3g_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 801c46d55602..b56317cfa9fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -1132,8 +1132,8 @@ &usb { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3g_1p2>; - vdda-pll-supply = <&vreg_l2d_0p88>; + vdda-phy-supply = <&vreg_l2d_0p88>; + vdda-pll-supply = <&vreg_l3g_1p2>; status = "okay"; }; From 9d883d21fc12c873eee2f864f706c38a289bef59 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:20 +0200 Subject: [PATCH 111/117] arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 6339e41fa39b ("arm64: dts: qcom: sar2130p: add QAR2130P board file") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-22-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 74778a5b19ba..80428c0b3b4e 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -551,8 +551,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p91>; + vdda-phy-supply = <&vreg_l1a_0p91>; + vdda-pll-supply = <&vreg_l3a_1p2>; status = "okay"; }; From c1dfdea72a9f59b1bdad64b8ec9f918b6c1a721f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:21 +0200 Subject: [PATCH 112/117] arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: b2f036a67580 ("arm64: dts: qcom: kaanpaali: Add USB support for MTP platform") Fixes: 01d15f5f6996 ("arm64: dts: qcom: kaanpaali: Add USB support for QRD platform") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-23-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 7ccff3d03b78..6d817381bb37 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -1389,8 +1389,8 @@ &usb_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l1d_1p2>; - vdda-pll-supply = <&vreg_l4f_0p8>; + vdda-phy-supply = <&vreg_l4f_0p8>; + vdda-pll-supply = <&vreg_l1d_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 6efbe45605a0..abd3e9f8a3eb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -884,8 +884,8 @@ &usb_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l1d_1p2>; - vdda-pll-supply = <&vreg_l4f_0p8>; + vdda-phy-supply = <&vreg_l4f_0p8>; + vdda-pll-supply = <&vreg_l1d_1p2>; status = "okay"; }; From c3c6b388edba50aad0d41b0b2a5e50482e320611 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:22 +0200 Subject: [PATCH 113/117] arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be the lower voltage (~0.8V) and the vdda-pll supply to be the higher voltage (~1.2V), as used by the DisplayPort QMP PHY on this SoC. But these two supplies are swapped for the USB QMP PHYs on this board, feeding 1.2V to vdda-phy and 0.72V/0.83V to vdda-pll. Fix it by swapping the two supplies back. Fixes: c8b63029455b ("arm64: dts: qcom: glymur-crd: Enable USB support") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-24-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 47fa3ae301ac..e27c697e3170 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -1167,8 +1167,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l3f_e0_0p72>; + vdda-phy-supply = <&vreg_l3f_e0_0p72>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l2f_e0_0p82>; status = "okay"; @@ -1196,8 +1196,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l1h_e0_0p89>; + vdda-phy-supply = <&vreg_l1h_e0_0p89>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l2f_e0_0p82>; status = "okay"; @@ -1243,16 +1243,16 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; + vdda-phy-supply = <&vreg_l2h_e0_0p72>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l4f_e1_1p08>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; + vdda-phy-supply = <&vreg_l2h_e0_0p72>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l4f_e1_1p08>; status = "okay"; From 932113c3c77814b4001ad37ea4383b93bc385284 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:23 +0200 Subject: [PATCH 114/117] arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be the lower voltage (~0.8V) and the vdda-pll supply to be the higher voltage (~1.2V), as used by the PCIe and UFS QMP PHYs on this SoC. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.14V to vdda-phy and 0.72V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 76326da895b8 ("arm64: dts: qcom: lemans: Refactor ride/ride-r3 boards based on daughter cards") Fixes: 7bd68ef80661 ("arm64: dts: qcom: lemans-evk: Enable first USB controller in device mode") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-25-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++-- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 0c53640c42a6..a45485b54a5b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -1170,8 +1170,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l1c>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index cefb8ff00806..144f117ba511 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -1103,8 +1103,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l1c>; status = "okay"; }; @@ -1126,8 +1126,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l1c>; status = "okay"; }; From 6b1195eeb204b455973fb05e10563a63bdd71c57 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:24 +0200 Subject: [PATCH 115/117] arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be the lower voltage (~0.8V) and the vdda-pll supply to be the higher voltage (~1.2V), as used by the UFS QMP PHY on this SoC. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.15V to vdda-phy and 0.72V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 49dab7311f57 ("arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-26-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 5abc23b9b676..868ae6c34830 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -579,8 +579,8 @@ &usb { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3g>; - vdda-pll-supply = <&vreg_l7k>; + vdda-phy-supply = <&vreg_l7k>; + vdda-pll-supply = <&vreg_l3g>; status = "okay"; }; From 3b50c16faa8452fd7ff021919c669c7b38227ca4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:25 +0200 Subject: [PATCH 116/117] arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB and UFS QMP PHYs on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 12dd4ebda47a ("arm64: dts: qcom: Fix usb entries for SA8155p adp board") Fixes: 5b85e8f2225c ("arm64: dts: qcom: sa8155p-adp: Add base dts file") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-27-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 388d5ecee949..3e22ee8b5092 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -428,8 +428,8 @@ &ufs_mem_hc { &ufs_mem_phy { status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l8c_1p2>; }; &usb_1 { @@ -474,8 +474,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + vdda-phy-supply = <&vdda_usb_ss_dp_core_1>; + vdda-pll-supply = <&vreg_l8c_1p2>; }; &pcie0 { From b426fedcef8c277574bd7beed0ae9d482c03605a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:26 +0200 Subject: [PATCH 117/117] arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0f9e6db8a223 ("arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-28-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index a057a7271480..a31bed7fad07 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -597,8 +597,8 @@ &usb_qmpphy { }; &usb_qmpphy_2 { - vdda-phy-supply = <&vreg_l11a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l11a>; status = "okay"; };