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dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptions

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Add the S[m|s]csrind ISA extension description.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
[pjw@kernel.org: use official extension names in the patch description]
Link: https://patch.msgid.link/20260807-counter_delegation-v9-4-58658104e487@meta.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Atish Patra 2026-08-07 19:24:31 -06:00 committed by Paul Walmsley
parent 0ce0702f5e
commit 7e1b808807
1 changed files with 16 additions and 0 deletions
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16
Documentation/devicetree/bindings/riscv/extensions.yaml
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@ -181,6 +181,14 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
- const: smcsrind
description: |
The standard Smcsrind machine-level extension extends the
indirect CSR access mechanism defined by the Smaia extension. This
extension allows other ISA extensions to use indirect CSR access
mechanism in M-mode as ratified in the 20240326 version of the
privileged ISA specification.
- const: smmpm
description: |
The standard Smmpm extension for M-mode pointer masking as
@ -226,6 +234,14 @@ properties:
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
ratified state.")
- const: sscsrind
description: |
The standard Sscsrind supervisor-level extension extends the
indirect CSR access mechanism defined by the Ssaia extension. This
extension allows other ISA extensions to use indirect CSR access
mechanism in S-mode as ratified in the 20240326 version of the
privileged ISA specification.
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as