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Qualcomm Arm64 DeviceTree updates for v7.3

Browse Source 
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
 controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
 Document the Hawi and Maili SoCs.
 
 Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
 Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
 Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
 
 Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
 thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
 
 Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
 audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
 thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
 CPU-capacity descriptions.
 
 Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
 support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
 controller support for Hamoa and Glymur boards.
 
 Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
 PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
 camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
 across established Qualcomm platforms.
 
 Correct bindings and DeviceTree validation for Qualcomm compatible strings,
 legacy fallback compatibles, node naming and formatting, address ranges,
 clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
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Merge tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree updates for v7.3

Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.

Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.

Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.

Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.

Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.

Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.

Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.

* tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (244 commits)
  arm64: dts: qcom: eliza: Describe the ADSP GPR node
  arm64: dts: qcom: eliza-evk: Add support for USB and SD card
  dt-bindings: arm: qcom-soc: Allow WSA88xx speaker compatible
  dt-bindings: arm: qcom-soc: Validate nodes with fallbacks
  dt-bindings: arm: qcom-soc: Document more of existing legacy style compatibles
  dt-bindings: arm: qcom-soc: Include Eliza, Kaanapali and others in SoC names
  arm64: dts: qcom: eliza: Enable cpufreq cooling devices
  arm64: dts: qcom: glymur: add SoCCP DT node
  arm64: dts: qcom: glymur: fix SoCCP memory mappings
  arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR
  arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
  arm64: dts: qcom: glymur: Add CX power domain to GCC
  arm64: dts: qcom: glymur: Drop fake PCIe phy 3B
  arm64: dts: qcom: glymur: add TRNG node
  arm64: dts: qcom: glymur: enable ETR and CTCU devices
  arm64: dts: qcom: glymur: Add PCIe port compatibles and ports
  arm64: dts: qcom: smb2370: Disable SMB2370_2 by default
  arm64: dts: qcom: eliza-mtp: Enable touchscreen
  arm64: dts: qcom: purwa-iot-som: enable video
  arm64: dts: qcom: purwa: Override Iris clocks and operating points
  ...

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Alexandre Belloni 2026-08-08 18:44:20 +02:00
commit 7855656ffb
161 changed files with 16109 additions and 1796 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
View File

@ -29,7 +29,11 @@ properties:
oneOf:
- items:
- enum:
- qcom,glymur-ctcu
- qcom,kaanapali-ctcu
- qcom,qcs8300-ctcu
- qcom,sm8750-ctcu
- qcom,x1e80100-ctcu
- const: qcom,sa8775p-ctcu
- enum:
- qcom,sa8775p-ctcu

92
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@ -22,49 +22,69 @@ description: |
select:
properties:
# Select all nodes which have SoC-based compatibles, but not the root
# "/" node, because its front compatibles do not follow any SoC patterns
$nodename:
pattern: "[^/]"
compatible:
oneOf:
- pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,.*(glymur|milos).*$"
contains:
oneOf:
- pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra).*$"
required:
- compatible
properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
- pattern: "^qcom,(glymur|milos)-.*$"
contains:
anyOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
- pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$"
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,gpucc-sdm630
- qcom,gpucc-sdm660
- qcom,lcc-apq8064
- qcom,lcc-ipq8064
- qcom,lcc-mdm9615
- qcom,lcc-msm8960
- qcom,lpass-cpu-apq8016
- qcom,usb-ss-ipq4019-phy
- qcom,usb-hs-ipq4019-phy
- qcom,vqmmc-ipq4019-regulator
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,apss-wdt-[a-z]+$" # Codenames variant
- pattern: "^qcom,kpss-gcc-(apq|ipq|mdm|msm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,rpmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,rpm(cc)?-[a-z]+$" # Codenames variant
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sar?|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,scm-[a-z]+$" # Codenames variant
- pattern: "^qcom,tcsr-(apq|ipq|mdm|msm)[0-9]+.*$"
- pattern: "^qcom,usb-hs-phy-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,gpucc-sdm630
- qcom,gpucc-sdm660
- qcom,lcc-apq8064
- qcom,lcc-ipq8064
- qcom,lcc-mdm9615
- qcom,lcc-msm8960
- qcom,lpass-cpu-apq8016
- qcom,usb-hs-ipq4019-phy
- qcom,usb-hsic-phy-mdm9615
- qcom,usb-hsic-phy-msm8974
- qcom,usb-ss-ipq4019-phy
- qcom,vqmmc-ipq4019-regulator
# Legacy compatibles with wild-cards - list cannot grow with new bindings:
- enum:
- qcom,ipq806x-gmac
- qcom,ipq806x-nand
- qcom,ipq806x-sata-phy
- qcom,ipq806x-usb-phy-ss
- qcom,ipq806x-usb-phy-hs
# Legacy compatibles with wild-cards - list cannot grow with new bindings:
- enum:
- qcom,ipq806x-ahci
- qcom,ipq806x-gmac
- qcom,ipq806x-nand
- qcom,ipq806x-sata-phy
- qcom,ipq806x-usb-phy-ss
- qcom,ipq806x-usb-phy-hs
# In general non-SoC Qualcomm devices do not need to be listed here,
# however in a few cases they got selected by patterns in "select":
- pattern: "^qcom,wsa[0-9]+$"
additionalProperties: true

533
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -49,18 +49,36 @@ properties:
- qcom,apq8074-dragonboard
- const: qcom,apq8074
- items:
- enum:
- qcom,apq8060-dragonboard
- qcom,msm8660-surf
- const: qcom,msm8660
- items:
- enum:
- qcom,apq8084-mtp
- qcom,apq8084-sbc
- const: qcom,apq8084
- items:
- const: qcom,eliza-cqs-evk
- const: qcom,eliza-cqs-som
- const: qcom,eliza
- items:
- enum:
- sony,karin_windy
- const: qcom,apq8094
- items:
- enum:
- arrow,apq8096-db820c
- inforce,ifc6640
- const: qcom,apq8096-sbc
- const: qcom,apq8096
- items:
- const: arrow,apq8096sg-db820c
- const: arrow,apq8096-db820c
- const: qcom,apq8096-sbc
- const: qcom,apq8096sg
- const: qcom,apq8096
- items:
- enum:
- qcom,eliza-mtp
@ -71,11 +89,102 @@ properties:
- qcom,glymur-crd
- const: qcom,glymur
- items:
- enum:
- 8dev,jalapeno
- alfa-network,ap120c-ac
- const: qcom,ipq4018
- items:
- enum:
- qcom,ipq4019-ap-dk01.1-c1
- qcom,ipq4019-ap-dk04.1-c3
- qcom,ipq4019-ap-dk07.1-c1
- qcom,ipq4019-ap-dk07.1-c2
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
- items:
- enum:
- qcom,ipq5018-rdp432-c2
- tplink,archer-ax55-v1
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5210-rdp504
- const: qcom,ipq5210
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
- qcom,ipq5332-ap-mi01.3
- qcom,ipq5332-ap-mi01.6
- qcom,ipq5332-ap-mi01.9
- const: qcom,ipq5332
- items:
- enum:
- qcom,ipq5424-rdp466
- const: qcom,ipq5424
- items:
- enum:
- qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
- items:
- enum:
- mikrotik,rb3011
- qcom,ipq8064-ap148
- const: qcom,ipq8064
- items:
- enum:
- qcom,ipq8074-hk01
- qcom,ipq8074-hk10-c1
- qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
- items:
- enum:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c2-emmc
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
- qcom,ipq9574-ap-al02-c7-emmc
- qcom,ipq9574-ap-al02-c8
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
- items:
- enum:
- qcom,ipq9650-rdp488
- const: qcom,ipq9650
- items:
- enum:
- qcom,hawi-mtp
- const: qcom,hawi
- items:
- enum:
- qcom,kaanapali-mtp
- qcom,kaanapali-qrd
- const: qcom,kaanapali
- items:
- enum:
- qcom,mahua-crd
- const: qcom,mahua
- description: Sierra Wireless MangOH Green with WP8548 Module
items:
- const: swir,mangoh-green-wp8548
- const: swir,wp8548
- const: qcom,mdm9615
- items:
- enum:
- fairphone,fp6
@ -88,6 +197,7 @@ properties:
- microsoft,makepeace
- microsoft,moneypenny
- motorola,falcon
- motorola,titan
- samsung,ms013g
- samsung,s3ve3g
- const: qcom,msm8226
@ -99,14 +209,73 @@ properties:
- microsoft,tesla
- motorola,peregrine
- samsung,matisselte
- sony,eagle
- const: qcom,msm8926
- const: qcom,msm8226
- items:
- enum:
- qcom,apq8060-dragonboard
- qcom,msm8660-surf
- const: qcom,msm8660
- items:
- enum:
- acer,a1-724
- alcatel,idol347
- asus,z00l
- gplus,fl8005a
- huawei,g7
- lg,c50
- lg,m216
- longcheer,l8910
- longcheer,l8150
- motorola,harpia
- motorola,osprey
- motorola,surnia
- qcom,msm8916-mtp
- samsung,a3u-eur
- samsung,a5u-eur
- samsung,coreprimeltevzw
- samsung,e5
- samsung,e7
- samsung,fortuna3g
- samsung,gprimeltecan
- samsung,grandmax
- samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j3ltetw
- samsung,j5
- samsung,j5x
- samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wiko,chuppito
- wingtech,wt86518
- wingtech,wt86528
- wingtech,wt88047
- yiming,uz801-v3
- const: qcom,msm8916
- items:
- enum:
- xiaomi,riva
- xiaomi,rolex
- xiaomi,tiare
- const: qcom,msm8917
- items:
- enum:
- wingtech,wt82918hd
- const: qcom,msm8929
- items:
- enum:
- xiaomi,land
- const: qcom,msm8937
- items:
- enum:
- asus,z00t
@ -119,6 +288,16 @@ properties:
- wingtech,wt82918hdhw39
- const: qcom,msm8939
- items:
- enum:
- flipkart,rimob
- motorola,potter
- xiaomi,daisy
- xiaomi,mido
- xiaomi,tissot
- xiaomi,vince
- const: qcom,msm8953
- items:
- enum:
- sony,kugo-row
@ -170,68 +349,6 @@ properties:
- longcheer,l9360
- const: qcom,msm8976
- items:
- enum:
- acer,a1-724
- alcatel,idol347
- asus,z00l
- gplus,fl8005a
- huawei,g7
- lg,c50
- lg,m216
- longcheer,l8910
- longcheer,l8150
- motorola,harpia
- motorola,osprey
- motorola,surnia
- qcom,msm8916-mtp
- samsung,a3u-eur
- samsung,a5u-eur
- samsung,coreprimeltevzw
- samsung,e5
- samsung,e7
- samsung,fortuna3g
- samsung,gprimeltecan
- samsung,grandmax
- samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j3ltetw
- samsung,j5
- samsung,j5x
- samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wiko,chuppito
- wingtech,wt86518
- wingtech,wt86528
- wingtech,wt88047
- yiming,uz801-v3
- const: qcom,msm8916
- items:
- enum:
- xiaomi,riva
- xiaomi,rolex
- xiaomi,tiare
- const: qcom,msm8917
- items:
- enum:
- xiaomi,land
- const: qcom,msm8937
- items:
- enum:
- flipkart,rimob
- motorola,potter
- xiaomi,daisy
- xiaomi,mido
- xiaomi,tissot
- xiaomi,vince
- const: qcom,msm8953
- items:
- enum:
- lg,bullhead
@ -240,11 +357,6 @@ properties:
- xiaomi,libra
- const: qcom,msm8992
- items:
- enum:
- sony,karin_windy
- const: qcom,apq8094
- items:
- enum:
- huawei,angler
@ -256,20 +368,6 @@ properties:
- sony,suzuran-row
- const: qcom,msm8994
- items:
- enum:
- arrow,apq8096-db820c
- inforce,ifc6640
- const: qcom,apq8096-sbc
- const: qcom,apq8096
- items:
- const: arrow,apq8096sg-db820c
- const: arrow,apq8096-db820c
- const: qcom,apq8096-sbc
- const: qcom,apq8096sg
- const: qcom,apq8096
- items:
- enum:
- oneplus,oneplus3
@ -303,86 +401,6 @@ properties:
- xiaomi,sagit
- const: qcom,msm8998
- items:
- enum:
- 8dev,jalapeno
- alfa-network,ap120c-ac
- const: qcom,ipq4018
- items:
- enum:
- qcom,ipq4019-ap-dk01.1-c1
- qcom,ipq4019-ap-dk04.1-c3
- qcom,ipq4019-ap-dk07.1-c1
- qcom,ipq4019-ap-dk07.1-c2
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
- items:
- enum:
- qcom,ipq5018-rdp432-c2
- tplink,archer-ax55-v1
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5210-rdp504
- const: qcom,ipq5210
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
- qcom,ipq5332-ap-mi01.3
- qcom,ipq5332-ap-mi01.6
- qcom,ipq5332-ap-mi01.9
- const: qcom,ipq5332
- items:
- enum:
- qcom,ipq5424-rdp466
- const: qcom,ipq5424
- items:
- enum:
- mikrotik,rb3011
- qcom,ipq8064-ap148
- const: qcom,ipq8064
- items:
- enum:
- qcom,ipq8074-hk01
- qcom,ipq8074-hk10-c1
- qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
- items:
- enum:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c2-emmc
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
- qcom,ipq9574-ap-al02-c7-emmc
- qcom,ipq9574-ap-al02-c8
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
- items:
- enum:
- qcom,ipq9650-rdp488
- const: qcom,ipq9650
- items:
- enum:
- qcom,kaanapali-mtp
- qcom,kaanapali-qrd
- const: qcom,kaanapali
- description: Sierra Wireless MangOH Green with WP8548 Module
items:
- const: swir,mangoh-green-wp8548
- const: swir,wp8548
- const: qcom,mdm9615
- description: Qualcomm Technologies, Inc. Robotics RB1
items:
- enum:
@ -401,8 +419,23 @@ properties:
- shift,otter
- thundercomm,minipc-g1iot
- thundercomm,rubikpi3
- vicharak,axon-mini
- const: qcom,qcm6490
- items:
- enum:
- qcom,qcs404-evb-1000
- qcom,qcs404-evb-4000
- const: qcom,qcs404-evb
- const: qcom,qcs404
- items:
- enum:
- arduino,monza
- qcom,monaco-evk
- qcom,qcs8300-ride
- const: qcom,qcs8300
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
items:
- enum:
@ -416,6 +449,31 @@ properties:
- qcom,qru1000-idp
- const: qcom,qru1000
- items:
- enum:
- qcom,sa8155p-adp
- const: qcom,sa8155p
- items:
- enum:
- qcom,sa8295p-adp
- qcom,sa8540p-ride
- const: qcom,sa8540p
- items:
- enum:
- qcom,sa8775p-ride
- qcom,sa8775p-ride-r3
- const: qcom,sa8775p
- items:
- enum:
- qcom,lemans-evk
- qcom,qcs9100-ride
- qcom,qcs9100-ride-r3
- const: qcom,qcs9100
- const: qcom,sa8775p
- description: Qualcomm AR2 Gen1 platform
items:
- enum:
@ -828,14 +886,6 @@ properties:
- const: google,zombie-sku514
- const: qcom,sc7280
- description: Xiaomi Poco F1
items:
- enum:
- xiaomi,beryllium-ebbg
- xiaomi,beryllium-tianma
- const: xiaomi,beryllium
- const: qcom,sdm845
- items:
- enum:
- lenovo,flex-5g
@ -853,6 +903,11 @@ properties:
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
- items:
- enum:
- inforce,ifc6560
- const: qcom,sda660
- items:
- enum:
- lenovo,tbx605f
@ -867,11 +922,6 @@ properties:
- sony,voyager-row
- const: qcom,sdm630
- items:
- enum:
- inforce,ifc6560
- const: qcom,sda660
- items:
- enum:
- fairphone,fp3
@ -899,74 +949,13 @@ properties:
- const: google,bonito
- const: qcom,sdm670
- items:
- description: Xiaomi Poco F1
items:
- enum:
- qcom,sdx55-mtp
- qcom,sdx55-telit-fn980-tlb
- qcom,sdx55-t55
- const: qcom,sdx55
- items:
- enum:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,sdx75-idp
- const: qcom,sdx75
- items:
- enum:
- qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
- items:
- enum:
- qcom,qcs404-evb-1000
- qcom,qcs404-evb-4000
- const: qcom,qcs404-evb
- const: qcom,qcs404
- items:
- enum:
- arduino,monza
- qcom,monaco-evk
- qcom,qcs8300-ride
- const: qcom,qcs8300
- items:
- enum:
- qcom,qcs615-ride
- qcom,talos-evk
- const: qcom,qcs615
- const: qcom,sm6150
- items:
- enum:
- qcom,sa8155p-adp
- const: qcom,sa8155p
- items:
- enum:
- qcom,sa8295p-adp
- qcom,sa8540p-ride
- const: qcom,sa8540p
- items:
- enum:
- qcom,sa8775p-ride
- qcom,sa8775p-ride-r3
- const: qcom,sa8775p
- items:
- enum:
- qcom,lemans-evk
- qcom,qcs9100-ride
- qcom,qcs9100-ride-r3
- const: qcom,qcs9100
- const: qcom,sa8775p
- xiaomi,beryllium-ebbg
- xiaomi,beryllium-tianma
- const: xiaomi,beryllium
- const: qcom,sdm845
- items:
- enum:
@ -989,6 +978,41 @@ properties:
- xiaomi,polaris
- const: qcom,sdm845
- items:
- enum:
- qcom,shikra-cqm-evk
- const: qcom,shikra-cqm-som
- const: qcom,shikra
- items:
- enum:
- qcom,shikra-cqs-evk
- const: qcom,shikra-cqs-som
- const: qcom,shikra
- items:
- enum:
- qcom,shikra-iqs-evk
- const: qcom,shikra-iqs-som
- const: qcom,shikra
- items:
- enum:
- qcom,sdx55-mtp
- qcom,sdx55-telit-fn980-tlb
- qcom,sdx55-t55
- const: qcom,sdx55
- items:
- enum:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,sdx75-idp
- const: qcom,sdx75
- items:
- enum:
- oneplus,billie2
@ -1024,6 +1048,13 @@ properties:
- xiaomi,willow
- const: qcom,sm6125
- items:
- enum:
- qcom,qcs615-ride
- qcom,talos-evk
- const: qcom,qcs615
- const: qcom,sm6150
- items:
- enum:
- sony,pdx213
@ -1054,6 +1085,7 @@ properties:
- enum:
- motorola,dubai
- nothing,spacewar
- xiaomi,taoyao
- const: qcom,sm7325
- items:
@ -1112,6 +1144,12 @@ properties:
- const: qcom,qcs8550
- const: qcom,sm8550
- items:
- enum:
- qcom,qcs8550-rb5gen2
- const: qcom,qcs8550
- const: qcom,sm8550
- items:
- enum:
- ayaneo,pocket-s2
@ -1160,6 +1198,7 @@ properties:
- dell,inspiron-14-plus-7441
- dell,latitude-7455
- dell,xps13-9345
- honor,magicbook-art-14-snapdragon
- hp,elitebook-ultra-g1q
- hp,omnibook-x14
- lenovo,ideacentre-mini-01q8x10

63
Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View File

@ -19,35 +19,40 @@ description: |
properties:
compatible:
enum:
- qcom,eliza-llcc
- qcom,glymur-llcc
- qcom,hawi-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
- qcom,sa8775p-llcc
- qcom,sar1130p-llcc
- qcom,sar2130p-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,sdm670-llcc
- qcom,sdm845-llcc
- qcom,shikra-llcc
- qcom,sm6350-llcc
- qcom,sm7150-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
- qcom,sm8750-llcc
- qcom,x1e80100-llcc
oneOf:
- enum:
- qcom,eliza-llcc
- qcom,glymur-llcc
- qcom,hawi-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
- qcom,sa8775p-llcc
- qcom,sar1130p-llcc
- qcom,sar2130p-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,sdm670-llcc
- qcom,sdm845-llcc
- qcom,shikra-llcc
- qcom,sm6350-llcc
- qcom,sm7150-llcc
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
- qcom,sm8750-llcc
- qcom,x1e80100-llcc
- items:
- enum:
- qcom,maili-llcc
- const: qcom,hawi-llcc
reg:
minItems: 1

72
Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm EVA Clock & Reset Controller on Glymur SoC
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm EVA clock control module which supports the clocks, resets and
power domains for the EVA instances on Glymur SoC.
See also:
- include/dt-bindings/clock/qcom,glymur-evacc.h
properties:
compatible:
const: qcom,glymur-evacc
clocks:
items:
- description: Interface clock from GCC
- description: Board XO source
- description: Sleep clock source
power-domains:
items:
- description: MMCX power domain
- description: MXC power domain
required-opps:
description:
Required OPP nodes for the MMCX and MXC power domains.
items:
- description: MMCX performance point
- description: MXC performance point
required:
- compatible
- clocks
- power-domains
- required-opps
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,glymur-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ab00000 {
compatible = "qcom,glymur-evacc";
reg = <0x0ab00000 0x10000>;
clocks = <&gcc GCC_EVA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

65
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
View File

@ -21,35 +21,41 @@ description: |
properties:
compatible:
items:
- enum:
- qcom,rpmcc-apq8060
- qcom,rpmcc-apq8064
- qcom,rpmcc-ipq806x
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8937
- qcom,rpmcc-msm8940
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
- qcom,rpmcc-msm8992
- qcom,rpmcc-msm8994
- qcom,rpmcc-msm8996
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
- qcom,rpmcc-sm6375
- const: qcom,rpmcc
oneOf:
- items:
- enum:
- qcom,rpmcc-apq8060
- qcom,rpmcc-apq8064
- qcom,rpmcc-ipq806x
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8937
- qcom,rpmcc-msm8940
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
- qcom,rpmcc-msm8992
- qcom,rpmcc-msm8994
- qcom,rpmcc-msm8996
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
- qcom,rpmcc-sm6375
- const: qcom,rpmcc
- items:
- enum:
- qcom,rpmcc-shikra
- const: qcom,rpmcc-qcm2290
- const: qcom,rpmcc
'#clock-cells':
const: 1
@ -126,6 +132,7 @@ allOf:
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-shikra
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125

70
Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml Normal file
View File

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Global Clock & Reset Controller on Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Global clock control module provides the clocks, resets and power
domains on Qualcomm Shikra SoC platform.
See also: include/dt-bindings/clock/qcom,shikra-gcc.h
properties:
compatible:
const: qcom,shikra-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: EMAC0 sgmiiphy mac rclk source
- description: EMAC0 sgmiiphy mac tclk source
- description: EMAC1 sgmiiphy mac rclk source
- description: EMAC1 sgmiiphy mac tclk source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@1400000 {
compatible = "qcom,shikra-gcc";
reg = <0x01400000 0x1f0000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&emac0_sgmiiphy_rclk>,
<&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>,
<&pcie_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

3
Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
View File

@ -8,12 +8,14 @@ title: Qualcomm Camera Clock & Reset Controller on x1e80100
maintainers:
- Bryan O'Donoghue <bryan.odonoghue@linaro.org>
- Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on x1e80100.
See also:
include/dt-bindings/clock/qcom,glymur-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
@ -22,6 +24,7 @@ allOf:
properties:
compatible:
enum:
- qcom,glymur-camcc
- qcom,x1e80100-camcc
- qcom,x1p42100-camcc

1
Documentation/devicetree/bindings/sram/sram.yaml
View File

@ -35,6 +35,7 @@ properties:
- nvidia,tegra194-sysram
- nvidia,tegra234-sysram
- qcom,eliza-imem
- qcom,glymur-imem
- qcom,hawi-imem
- qcom,kaanapali-imem
- qcom,milos-imem

4
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -737,6 +737,8 @@ patternProperties:
description: Honestar Technologies Co., Ltd.
"^honeywell,.*":
description: Honeywell
"^honor,.*":
description: Honor Device Co., Ltd.
"^hoperf,.*":
description: Shenzhen Hope Microelectronics Co., Ltd.
"^hoperun,.*":
@ -1803,6 +1805,8 @@ patternProperties:
description: VIA Technologies, Inc.
"^vialab,.*":
description: VIA Labs, Inc.
"^vicharak,.*":
description: Vicharak Computers Pvt. Ltd.
"^vicor,.*":
description: Vicor Corporation
"^videostrong,.*":

2
arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi
View File

@ -87,7 +87,7 @@ gsbi7_uart_2pins: gsbi7-uart-2pins-state {
function = "gsbi7";
};
gsbi7_uart_4pins: gsbi7_uart_4pins-state {
gsbi7_uart_4pins: gsbi7-uart-4pins-state {
pins = "gpio82", "gpio83", "gpio84", "gpio85";
function = "gsbi7";
};

4
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
View File

@ -591,7 +591,7 @@ saw1: power-manager@2099000 {
nss_common: syscon@3000000 {
compatible = "syscon";
reg = <0x03000000 0x0000FFFF>;
reg = <0x03000000 0x0000ffff>;
};
usb3_0: usb@100f8800 {
@ -1241,7 +1241,7 @@ pcie@0 {
qsgmii_csr: syscon@1bb00000 {
compatible = "syscon";
reg = <0x1bb00000 0x000001FF>;
reg = <0x1bb00000 0x000001ff>;
};
lcc: clock-controller@28000000 {

2
arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi
View File

@ -15,7 +15,7 @@ / {
memory@48000000 {
device_type = "memory";
reg = <0x48000000 0x7F00000>;
reg = <0x48000000 0x7f00000>;
};
};

2
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
View File

@ -1866,7 +1866,7 @@ cci_i2c1_sleep: cci-i2c1-sleep-pins {
};
};
spi8_default: spi8_default-state {
spi8_default: spi8-default-state {
mosi-pins {
pins = "gpio45";
function = "blsp_spi8";

2
arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts
View File

@ -55,7 +55,7 @@ vph_pwr: vph-pwr-regulator {
regulator-max-microvolt = <3700000>;
};
vreg_bob_3p3: pmx65_bob {
vreg_bob_3p3: pmx65-bob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob_3p3";
regulator-min-microvolt = <3300000>;

19
arch/arm64/boot/dts/qcom/Makefile
View File

@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
@ -184,12 +185,14 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-vicharak-axon-mini.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-rb5gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
@ -216,8 +219,6 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb
sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb
sc7180-ecs-liva-qc710-el2-dtbs := sc7180-ecs-liva-qc710.dtb sc7180-el2.dtbo
@ -334,6 +335,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-huawei-matebook-e-2019.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
@ -348,7 +352,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-csot.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-tianma.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-xiaomi-taoyao.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
@ -401,6 +408,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb
talos-evk-el2-dtbs := talos-evk.dtb talos-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += talos-evk-el2.dtb
talos-evk-usb1-peripheral-dtbs := talos-evk.dtb talos-evk-usb1-peripheral.dtbo
dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb
dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtbo
@ -431,6 +442,8 @@ x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-elitebook-ultra-g1q.dtb x1e80100-hp-elitebook-ultra-g1q-el2.dtb
x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb
x1e80100-honor-magicbook-art-14-el2-dtbs := x1e80100-honor-magicbook-art-14.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-honor-magicbook-art-14.dtb x1e80100-honor-magicbook-art-14-el2.dtb
x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb
x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo
@ -457,3 +470,5 @@ x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb
x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb
x1p42100-microsoft-sp12in-el2-dtbs := x1p42100-microsoft-sp12in.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-microsoft-sp12in.dtb x1p42100-microsoft-sp12in-el2.dtb

2
arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso
View File

@ -4,5 +4,5 @@
/plugin/;
&usb {
dr_mode = "host";
dr_mode = "host";
};

14
arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "eliza-cqs-som.dtsi"
#include "eliza-evk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Eliza CQS EVK";
compatible = "qcom,eliza-cqs-evk", "qcom,eliza-cqs-som", "qcom,eliza";
};

399
arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi Normal file
View File

@ -0,0 +1,399 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "eliza.dtsi"
#include "pm7550ba-eliza.dtsi"
#include "pm7550-eliza.dtsi"
#include "pm8550vs-d-eliza.dtsi"
#include "pm8550vs-g-eliza.dtsi"
#include "pmr735d-eliza.dtsi"
#include "pmk8550-eliza.dtsi"
/ {
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
#clock-cells = <0>;
};
bi_tcxo_div2: bi-tcxo-div2-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-mult = <1>;
clock-div = <2>;
};
bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK_A>;
clock-mult = <1>;
clock-div = <2>;
};
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm7550-rpmh-regulators";
vdd-l1-supply = <&vreg_s3b>;
vdd-l2-l3-supply = <&vreg_s3b>;
vdd-l4-l5-supply = <&vreg_s2b>;
vdd-l6-supply = <&vreg_s2b>;
vdd-l7-supply = <&vreg_s1b>;
vdd-l8-supply = <&vreg_s1b>;
vdd-l9-l10-supply = <&vreg_s1b>;
vdd-l11-supply = <&vreg_s1b>;
vdd-l12-l14-supply = <&vreg_bob>;
vdd-l13-l16-supply = <&vreg_bob>;
vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>;
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-bob-supply = <&vph_pwr>;
qcom,pmic-id = "b";
vreg_s1b: smps1 {
regulator-name = "vreg_s1b";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s2b: smps2 {
regulator-name = "vreg_s2b";
regulator-min-microvolt = <375000>;
regulator-max-microvolt = <2744000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s3b: smps3 {
regulator-name = "vreg_s3b";
regulator-min-microvolt = <375000>;
regulator-max-microvolt = <2744000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s4b: smps4 {
regulator-name = "vreg_s4b";
regulator-min-microvolt = <2156000>;
regulator-max-microvolt = <2400000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b: ldo2 {
regulator-name = "vreg_l2b";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b: ldo3 {
regulator-name = "vreg_l3b";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4b: ldo4 {
regulator-name = "vreg_l4b";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b: ldo6 {
regulator-name = "vreg_l6b";
regulator-min-microvolt = <866000>;
regulator-max-microvolt = <958000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b: ldo7 {
regulator-name = "vreg_l7b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b: ldo8 {
regulator-name = "vreg_l8b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b: ldo9 {
regulator-name = "vreg_l9b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10b: ldo10 {
regulator-name = "vreg_l10b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b: ldo11 {
regulator-name = "vreg_l11b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b: ldo12 {
regulator-name = "vreg_l12b";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13b: ldo13 {
regulator-name = "vreg_l13b";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b: ldo14 {
regulator-name = "vreg_l14b";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b: ldo15 {
regulator-name = "vreg_l15b";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16b: ldo16 {
regulator-name = "vreg_l16b";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b: ldo17 {
regulator-name = "vreg_l17b";
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18b: ldo18 {
regulator-name = "vreg_l18b";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19b: ldo19 {
regulator-name = "vreg_l19b";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20b: ldo20 {
regulator-name = "vreg_l20b";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21b: ldo21 {
regulator-name = "vreg_l21b";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l22b: ldo22 {
regulator-name = "vreg_l22b";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l23b: ldo23 {
regulator-name = "vreg_l23b";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob: bob {
regulator-name = "vreg_bob";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pm8550vs-rpmh-regulators";
vdd-l1-supply = <&vreg_s1b>;
qcom,pmic-id = "d";
vreg_l1d: ldo1 {
regulator-name = "vreg_l1d";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pm8550vs-rpmh-regulators";
vdd-l1-supply = <&vreg_s2b>;
vdd-l3-supply = <&vreg_s2b>;
qcom,pmic-id = "g";
vreg_l1g: ldo1 {
regulator-name = "vreg_l1g";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3g: ldo3 {
regulator-name = "vreg_l3g";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-3 {
compatible = "qcom,pmr735d-rpmh-regulators";
vdd-l1-l2-l5-supply = <&vreg_s3b>;
vdd-l3-l4-supply = <&vreg_s2b>;
vdd-l6-supply = <&vreg_s1b>;
vdd-l7-supply = <&vreg_s3b>;
qcom,pmic-id = "k";
vreg_l1k: ldo1 {
regulator-name = "vreg_l1k";
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2k: ldo2 {
regulator-name = "vreg_l2k";
regulator-min-microvolt = <920000>;
regulator-max-microvolt = <969000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3k: ldo3 {
regulator-name = "vreg_l3k";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4k: ldo4 {
regulator-name = "vreg_l4k";
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5k: ldo5 {
regulator-name = "vreg_l5k";
regulator-min-microvolt = <866000>;
regulator-max-microvolt = <931000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6k: ldo6 {
regulator-name = "vreg_l6k";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7k: ldo7 {
regulator-name = "vreg_l7k";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <958000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&remoteproc_adsp {
firmware-name = "qcom/eliza/adsp.mbn",
"qcom/eliza/adsp_dtb.mbn";
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&vreg_l12b>;
vqmmc-supply = <&vreg_l1d>;
pinctrl-0 = <&sdc1_default>;
pinctrl-1 = <&sdc1_sleep>;
pinctrl-names = "default", "sleep";
mmc-hs400-1_8v;
mmc-hs200-1_8v;
non-removable;
supports-cqe;
no-sdio;
no-sd;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <20 4>, /* NFC SPI */
<111 2>, /* WCN UART1 */
<118 1>; /* NFC Secure I/O */
};

112
arch/arm64/boot/dts/qcom/eliza-evk.dtsi Normal file
View File

@ -0,0 +1,112 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/ {
aliases {
serial0 = &uart13;
};
chosen {
stdout-path = "serial0:115200n8";
};
pmic-glink {
compatible = "qcom,eliza-pmic-glink",
"qcom,sm8550-pmic-glink",
"qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
orientation-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_dp_qmpphy_out>;
};
};
};
};
};
};
&pm7550ba_eusb2_repeater {
vdd18-supply = <&vreg_l7b>;
vdd3-supply = <&vreg_l17b>;
};
&sdhc_2 {
vmmc-supply = <&vreg_l13b>;
vqmmc-supply = <&vreg_l23b>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdc2_default>, <&sd_cd>;
pinctrl-1 = <&sdc2_sleep>, <&sd_cd>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&tlmm {
sd_cd: sd-cd-state {
pins = "gpio58";
function = "gpio";
bias-pull-up;
};
};
&uart13 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb {
status = "okay";
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3g>;
vdda-pll-supply = <&vreg_l7k>;
status = "okay";
};
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
&usb_hsphy {
vdd-supply = <&vreg_l7k>;
vdda12-supply = <&vreg_l4b>;
phys = <&pm7550ba_eusb2_repeater>;
status = "okay";
};

44
arch/arm64/boot/dts/qcom/eliza-mtp.dts
View File

@ -11,6 +11,11 @@
#include "eliza.dtsi"
#include "pm7550ba-eliza.dtsi"
#include "pm7550-eliza.dtsi"
#include "pm8550vs-d-eliza.dtsi"
#include "pm8550vs-g-eliza.dtsi"
#include "pmr735d-eliza.dtsi"
#include "pmk8550-eliza.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Eliza MTP";
@ -479,6 +484,30 @@ &remoteproc_adsp {
status = "okay";
};
&spi8 {
status = "okay";
touchscreen@0 {
compatible = "goodix,gt9916";
reg = <0>;
interrupt-parent = <&tlmm>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
avdd-supply = <&vreg_l22b>;
spi-max-frequency = <1000000>;
touchscreen-size-x = <1080>;
touchscreen-size-y = <2400>;
pinctrl-0 = <&ts_irq>, <&ts_reset>;
pinctrl-names = "default";
};
};
&tlmm {
gpio-reserved-ranges = <20 4>, /* NFC SPI */
<111 2>, /* WCN UART1 */
@ -504,6 +533,21 @@ mdp_vsync: mdp-vsync-state {
drive-strength = <2>;
bias-pull-down;
};
ts_irq: ts-irq-state {
pins = "gpio13";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-disable;
};
ts_reset: ts-reset-state {
pins = "gpio16";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&uart13 {

149
arch/arm64/boot/dts/qcom/eliza.dtsi
View File

@ -17,6 +17,7 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@ -45,6 +46,7 @@ cpu0: cpu@0 {
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@ -76,6 +78,7 @@ cpu1: cpu@100 {
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
@ -94,6 +97,7 @@ cpu2: cpu@200 {
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
l2_2: l2-cache {
compatible = "cache";
@ -119,6 +123,7 @@ cpu3: cpu@300 {
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
l2_3: l2-cache {
compatible = "cache";
@ -144,6 +149,7 @@ cpu4: cpu@400 {
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
l2_4: l2-cache {
compatible = "cache";
@ -169,6 +175,7 @@ cpu5: cpu@500 {
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
l2_5: l2-cache {
compatible = "cache";
@ -194,6 +201,7 @@ cpu6: cpu@600 {
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
l2_6: l2-cache {
compatible = "cache";
@ -219,6 +227,7 @@ cpu7: cpu@700 {
dynamic-power-coefficient = <588>;
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
l2_7: l2-cache {
compatible = "cache";
@ -1232,8 +1241,6 @@ qupv3_1: geniqup@ac0000 {
#size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a80000 0x0 0x4000>;
@ -2014,6 +2021,46 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
label = "lpass";
qcom,remote-pid = <2>;
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1061 0x0>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
@ -2696,7 +2743,7 @@ lpass_ag_noc: interconnect@7e40000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,eliza-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x40000>,
reg = <0x0 0x0b220000 0x0 0x10000>,
<0x0 0x174000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
@ -3616,6 +3663,102 @@ cpufreq_hw: cpufreq@17d91000 {
#clock-cells = <1>;
};
pmu@24091000 {
compatible = "qcom,eliza-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0x0 0x24091000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&llcc_bwmon_opp_table>;
llcc_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
opp-0 {
opp-peak-kBps = <2188800>;
};
opp-1 {
opp-peak-kBps = <5414400>;
};
opp-2 {
opp-peak-kBps = <6220800>;
};
opp-3 {
opp-peak-kBps = <6835200>;
};
opp-4 {
opp-peak-kBps = <8371200>;
};
opp-5 {
opp-peak-kBps = <10944000>;
};
opp-6 {
opp-peak-kBps = <12748800>;
};
opp-7 {
opp-peak-kBps = <14745600>;
};
opp-8 {
opp-peak-kBps = <16896000>;
};
};
};
pmu@240b7400 {
compatible = "qcom,eliza-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x240b7400 0x0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
cpu_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
opp-0 {
opp-peak-kBps = <307200>;
};
opp-1 {
opp-peak-kBps = <5600000>;
};
opp-2 {
opp-peak-kBps = <8528000>;
};
opp-3 {
opp-peak-kBps = <11120000>;
};
opp-4 {
opp-peak-kBps = <14000000>;
};
opp-5 {
opp-peak-kBps = <14928000>;
};
opp-6 {
opp-peak-kBps = <17056000>;
};
};
};
gem_noc: interconnect@24100000 {
compatible = "qcom,eliza-gem-noc";
reg = <0x0 0x24100000 0x0 0x163080>;

415
arch/arm64/boot/dts/qcom/glymur-crd.dts
View File

@ -8,198 +8,9 @@
#include "glymur.dtsi"
#include "glymur-crd.dtsi"
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
compatible = "qcom,glymur-crd", "qcom,glymur";
pmic-glink {
compatible = "qcom,glymur-pmic-glink",
"qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_0_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_0_qmpphy_out>;
};
};
};
};
connector@1 {
compatible = "usb-c-connector";
reg = <1>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in1: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in1: endpoint {
remote-endpoint = <&usb_1_qmpphy_out>;
};
};
};
};
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_MISC_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&misc_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
touchpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
wakeup-source;
};
keyboard@3a {
compatible = "hid-over-i2c";
reg = <0x3a>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&kybd_default>;
pinctrl-names = "default";
wakeup-source;
};
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
touchscreen@38 {
compatible = "hid-over-i2c";
reg = <0x38>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&ts0_default>;
pinctrl-names = "default";
};
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";
ptn3222_0: redriver@43 {
compatible = "nxp,ptn3222";
reg = <0x43>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l8b_e0_1p50>;
vdd1v8-supply = <&vreg_l15b_e0_1p8>;
#phy-cells = <0>;
};
ptn3222_1: redriver@47 {
compatible = "nxp,ptn3222";
reg = <0x47>;
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l8b_e0_1p50>;
vdd1v8-supply = <&vreg_l15b_e0_1p8>;
#phy-cells = <0>;
};
};
&mdss {
status = "okay";
};
&mdss_dp0 {
@ -218,212 +29,22 @@ &mdss_dp1_out {
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
};
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
status = "okay";
aux-bus {
panel {
compatible = "samsung,atna60cl08", "samsung,atna33xc20";
enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
power-supply = <&vreg_edp_3p3>;
pinctrl-0 = <&edp_bl_en>;
pinctrl-names = "default";
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
};
};
};
};
};
&mdss_dp3_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&edp_panel_in>;
};
&mdss_dp3_phy {
vdda-phy-supply = <&vreg_l2f_e1_0p83>;
vdda-pll-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&pmh0110_f_e0_gpios {
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio6";
function = "normal";
bias-disable;
input-disable;
output-enable;
drive-push-pull;
power-source = <1>; /* 1.8 V */
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
};
&smb2370_j_e2_eusb2_repeater {
vdd18-supply = <&vreg_l15b_e0_1p8>;
vdd3-supply = <&vreg_l7b_e0_2p79>;
};
&smb2370_k_e2_eusb2_repeater {
vdd18-supply = <&vreg_l15b_e0_1p8>;
vdd3-supply = <&vreg_l7b_e0_2p79>;
};
&tlmm {
edp_bl_en: edp-bl-en-state {
pins = "gpio18";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
bias-disable;
};
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
bias-disable;
};
ts0_default: ts0-default-state {
int-n-pins {
pins = "gpio51";
function = "gpio";
bias-disable;
};
reset-n-pins {
pins = "gpio48";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
};
&usb_0 {
status = "okay";
};
&usb_0_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
&usb_0_hsphy {
vdd-supply = <&vreg_l3f_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&smb2370_j_e2_eusb2_repeater>;
status = "okay";
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l3f_e0_0p72>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
};
&usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in1>;
};
&usb_1_hsphy {
vdd-supply = <&vreg_l3f_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&smb2370_k_e2_eusb2_repeater>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l1h_e0_0p89>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
};
&usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in1>;
};
&usb_hs {
status = "okay";
};
&usb_hs_phy {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&ptn3222_1>;
status = "okay";
};
&usb_mp {
status = "okay";
};
&usb_mp_hsphy0 {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&ptn3222_0>;
status = "okay";
};
&usb_mp_hsphy1 {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
status = "okay";
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
&tcsr {
vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0_0p72>;
vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>;
vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0_0p72>;
vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0_0p72>;
vdda-qreftx0-0p9-supply = <&vreg_l3f_e0_0p72>;
vdda-qreftx0-1p2-supply = <&vreg_l4h_e0_1p2>;
vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>;
vdda-refgen3-0p9-supply = <&vreg_l2f_e0_0p82>;
vdda-refgen3-1p2-supply = <&vreg_l4h_e0_1p2>;
vdda-refgen4-0p9-supply = <&vreg_l1f_e1_0p82>;
vdda-refgen4-1p2-supply = <&vreg_l4f_e1_1p08>;
};

556
arch/arm64/boot/dts/qcom/glymur-crd.dtsi
View File

@ -11,6 +11,7 @@
#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
@ -22,6 +23,7 @@ aliases {
i2c0 = &i2c0;
i2c1 = &i2c4;
i2c2 = &i2c5;
i2c3 = &i2c9;
spi0 = &spi18;
};
@ -68,6 +70,101 @@ switch-lid {
};
};
pmic-glink {
compatible = "qcom,glymur-pmic-glink",
"qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_0_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_0_qmpphy_out>;
};
};
};
};
connector@1 {
compatible = "usb-c-connector";
reg = <1>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in1: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in1: endpoint {
remote-endpoint = <&usb_1_qmpphy_out>;
};
};
};
};
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_MISC_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&misc_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
@ -140,6 +237,54 @@ vreg_wwan: regulator-wwan {
pinctrl-names = "default";
};
sound {
compatible = "qcom,glymur-sndcard";
model = "GLYMUR-CRD";
audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
"TweeterLeft IN", "WSA WSA_SPK2 OUT",
"WooferRight IN", "WSA2 WSA_SPK1 OUT",
"TweeterRight IN", "WSA2 WSA_SPK2 OUT",
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"VA DMIC2", "vdd-micb",
"VA DMIC3", "vdd-micb";
wsa-dai-link {
link-name = "WSA Playback";
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&left_woofer>, <&left_tweeter>,
<&swr0 0>, <&lpass_wsamacro 0>,
<&right_woofer>, <&right_tweeter>,
<&swr3 0>, <&lpass_wsa2macro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
va-dai-link {
link-name = "VA Capture";
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
codec {
sound-dai = <&lpass_vamacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
@ -444,6 +589,160 @@ vreg_l4h_e0_1p2: ldo4 {
};
};
&i2c9 {
clock-frequency = <400000>;
status = "okay";
embedded-controller@76 {
compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec";
reg = <0x76>;
interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&ec_int_n_default>;
pinctrl-names = "default";
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
touchpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
wakeup-source;
};
keyboard@3a {
compatible = "hid-over-i2c";
reg = <0x3a>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&kybd_default>;
pinctrl-names = "default";
wakeup-source;
};
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";
ptn3222_0: redriver@43 {
compatible = "nxp,ptn3222";
reg = <0x43>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l8b_e0_1p50>;
vdd1v8-supply = <&vreg_l15b_e0_1p8>;
#phy-cells = <0>;
};
ptn3222_1: redriver@47 {
compatible = "nxp,ptn3222";
reg = <0x47>;
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l8b_e0_1p50>;
vdd1v8-supply = <&vreg_l15b_e0_1p8>;
#phy-cells = <0>;
};
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
touchscreen@38 {
compatible = "hid-over-i2c";
reg = <0x38>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&ts0_default>;
pinctrl-names = "default";
};
};
&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
qcom,dmic-sample-rate = <4800000>;
vdd-micb-supply = <&vreg_l1b_e0_1p8>;
};
&mdss {
status = "okay";
};
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
status = "okay";
aux-bus {
panel {
compatible = "samsung,atna60cl08", "samsung,atna33xc20";
enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
power-supply = <&vreg_edp_3p3>;
pinctrl-0 = <&edp_bl_en>;
pinctrl-names = "default";
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
};
};
};
};
};
&mdss_dp3_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&edp_panel_in>;
};
&mdss_dp3_phy {
vdda-phy-supply = <&vreg_l2f_e1_0p83>;
vdda-pll-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&pcie3b {
vddpe-3v3-supply = <&vreg_nvmesec>;
@ -451,11 +750,6 @@ &pcie3b {
pinctrl-names = "default";
};
&pcie3b_phy {
vdda-phy-supply = <&vreg_l3c_e1_0p89>;
vdda-pll-supply = <&vreg_l2c_e1_1p14>;
};
&pcie3b_port0 {
reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>;
@ -537,14 +831,6 @@ &pcie6_port0 {
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
};
&pmh0101_gpios {
nvme_reg_en: nvme-reg-en-state {
pins = "gpio14";
function = "normal";
bias-disable;
};
};
&pmh0110_f_e1_gpios {
nvme_sec_reg_en: nvme-reg-en-state {
pins = "gpio14";
@ -560,6 +846,25 @@ key_vol_up_default: key-vol-up-default-state {
output-disable;
bias-pull-up;
};
nvme_reg_en: nvme-reg-en-state {
pins = "gpio14";
function = "normal";
bias-disable;
};
};
&pmh0110_f_e0_gpios {
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio6";
function = "normal";
bias-disable;
input-disable;
output-enable;
drive-push-pull;
power-source = <1>; /* 1.8 V */
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
};
&pmk8850_rtc {
@ -585,17 +890,114 @@ &remoteproc_cdsp {
status = "okay";
};
&smb2370_j_e2_eusb2_repeater {
vdd18-supply = <&vreg_l15b_e0_1p8>;
vdd3-supply = <&vreg_l7b_e0_2p79>;
};
&smb2370_k_e2_eusb2_repeater {
vdd18-supply = <&vreg_l15b_e0_1p8>;
vdd3-supply = <&vreg_l7b_e0_2p79>;
};
&swr0 {
status = "okay";
/* WSA8845, Left Woofer */
left_woofer: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "WooferLeft";
vdd-1p8-supply = <&vreg_l15b_e0_1p8>;
vdd-io-supply = <&vreg_l18b_e0_1p2>;
qcom,port-mapping = <1 2 3 7 12 14>;
};
/* WSA8845, Left Tweeter */
left_tweeter: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "TweeterLeft";
vdd-1p8-supply = <&vreg_l15b_e0_1p8>;
vdd-io-supply = <&vreg_l18b_e0_1p2>;
qcom,port-mapping = <4 5 6 7 13 15>;
};
};
&swr3 {
status = "okay";
/* WSA8845, Right Woofer */
right_woofer: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "WooferRight";
vdd-1p8-supply = <&vreg_l15b_e0_1p8>;
vdd-io-supply = <&vreg_l18b_e0_1p2>;
qcom,port-mapping = <1 2 3 7 12 14>;
};
/* WSA8845, Right Tweeter */
right_tweeter: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "TweeterRight";
vdd-1p8-supply = <&vreg_l15b_e0_1p8>;
vdd-io-supply = <&vreg_l18b_e0_1p2>;
qcom,port-mapping = <4 5 6 7 13 15>;
};
};
&remoteproc_soccp {
firmware-name = "qcom/glymur/soccp.mbn",
"qcom/glymur/soccp_dtb.mbn";
};
&tlmm {
gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
<10 2>, /* OOB UART */
<44 4>; /* Security SPI (TPM) */
edp_bl_en: edp-bl-en-state {
pins = "gpio18";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
hall_int_n_default: hall-int-n-state {
pins = "gpio92";
function = "gpio";
bias-disable;
};
ec_int_n_default: ec-int-n-state {
pins = "gpio66";
function = "gpio";
bias-disable;
};
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
bias-disable;
};
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
@ -688,6 +1090,27 @@ wake-n-pins {
};
};
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
bias-disable;
};
ts0_default: ts0-default-state {
int-n-pins {
pins = "gpio51";
function = "gpio";
bias-disable;
};
reset-n-pins {
pins = "gpio48";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
wcn_wlan_bt_en: wcn-wlan-bt-en-state {
pins = "gpio116", "gpio117";
function = "gpio";
@ -726,3 +1149,110 @@ bluetooth {
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
};
};
&usb_0 {
status = "okay";
};
&usb_0_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
&usb_0_hsphy {
vdd-supply = <&vreg_l3f_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&smb2370_j_e2_eusb2_repeater>;
status = "okay";
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l3f_e0_0p72>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
};
&usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in1>;
};
&usb_1_hsphy {
vdd-supply = <&vreg_l3f_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&smb2370_k_e2_eusb2_repeater>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l1h_e0_0p89>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
};
&usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in1>;
};
&usb_hs {
status = "okay";
};
&usb_hs_phy {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&ptn3222_1>;
status = "okay";
};
&usb_mp {
status = "okay";
};
&usb_mp_hsphy0 {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&ptn3222_0>;
status = "okay";
};
&usb_mp_hsphy1 {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
status = "okay";
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};

1108
arch/arm64/boot/dts/qcom/glymur.dtsi
View File

File diff suppressed because it is too large Load Diff

16
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
View File

@ -839,6 +839,16 @@ eusb6_repeater: redriver@4f {
pinctrl-0 = <&eusb6_reset_n>;
pinctrl-names = "default";
};
embedded-controller@76 {
compatible = "qcom,hamoa-iot-evk-ec", "qcom,hamoa-crd-ec";
reg = <0x76>;
interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&ec_int_n_default>;
pinctrl-names = "default";
};
};
&i2c7 {
@ -1341,6 +1351,12 @@ right_tweeter: speaker@0,1 {
};
&tlmm {
ec_int_n_default: ec-int-n-state {
pins = "gpio66";
function = "gpio";
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";

284
arch/arm64/boot/dts/qcom/hamoa.dtsi
View File

@ -6,11 +6,13 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,x1e80100-camcc.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -474,16 +476,6 @@ gunyah_hyp_mem: gunyah-hyp@80000000 {
no-map;
};
hyp_elf_package_mem: hyp-elf-package@80800000 {
reg = <0x0 0x80800000 0x0 0x200000>;
no-map;
};
ncc_mem: ncc@80a00000 {
reg = <0x0 0x80a00000 0x0 0x400000>;
no-map;
};
cpucp_log_mem: cpucp-log@80e00000 {
reg = <0x0 0x80e00000 0x0 0x40000>;
no-map;
@ -504,11 +496,6 @@ tags_mem: tags-region@81400000 {
no-map;
};
xbl_dtlog_mem: xbl-dtlog@81a00000 {
reg = <0x0 0x81a00000 0x0 0x40000>;
no-map;
};
xbl_ramdump_mem: xbl-ramdump@81a40000 {
reg = <0x0 0x81a40000 0x0 0x1c0000>;
no-map;
@ -550,51 +537,6 @@ secdata_apss_mem: secdata-apss@81cff000 {
no-map;
};
pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
reg = <0x0 0x81e00000 0x0 0x100000>;
no-map;
};
gpu_prr_mem: gpu-prr@81f00000 {
reg = <0x0 0x81f00000 0x0 0x10000>;
no-map;
};
tpm_control_mem: tpm-control@81f10000 {
reg = <0x0 0x81f10000 0x0 0x10000>;
no-map;
};
usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
reg = <0x0 0x81f20000 0x0 0x10000>;
no-map;
};
pld_pep_mem: pld-pep@81f30000 {
reg = <0x0 0x81f30000 0x0 0x6000>;
no-map;
};
pld_gmu_mem: pld-gmu@81f36000 {
reg = <0x0 0x81f36000 0x0 0x1000>;
no-map;
};
pld_pdp_mem: pld-pdp@81f37000 {
reg = <0x0 0x81f37000 0x0 0x1000>;
no-map;
};
tz_stat_mem: tz-stat@82700000 {
reg = <0x0 0x82700000 0x0 0x100000>;
no-map;
};
xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
reg = <0x0 0x82800000 0x0 0xc00000>;
no-map;
};
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
reg = <0x0 0x84b00000 0x0 0x800000>;
no-map;
@ -2868,7 +2810,7 @@ usb_1_ss0_hsphy: phy@fd3000 {
reg = <0 0x00fd3000 0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
@ -3010,7 +2952,7 @@ usb_1_ss2_hsphy: phy@fde000 {
reg = <0 0x00fde000 0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
@ -4371,6 +4313,9 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
memory-region = <&adsp_rpc_remote_heap_mem>;
qcom,vmids = <QCOM_SCM_VMID_LPASS
QCOM_SCM_VMID_ADSP_HEAP>;
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
@ -5318,6 +5263,13 @@ usb_1_ss0: usb@a600000 {
resets = <&gcc GCC_USB30_PRIM_BCR>;
interconnects = <&usb_south_anoc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr",
"apps-usb";
wakeup-source;
iommus = <&apps_smmu 0x1420 0x0>;
@ -5550,6 +5502,22 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss: display-subsystem@ae00000 {
compatible = "qcom,x1e80100-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@ -6047,7 +6015,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>;
qcom,pdc-ranges = <0 480 42>, <42 251 5>,
<47 522 52>, <99 609 32>,
@ -6804,6 +6772,35 @@ data-pins {
};
};
ctcu@10001000 {
compatible = "qcom,x1e80100-ctcu", "qcom,sa8775p-ctcu";
reg = <0x0 0x10001000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ctcu_in0: endpoint {
remote-endpoint = <&etr0_out>;
};
};
port@1 {
reg = <1>;
ctcu_in1: endpoint {
remote-endpoint = <&etr1_out>;
};
};
};
};
stm@10002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x10002000 0x0 0x1000>,
@ -6829,6 +6826,7 @@ tpdm@10003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -6886,6 +6884,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -7018,12 +7017,129 @@ qdss_funnel_out: endpoint {
};
};
replicator@10046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x10046000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
qdss_rep_in: endpoint {
remote-endpoint = <&swao_rep_out0>;
};
};
};
out-ports {
port {
qdss_rep_out0: endpoint {
remote-endpoint = <&etr_rep_in>;
};
};
};
};
tmc_etr: tmc@10048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10048000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
iommus = <&apps_smmu 0x04e0 0x0>;
arm,scatter-gather;
in-ports {
port {
etr0_in: endpoint {
remote-endpoint = <&etr_rep_out0>;
};
};
};
out-ports {
port {
etr0_out: endpoint {
remote-endpoint = <&ctcu_in0>;
};
};
};
};
replicator@1004e000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x1004e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
etr_rep_in: endpoint {
remote-endpoint = <&qdss_rep_out0>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
etr_rep_out0: endpoint {
remote-endpoint = <&etr0_in>;
};
};
port@1 {
reg = <1>;
etr_rep_out1: endpoint {
remote-endpoint = <&etr1_in>;
};
};
};
};
tmc_etr1: tmc@1004f000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x1004f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
iommus = <&apps_smmu 0x0500 0x0>;
arm,scatter-gather;
arm,buffer-size = <0x400000>;
in-ports {
port {
etr1_in: endpoint {
remote-endpoint = <&etr_rep_out1>;
};
};
};
out-ports {
port {
etr1_out: endpoint {
remote-endpoint = <&ctcu_in1>;
};
};
};
};
tpdm@10800000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10800000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_tmess_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7043,6 +7159,7 @@ tpdm@1082c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dl_south_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7062,6 +7179,7 @@ tpdm@10841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -7081,6 +7199,7 @@ tpdm@10844000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_qm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7124,6 +7243,7 @@ cti@1098b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_cdsp_cscti";
};
tpdm@109d0000 {
@ -7132,6 +7252,7 @@ tpdm@109d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_lpass";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7152,6 +7273,7 @@ tpdm@10ac0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_gcc";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7172,6 +7294,7 @@ tpdm@10ac1000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rpdm_mxa";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7331,7 +7454,20 @@ swao_rep_in: endpoint {
};
out-ports {
port {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
swao_rep_out0: endpoint {
remote-endpoint = <&qdss_rep_in>;
};
};
port@1 {
reg = <1>;
swao_rep_out1: endpoint {
remote-endpoint = <&eud_in>;
};
@ -7406,6 +7542,7 @@ tpdm@10b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dl_south_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7425,6 +7562,7 @@ tpdm@10b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7444,6 +7582,7 @@ tpdm@10b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7463,6 +7602,7 @@ tpdm@10b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7482,6 +7622,7 @@ tpdm@10b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dlct";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7501,6 +7642,7 @@ tpdm@10b20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dlmm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7571,6 +7713,7 @@ tpdm@10c08000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7619,6 +7762,7 @@ tpdm@10c28000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ddr_lpi";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -7638,6 +7782,7 @@ tpdm@10c29000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7771,6 +7916,7 @@ tpdm@10c38000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7790,6 +7936,7 @@ tpdm@10c39000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_mx";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7886,6 +8033,7 @@ tpdm@10cc1000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -7990,6 +8138,7 @@ tpdm@10d08000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_7";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8009,6 +8158,7 @@ tpdm@10d09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_6";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8028,6 +8178,7 @@ tpdm@10d0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_5";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8047,6 +8198,7 @@ tpdm@10d0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_4";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8066,6 +8218,7 @@ tpdm@10d0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_3";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8085,6 +8238,7 @@ tpdm@10d0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_0";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8104,6 +8258,7 @@ tpdm@10d0e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_1";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -8123,6 +8278,7 @@ tpdm@10d0f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llcc_2";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;

15
arch/arm64/boot/dts/qcom/ipq5018.dtsi
View File

@ -229,6 +229,9 @@ ge_phy: ethernet-phy@7 {
compatible = "ethernet-phy-id004d.d0c0";
reg = <7>;
clocks = <&gcc GCC_GEPHY_RX_CLK>,
<&gcc GCC_GEPHY_TX_CLK>;
clock-names = "rx", "tx";
resets = <&gcc GCC_GEPHY_MISC_ARES>;
};
};
@ -256,7 +259,7 @@ cmn_pll: clock-controller@9b000 {
"sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
};
qfprom: qfprom@a0000 {
@ -453,6 +456,16 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x21000>;
};
pwm: pwm@1941010 {
compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm";
reg = <0x01941010 0x20>;
clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clock-rates = <100000000>;
#pwm-cells = <3>;
status = "disabled";
};
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000>;

24
arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
View File

@ -2,7 +2,7 @@
/*
* IPQ5332 RDP board common device tree source
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
@ -55,12 +55,32 @@ &blsp1_uart0 {
status = "okay";
};
/*
* The bootstrap pins for the board select the XO clock frequency that
* supports 48 MHZ or 96 MHZ. This setting automatically enables the
* right dividers, to ensure the reference clock output from WiFi to
* the CMN PLL is 48 MHZ.
*/
&ref_48mhz_clk {
clock-div = <1>;
clock-mult = <1>;
};
&sleep_clk {
clock-frequency = <32000>;
};
/*
* The frequency of xo_board is fixed to 24 MHZ, which is routed
* from WiFi output clock 48 MHZ divided by 2.
*/
&xo_board {
clock-frequency = <24000000>;
clock-div = <2>;
clock-mult = <1>;
};
&xo_clk {
clock-frequency = <48000000>;
};
/* PINCTRL */

16
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
View File

@ -36,9 +36,6 @@ &pcie0 {
pinctrl-0 = <&pcie0_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -46,13 +43,15 @@ &pcie0_phy {
status = "okay";
};
&pcie0_port0 {
reset-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
};
&pcie1 {
pinctrl-0 = <&pcie1_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -60,6 +59,11 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
};
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";

53
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -2,10 +2,11 @@
/*
* IPQ5332 device tree source
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq5332.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -16,12 +17,24 @@ / {
#size-cells = <2>;
clocks {
ref_48mhz_clk: ref-48mhz-clk {
compatible = "fixed-factor-clock";
clocks = <&xo_clk>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board: xo-board-clk {
compatible = "fixed-factor-clock";
clocks = <&ref_48mhz_clk>;
#clock-cells = <0>;
};
xo_clk: xo-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
@ -167,6 +180,20 @@ usbphy0: phy@7b000 {
status = "disabled";
};
cmn_pll: clock-controller@9b000 {
compatible = "qcom,ipq5332-cmn-pll";
reg = <0x0009b000 0x800>;
clocks = <&ref_48mhz_clk>,
<&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>;
clock-names = "ref",
"ahb",
"sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll IPQ5332_CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <6000000000>;
};
qfprom: efuse@a4000 {
compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x721>;
@ -334,6 +361,16 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x21000>;
};
pwm: pwm@1941010 {
compatible = "qcom,ipq5332-pwm", "qcom,ipq6018-pwm";
reg = <0x01941010 0x20>;
clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clock-rates = <100000000>;
#pwm-cells = <3>;
status = "disabled";
};
sdhc: mmc@7804000 {
compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
@ -704,19 +741,18 @@ pcie1: pcie@18000000 {
"aux",
"ahb";
phys = <&pcie1_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
<&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -808,19 +844,18 @@ pcie0: pcie@20000000 {
"aux",
"ahb";
phys = <&pcie0_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
<&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;

12
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
View File

@ -86,8 +86,6 @@ &pcie2 {
pinctrl-0 = <&pcie2_default_state>;
pinctrl-names = "default";
perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -95,12 +93,14 @@ &pcie2_phy {
status = "okay";
};
&pcie2_port0 {
reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
&pcie3 {
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -108,6 +108,10 @@ &pcie3_phy {
status = "okay";
};
&pcie3_port0 {
reset-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
};
&qusb_phy_0 {
vdd-supply = <&vreg_misc_0p925>;
vdda-pll-supply = <&vreg_misc_1p8>;

24
arch/arm64/boot/dts/qcom/ipq5424.dtsi
View File

@ -968,19 +968,19 @@ pcie3: pcie@40000000 {
"aux",
"ahb";
phys = <&pcie3_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
<&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie3_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie3_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -1071,19 +1071,19 @@ pcie2: pcie@50000000 {
"aux",
"ahb";
phys = <&pcie2_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
<&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie2_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -1174,19 +1174,19 @@ pcie1: pcie@60000000 {
"aux",
"ahb";
phys = <&pcie1_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
<&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -1277,19 +1277,19 @@ pcie0: pcie@70000000 {
"aux",
"ahb";
phys = <&pcie0_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
<&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;

10
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -413,6 +413,16 @@ tcsr: syscon@1937000 {
reg = <0x0 0x01937000 0x0 0x21000>;
};
pwm: pwm@1941010 {
compatible = "qcom,ipq6018-pwm";
reg = <0x0 0x01941010 0x0 0x20>;
clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clock-rates = <100000000>;
#pwm-cells = <3>;
status = "disabled";
};
usb2: usb@70f8800 {
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
reg = <0x0 0x070f8800 0x0 0x400>;

34
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -445,6 +445,16 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x21000>;
};
pwm: pwm@1941010 {
compatible = "qcom,ipq9574-pwm", "qcom,ipq6018-pwm";
reg = <0x01941010 0x20>;
clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clock-rates = <100000000>;
#pwm-cells = <3>;
status = "disabled";
};
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>,
@ -945,7 +955,8 @@ pcie1: pcie@10000000 {
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -953,7 +964,8 @@ pcie1: pcie@10000000 {
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@ -1031,7 +1043,8 @@ pcie3: pcie@18000000 {
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1039,7 +1052,8 @@ pcie3: pcie@18000000 {
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@ -1117,7 +1131,8 @@ pcie2: pcie@20000000 {
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1125,7 +1140,8 @@ pcie2: pcie@20000000 {
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@ -1202,7 +1218,8 @@ pcie0: pcie@28000000 {
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@ -1210,7 +1227,8 @@ pcie0: pcie@28000000 {
"msi4",
"msi5",
"msi6",
"msi7";
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;

58
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
View File

@ -163,6 +163,49 @@ platform {
};
};
pmic-glink {
compatible = "qcom,kaanapali-pmic-glink",
"qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_dp_qmpphy_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_sbu: endpoint {
};
};
};
};
};
wcd939x: audio-codec {
compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
@ -1076,6 +1119,11 @@ &remoteproc_cdsp {
status = "okay";
};
&remoteproc_soccp {
firmware-name = "qcom/kaanapali/soccp.mbn",
"qcom/kaanapali/soccp_dtb.mbn";
};
&sdhc_2 {
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
@ -1328,8 +1376,6 @@ &ufs_mem_phy {
};
&usb {
dr_mode = "peripheral";
status = "okay";
};
@ -1348,3 +1394,11 @@ &usb_dp_qmpphy {
status = "okay";
};
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};

58
arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
View File

@ -80,6 +80,49 @@ key-volume-up {
wakeup-source;
};
};
pmic-glink {
compatible = "qcom,kaanapali-pmic-glink",
"qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_dp_qmpphy_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_sbu: endpoint {
};
};
};
};
};
};
&apps_rsc {
@ -786,6 +829,11 @@ &remoteproc_cdsp {
status = "okay";
};
&remoteproc_soccp {
firmware-name = "qcom/kaanapali/soccp.mbn",
"qcom/kaanapali/soccp_dtb.mbn";
};
&tlmm {
gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
<74 1>, /* eSE */
@ -823,8 +871,6 @@ &ufs_mem_phy {
};
&usb {
dr_mode = "peripheral";
status = "okay";
};
@ -843,3 +889,11 @@ &usb_dp_qmpphy {
status = "okay";
};
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};

190
arch/arm64/boot/dts/qcom/kaanapali.dtsi
View File

@ -45,9 +45,9 @@ cpu0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 0>;
power-domains = <&cpu_pd0>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@ -62,9 +62,9 @@ cpu1: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 0>;
power-domains = <&cpu_pd1>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu2: cpu@200 {
@ -73,9 +73,9 @@ cpu2: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 0>;
power-domains = <&cpu_pd2>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu3: cpu@300 {
@ -84,9 +84,9 @@ cpu3: cpu@300 {
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 0>;
power-domains = <&cpu_pd3>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu4: cpu@400 {
@ -95,9 +95,9 @@ cpu4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 0>;
power-domains = <&cpu_pd4>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu5: cpu@500 {
@ -106,9 +106,9 @@ cpu5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 0>;
power-domains = <&cpu_pd5>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu6: cpu@10000 {
@ -117,9 +117,9 @@ cpu6: cpu@10000 {
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 1>;
power-domains = <&cpu_pd6>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_1: l2-cache {
compatible = "cache";
@ -134,9 +134,9 @@ cpu7: cpu@10100 {
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
clocks = <&pdp_scmi_perf 1>;
power-domains = <&cpu_pd7>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu-map {
@ -235,9 +235,9 @@ scmi: scmi {
#address-cells = <1>;
#size-cells = <0>;
pdp_scmi_perf: protocol@13 {
scmi_perf: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
};
};
@ -504,6 +504,32 @@ smp2p_cdsp_in: slave-kernel {
};
};
smp2p-soccp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <617>, <616>;
qcom,local-pid = <0>;
qcom,remote-pid = <19>;
soccp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
soccp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
compatible = "simple-bus";
@ -1513,6 +1539,55 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
};
};
remoteproc_soccp: remoteproc@d00000 {
compatible = "qcom,kaanapali-soccp-pas";
reg = <0x0 0x00d00000 0x0 0x200000>;
interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"pong";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MX>;
power-domain-names = "cx",
"mx";
memory-region = <&soccp_mem>,
<&soccp_dtb_mem>;
qcom,smem-states = <&soccp_smp2p_out 0>,
<&soccp_smp2p_out 8>;
qcom,smem-state-names = "stop",
"ping";
glink-edge {
interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <19>;
label = "soccp";
};
};
rng: rng@10c3000 {
compatible = "qcom,kaanapali-trng", "qcom,trng";
reg = <0x0 0x010c3000 0x0 0x1000>;
};
ipcc: mailbox@1106000 {
compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
reg = <0x0 0x01106000 0x0 0x1000>;
@ -2545,6 +2620,31 @@ ice: crypto@1d88000 {
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v2.0.0";
reg = <0x0 0x01dc4000 0x0 0x22000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&apps_smmu 0xc0 0x0>,
<&apps_smmu 0xc1 0x0>;
qcom,ee = <0>;
qcom,num-ees = <4>;
num-channels = <20>;
qcom,controlled-remotely;
};
crypto: crypto@1dfa000 {
compatible = "qcom,kaanapali-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "memory";
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0xc0 0x0>,
<&apps_smmu 0xc1 0x0>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
@ -3557,6 +3657,9 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
tx-fifo-resize;
dma-coherent;
usb-role-switch;
wakeup-source;
status = "disabled";
ports {
@ -4359,6 +4462,7 @@ tpdm@10003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
@ -4414,6 +4518,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
@ -4477,6 +4582,7 @@ tpdm@11000000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_modem_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4565,6 +4671,7 @@ tpdm@1102c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
@ -4583,6 +4690,7 @@ tpdm@11180000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4602,6 +4710,7 @@ tpdm@11183000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_cmsr1";
qcom,dsb-element-bits = <32>;
qcom,cmb-element-bits = <32>;
@ -4621,6 +4730,7 @@ tpdm@11184000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_cmsr2";
qcom,dsb-element-bits = <32>;
qcom,cmb-element-bits = <32>;
@ -4640,6 +4750,7 @@ tpdm@11185000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_dpm1";
qcom,cmb-element-bits = <64>;
@ -4658,6 +4769,7 @@ tpdm@11186000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_dpm2";
qcom,cmb-element-bits = <64>;
@ -4777,6 +4889,7 @@ tpdm@111a3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_pmu";
qcom,dsb-msrs-num = <32>;
@ -4795,6 +4908,7 @@ tpdm@111a4000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_qrng";
out-ports {
port {
@ -4811,6 +4925,7 @@ tpdm@111a5000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dlmm";
qcom,dsb-msrs-num = <32>;
@ -4829,6 +4944,7 @@ tpdm@111a6000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_north_dsb";
qcom,dsb-msrs-num = <32>;
@ -4847,6 +4963,7 @@ tpdm@111a7000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
@ -4865,6 +4982,7 @@ tpdm@111a8000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_cx";
out-ports {
port {
@ -4881,6 +4999,7 @@ tpdm@111a9000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_mxa";
out-ports {
port {
@ -4897,6 +5016,7 @@ tpdm@111aa000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_rdpm_mxc";
out-ports {
port {
@ -4913,6 +5033,7 @@ tpdm@111ab000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc_cmb0";
out-ports {
port {
@ -4929,6 +5050,7 @@ tpdm@111ac000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc_cmb1";
out-ports {
port {
@ -4945,6 +5067,7 @@ tpdm@111ad000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc_cmb2";
out-ports {
port {
@ -4961,6 +5084,7 @@ tpdm@111ae000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc_cmb3";
out-ports {
port {
@ -4977,6 +5101,7 @@ tpdm@111af000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipcc_cmb4";
out-ports {
port {
@ -4993,6 +5118,7 @@ tpdm@111b3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_pcie_rscc";
out-ports {
port {
@ -5182,6 +5308,7 @@ tpdm@111d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_qm";
out-ports {
port {
@ -5198,6 +5325,7 @@ tpdm@11303000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_4";
qcom,cmb-element-bits = <64>;
@ -5339,6 +5467,7 @@ tpdm@11309000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
@ -5357,6 +5486,7 @@ tpdm@1130a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
@ -5375,6 +5505,7 @@ tpdm@1130b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
@ -5393,6 +5524,7 @@ tpdm@1130c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
@ -5411,6 +5543,7 @@ tpdm@1130d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -5430,6 +5563,7 @@ tpdm@11422000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ipa";
qcom,dsb-msrs-num = <32>;
@ -7116,6 +7250,7 @@ timer {
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
label = "tpdm_cdsp_llm";
qcom,cmb-element-bits = <32>;
out-ports {
@ -7129,6 +7264,7 @@ tpdm_cdsp_llm_out: endpoint {
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
label = "tpdm_cdsp_llm2";
qcom,cmb-element-bits = <32>;
out-ports {
@ -7142,6 +7278,7 @@ tpdm_cdsp_llm2_out: endpoint {
tpdm-modem1 {
compatible = "qcom,coresight-static-tpdm";
label = "tpdm_modem_1";
qcom,cmb-element-bits = <32>;
out-ports {
@ -7155,6 +7292,7 @@ tpdm_modem1_out: endpoint {
tpdm-modem2 {
compatible = "qcom,coresight-static-tpdm";
label = "tpdm_modem_2";
qcom,cmb-element-bits = <64>;
out-ports {

36
arch/arm64/boot/dts/qcom/kodiak.dtsi
View File

@ -191,9 +191,12 @@ rmtfs_mem: rmtfs@9c900000 {
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
};
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 {
reg = <0x0 0x9cb80000 0x0 0x800000>;
no-map;
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x80000000 0x0 0x80000000>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
};
@ -2286,9 +2289,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc GCC_PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_clkreq_n>;
dma-coherent;
@ -2300,6 +2300,8 @@ pcie0_port: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -2416,9 +2418,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc GCC_PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>;
@ -2434,6 +2433,8 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -2646,6 +2647,9 @@ ipa: ipa@1e40000 {
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
sram = <&ipa_modem_tables>;
status = "disabled";
@ -3517,6 +3521,7 @@ tpdm@600f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -3536,6 +3541,7 @@ cti@6010000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_qdss";
};
funnel@6041000 {
@ -3685,6 +3691,7 @@ cti@6b00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_swao";
};
cti@6b01000 {
@ -3693,6 +3700,7 @@ cti@6b01000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_swao_1";
};
cti@6b02000 {
@ -3701,6 +3709,7 @@ cti@6b02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_swao_2";
};
cti@6b03000 {
@ -3709,6 +3718,7 @@ cti@6b03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_swao_3";
};
funnel@6b04000 {
@ -3863,6 +3873,7 @@ tpdm@6b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3882,6 +3893,7 @@ tpdm@6b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3901,6 +3913,7 @@ tpdm@6b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3920,6 +3933,7 @@ tpdm@6b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3939,6 +3953,7 @@ tpdm@6b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3958,6 +3973,7 @@ cti@6b11000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_aoss";
};
etm@7040000 {
@ -5743,7 +5759,7 @@ opp-810000000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,

104
arch/arm64/boot/dts/qcom/lemans-auto.dtsi
View File

@ -1,104 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include "lemans.dtsi"
/delete-node/ &pil_camera_mem;
/delete-node/ &pil_adsp_mem;
/delete-node/ &q6_adsp_dtb_mem;
/delete-node/ &q6_gdsp0_dtb_mem;
/delete-node/ &pil_gdsp0_mem;
/delete-node/ &pil_gdsp1_mem;
/delete-node/ &q6_gdsp1_dtb_mem;
/delete-node/ &q6_cdsp0_dtb_mem;
/delete-node/ &pil_cdsp0_mem;
/delete-node/ &pil_gpu_mem;
/delete-node/ &pil_cdsp1_mem;
/delete-node/ &q6_cdsp1_dtb_mem;
/delete-node/ &pil_cvp_mem;
/delete-node/ &pil_video_mem;
/delete-node/ &gunyah_md_mem;
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz_ffi_mem: tz-ffi@91c00000 {
compatible = "shared-dma-pool";
reg = <0x0 0x91c00000 0x0 0x1400000>;
no-map;
};
pil_camera_mem: pil-camera@95200000 {
reg = <0x0 0x95200000 0x0 0x500000>;
no-map;
};
pil_adsp_mem: pil-adsp@95c00000 {
reg = <0x0 0x95c00000 0x0 0x1e00000>;
no-map;
};
pil_gdsp0_mem: pil-gdsp0@97b00000 {
reg = <0x0 0x97b00000 0x0 0x1e00000>;
no-map;
};
pil_gdsp1_mem: pil-gdsp1@99900000 {
reg = <0x0 0x99900000 0x0 0x1e00000>;
no-map;
};
pil_cdsp0_mem: pil-cdsp0@9b800000 {
reg = <0x0 0x9b800000 0x0 0x1e00000>;
no-map;
};
pil_gpu_mem: pil-gpu@9d600000 {
reg = <0x0 0x9d600000 0x0 0x2000>;
no-map;
};
pil_cdsp1_mem: pil-cdsp1@9d700000 {
reg = <0x0 0x9d700000 0x0 0x1e00000>;
no-map;
};
pil_cvp_mem: pil-cvp@9f500000 {
reg = <0x0 0x9f500000 0x0 0x700000>;
no-map;
};
pil_video_mem: pil-video@9fc00000 {
reg = <0x0 0x9fc00000 0x0 0x700000>;
no-map;
};
audio_mdf_mem: audio-mdf-region@ae000000 {
reg = <0x0 0xae000000 0x0 0x1000000>;
no-map;
};
hyptz_reserved_mem: hyptz-reserved@beb00000 {
reg = <0x0 0xbeb00000 0x0 0x11500000>;
no-map;
};
trusted_apps_mem: trusted-apps@d1900000 {
reg = <0x0 0xd1900000 0x0 0x3800000>;
no-map;
};
};
firmware {
scm {
memory-region = <&tz_ffi_mem>;
};
};
};

2
arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso
View File

@ -14,7 +14,7 @@
#include <dt-bindings/gpio/gpio.h>
&{/} {
vreg_cam1_1p8: vreg_cam1_1p8 {
vreg_cam1_1p8: cam1-1p8-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_cam1_1p8";
startup-delay-us = <10000>;

251
arch/arm64/boot/dts/qcom/lemans-evk.dts
View File

@ -21,6 +21,7 @@ aliases {
ethernet0 = &ethernet0;
mmc1 = &sdhc;
serial0 = &uart10;
serial1 = &uart17;
serial2 = &uart0;
};
@ -63,12 +64,43 @@ port@1 {
reg = <1>;
usb0_con_ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
remote-endpoint = <&hd3ss3220_0_in_ep>;
};
};
};
};
connector-1 {
compatible = "usb-c-connector";
label = "USB1-Type-C";
data-role = "host";
power-role = "source";
vbus-supply = <&usb1_vbus>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb1_con_hs_ep: endpoint {
remote-endpoint = <&usb_hub_2_1>;
};
};
port@1 {
reg = <1>;
usb1_con_ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_1_in_ep>;
};
};
};
};
connector-2 {
compatible = "gpio-usb-b-connector", "usb-b-connector";
label = "micro-USB";
@ -88,6 +120,38 @@ usb2_con_hs_ep: endpoint {
};
};
connector-3 {
compatible = "pcie-m2-e-connector";
vpcie3v3-supply = <&vreg_wcn_3p3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
m2_e_pcie_ep: endpoint@0 {
reg = <0>;
remote-endpoint = <&pcieport0_ep>;
};
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
m2_e_uart_ep: endpoint@0 {
reg = <0>;
remote-endpoint = <&uart17_ep>;
};
};
};
};
edp0-connector {
compatible = "dp-connector";
label = "EDP0";
@ -161,6 +225,15 @@ usb0_vbus: regulator-usb0-vbus {
enable-active-high;
};
usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
gpio = <&expander1 3 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
};
usb2_vbus: regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
@ -178,6 +251,17 @@ vmmc_sdc: regulator-vmmc-sdc {
regulator-max-microvolt = <2950000>;
};
vreg_dcin_12v: regulator-dcin-12v {
compatible = "regulator-fixed";
regulator-name = "VREG_DCIN_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vreg_sdc: regulator-vreg-sdc {
compatible = "regulator-gpio";
@ -191,6 +275,19 @@ vreg_sdc: regulator-vreg-sdc {
startup-delay-us = <100>;
};
vreg_wcn_3p3: regulator-wcn-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_WCN_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vreg_dcin_12v>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
@ -551,7 +648,7 @@ ports {
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
hd3ss3220_0_in_ep: endpoint {
remote-endpoint = <&usb0_con_ss_ep>;
};
};
@ -559,12 +656,45 @@ hd3ss3220_in_ep: endpoint {
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
hd3ss3220_0_out_ep: endpoint {
remote-endpoint = <&usb_0_dwc3_ss>;
};
};
};
};
usb-typec@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupts-extended = <&pmm8654au_2_gpios 6 IRQ_TYPE_EDGE_FALLING>;
id-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb1_id>, <&usb1_intr>;
pinctrl-names = "default";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_1_in_ep: endpoint {
remote-endpoint = <&usb1_con_ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_1_out_ep: endpoint {
remote-endpoint = <&usb_hub_3_1>;
};
};
};
};
};
&i2c18 {
@ -742,6 +872,14 @@ &pcie1_phy {
status = "okay";
};
&pcieport0 {
port {
pcieport0_ep: endpoint {
remote-endpoint = <&m2_e_pcie_ep>;
};
};
};
&pmm8654au_0_pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@ -756,6 +894,14 @@ usb0_intr_state: usb0-intr-state {
power-source = <0>;
};
usb1_intr: usb1-intr-state {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
power-source = <0>;
};
usb2_id: usb2-id-state {
pins = "gpio11";
function = "normal";
@ -956,6 +1102,12 @@ usb_id: usb-id-state {
function = "gpio";
bias-pull-up;
};
usb1_id: usb1-id-state {
pins = "gpio51";
function = "gpio";
bias-pull-up;
};
};
&uart0 {
@ -970,6 +1122,16 @@ &uart10 {
status = "okay";
};
&uart17 {
status = "okay";
port {
uart17_ep: endpoint {
remote-endpoint = <&m2_e_uart_ep>;
};
};
};
&ufs_mem_hc {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
@ -996,7 +1158,7 @@ &usb_0_dwc3_hs {
};
&usb_0_dwc3_ss {
remote-endpoint = <&hd3ss3220_out_ep>;
remote-endpoint = <&hd3ss3220_0_out_ep>;
};
&usb_0_hsphy {
@ -1014,6 +1176,87 @@ &usb_0_qmpphy {
status = "okay";
};
&usb_1 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb_hub_2_x: hub@1 {
compatible = "usb5e3,610";
reg = <1>;
peer-hub = <&usb_hub_3_x>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
usb_hub_2_1: endpoint {
remote-endpoint = <&usb1_con_hs_ep>;
};
};
/*
* Port-4 is connected to M.2 E key connector on corekit.
*/
port@4 {
reg = <4>;
usb_hub_2_4: endpoint {
};
};
};
};
usb_hub_3_x: hub@2 {
compatible = "usb5e3,625";
reg = <2>;
peer-hub = <&usb_hub_2_x>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
usb_hub_3_1: endpoint {
remote-endpoint = <&hd3ss3220_1_out_ep>;
};
};
port@4 {
reg = <4>;
usb_hub_3_4: endpoint {
};
};
};
};
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
status = "okay";
};
&usb_2 {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
View File

@ -63,7 +63,7 @@ vreg_3p3: vreg-3p3-regulator {
regulator-max-microvolt = <3300000>;
};
vreg_conn_1p8: vreg_conn_1p8 {
vreg_conn_1p8: vreg-conn-1p8-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_1p8";
startup-delay-us = <4000>;
@ -71,7 +71,7 @@ vreg_conn_1p8: vreg_conn_1p8 {
gpio = <&pmm8654au_1_gpios 4 GPIO_ACTIVE_HIGH>;
};
vreg_conn_pa: vreg_conn_pa {
vreg_conn_pa: vreg-conn-pa-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_pa";
startup-delay-us = <4000>;

55
arch/arm64/boot/dts/qcom/lemans.dtsi
View File

@ -297,17 +297,7 @@ core3 {
idle-states {
entry-method = "psci";
gold_cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <549>;
exit-latency-us = <901>;
min-residency-us = <1774>;
local-timer-stop;
};
gold_rail_cpu_sleep_0: cpu-sleep-1 {
gold_rail_cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -566,57 +556,49 @@ psci {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_0_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster_1_pd>;
domain-idle-states = <&gold_cpu_sleep_0>,
<&gold_rail_cpu_sleep_0>;
domain-idle-states = <&gold_rail_cpu_sleep_0>;
};
cluster_0_pd: power-domain-cluster0 {
@ -1041,7 +1023,7 @@ qfprom: efuse@784000 {
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@240c {
gpu_speed_bin: gpu-speed-bin@240c {
reg = <0x240c 0x1>;
bits = <0 8>;
};
@ -2779,6 +2761,7 @@ pcie0: pcie@1c00000 {
status = "disabled";
pcieport0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@ -3197,6 +3180,7 @@ tpdm@4003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -3256,6 +3240,7 @@ tpdm@400f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -3724,6 +3709,7 @@ tpdm@4b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3744,6 +3730,7 @@ tpdm@4b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3764,6 +3751,7 @@ tpdm@4b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3784,6 +3772,7 @@ tpdm@4b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3804,6 +3793,7 @@ tpdm@4b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3824,6 +3814,7 @@ aoss_cti: cti@4b13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_aoss";
};
funnel@4b83000 {
@ -4145,6 +4136,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_actpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -4165,6 +4157,7 @@ tpdm@6861000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4247,6 +4240,7 @@ tpdm@68a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -4267,6 +4261,7 @@ tpdm@68b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -4287,6 +4282,7 @@ tpdm@68c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llm_ext";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -5873,7 +5869,7 @@ dispcc0: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
reg = <0x0 0x0b220000 0x0 0x10000>,
<0x0 0x17c000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 40>,
<40 140 14>,
@ -9179,6 +9175,7 @@ arch_timer: timer {
turing-llm-tpdm {
compatible = "qcom,coresight-static-tpdm";
label = "tpdm_cdsp_llm_0";
qcom,cmb-element-bits = <32>;

16
arch/arm64/boot/dts/qcom/mahua-crd.dts
View File

@ -19,3 +19,19 @@ / {
model = "Qualcomm Technologies, Inc. Mahua CRD";
compatible = "qcom,mahua-crd", "qcom,mahua";
};
&tcsr {
vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrpt3-0p9-supply = <&vreg_l1f_e1_0p82>;
vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>;
vdda-qrefrpt5-0p9-supply = <&vreg_l2h_e0_0p72>;
vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>;
vdda-qrefrx3-0p9-supply = <&vreg_l2h_e0_0p72>;
vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>;
vdda-refgen3-0p9-supply = <&vreg_l1f_e1_0p82>;
vdda-refgen3-1p2-supply = <&vreg_l4f_e1_1p08>;
};

13
arch/arm64/boot/dts/qcom/mahua.dtsi
View File

@ -115,6 +115,15 @@ &oobm_ss_noc {
compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc";
};
&pcie5_phy {
clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>,
<&gcc GCC_PCIE_5_CFG_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_5_PIPE_CLK>,
<&gcc GCC_PCIE_5_PIPE_DIV2_CLK>;
};
&pcie_east_anoc {
compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc";
};
@ -286,6 +295,10 @@ gpuss-4-critical {
};
};
&tcsr {
compatible = "qcom,mahua-tcsr", "syscon";
};
&tlmm {
compatible = "qcom,mahua-tlmm";
};

29
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
View File

@ -449,16 +449,16 @@ vreg_l2c: ldo2 {
regulators-2 {
compatible = "qcom,pmr735b-rpmh-regulators";
vdd-l1-l2-supply= <&vreg_s3b>;
vdd-l3-supply= <&vreg_s3b>;
vdd-l4-supply= <&vreg_s1b>;
vdd-l5-supply= <&vreg_s2b>;
vdd-l6-supply= <&vreg_s2b>;
vdd-l7-l8-supply= <&vreg_s2b>;
vdd-l9-supply= <&vreg_s3b>;
vdd-l10-supply= <&vreg_s1b>;
vdd-l11-supply= <&vreg_s3b>;
vdd-l12-supply= <&vreg_s3b>;
vdd-l1-l2-supply = <&vreg_s3b>;
vdd-l3-supply = <&vreg_s3b>;
vdd-l4-supply = <&vreg_s1b>;
vdd-l5-supply = <&vreg_s2b>;
vdd-l6-supply = <&vreg_s2b>;
vdd-l7-l8-supply = <&vreg_s2b>;
vdd-l9-supply = <&vreg_s3b>;
vdd-l10-supply = <&vreg_s1b>;
vdd-l11-supply = <&vreg_s3b>;
vdd-l12-supply = <&vreg_s3b>;
qcom,pmic-id = "f";
@ -700,6 +700,15 @@ vibrator@5a {
};
};
&ipa {
firmware-name = "qcom/milos/fairphone/fp6/ipa_fws.mbn";
memory-region = <&ipa_fw_mem>;
qcom,gsi-loader = "self";
status = "okay";
};
&pm8550vs_c {
status = "okay";
};

38
arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts
View File

@ -25,31 +25,7 @@ aliases {
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0:115200n8";
framebuffer0: framebuffer@e3940000 {
compatible = "simple-framebuffer";
reg = <0x0 0xe3940000 0x0 (2392 * 1080 * 4)>;
width = <1080>;
height = <2392>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
panel = <&panel>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
clocks = <&gcc GCC_DISP_HF_AXI_CLK>;
/* Dummy panel for simple-framebuffer dimension info */
panel: dummy-panel {
compatible = "boe,bf068mwm-td0";
height-mm = <157>;
width-mm = <71>;
};
};
};
gpio-keys {
@ -131,15 +107,6 @@ ramoops@81f20000 {
mem-type = <2>;
pmsg-size = <0x200000>;
};
/*
* ABL is powering down display and controller if this node is
* not named exactly "splash_region".
*/
splash_region@e3940000 {
reg = <0x0 0xe3940000 0x0 0x2b00000>;
no-map;
};
};
};
@ -507,11 +474,6 @@ vreg_l12f: ldo12 {
};
};
&dispcc {
/* Disable for now so simple-framebuffer continues working */
status = "disabled";
};
&gcc {
protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,

282
arch/arm64/boot/dts/qcom/milos.dtsi
View File

@ -3,6 +3,7 @@
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
*/
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,milos-camcc.h>
#include <dt-bindings/clock/qcom,milos-dispcc.h>
#include <dt-bindings/clock/qcom,milos-gcc.h>
@ -1647,6 +1648,50 @@ adreno_smmu: iommu@3da0000 {
dma-coherent;
};
ipa: ipa@3f40000 {
compatible = "qcom,milos-ipa";
reg = <0x0 0x03f40000 0x0 0x10000>,
<0x0 0x03f50000 0x0 0x5000>,
<0x0 0x03e04000 0x0 0xfc000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>,
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>,
<&smp2p_ipa_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_ipa_in 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ipa",
"gsi",
"ipa-clock-query",
"ipa-setup-ready";
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc_main SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "memory",
"config";
iommus = <&apps_smmu 0x4a0 0x0>,
<&apps_smmu 0x4a2 0x0>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_ipa_out 0>,
<&smp2p_ipa_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
sram = <&ipa_modem_tables>;
status = "disabled";
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,milos-mpss-pas";
reg = <0x0 0x04080000 0x0 0x10000>;
@ -1724,6 +1769,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
iommus = <&apps_smmu 0x540 0>;
resets = <&gcc GCC_SDCC2_BCR>;
bus-width = <4>;
qcom,dll-config = <0x0007442c>;
@ -1971,11 +2018,220 @@ camcc: clock-controller@adb0000 {
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
&mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss: display-subsystem@ae00000 {
compatible = "qcom,milos-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
reg-names = "mdss";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
iommus = <&apps_smmu 0x1c00 0x2>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,milos-dpu";
reg = <0x0 0x0ae01000 0x0 0x8f000>,
<0x0 0x0aeb0000 0x0 0x3000>;
reg-names = "mdp",
"vbif";
interrupts-extended = <&mdss 0>;
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_CX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-342000000 {
opp-hz = /bits/ 64 <342000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-402000000 {
opp-hz = /bits/ 64 <402000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-535000000 {
opp-hz = /bits/ 64 <535000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
required-opps = <&rpmhpd_opp_nom_l1>;
};
opp-630000000 {
opp-hz = /bits/ 64 <630000000>;
required-opps = <&rpmhpd_opp_turbo>;
};
};
};
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae94000 0x0 0x1000>;
reg-names = "dsi_ctrl";
interrupts-extended = <&mdss 4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd RPMHPD_CX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
mdss_dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
mdss_dsi0_phy: phy@ae95000 {
compatible = "qcom,milos-dsi-phy-4nm";
reg = <0x0 0x0ae95000 0x0 0x200>,
<0x0 0x0ae95200 0x0 0x300>,
<0x0 0x0ae95500 0x0 0x400>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"ref";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
};
dispcc: clock-controller@af00000 {
compatible = "qcom,milos-dispcc";
reg = <0x0 0x0af00000 0x0 0x20000>;
@ -1984,8 +2240,8 @@ dispcc: clock-controller@af00000 {
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<0>, /* dsi0_phy_pll_out_byteclk */
<0>, /* dsi0_phy_pll_out_dsiclk */
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<0>, /* dp0_phy_pll_link_clk */
<0>; /* dp0_phy_pll_vco_div_clk */
@ -1996,7 +2252,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,milos-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
reg = <0x0 0x0b220000 0x0 0x10000>,
<0x0 0x174000f0 0x0 0x64>;
interrupt-parent = <&intc>;
@ -2337,6 +2593,26 @@ scl-pins {
};
};
sram@14680000 {
compatible = "qcom,milos-imem", "mmio-sram";
reg = <0x0 0x14680000 0x0 0x2c000>;
ranges = <0x0 0x0 0x14680000 0x2c000>;
no-memory-wc;
#address-cells = <1>;
#size-cells = <1>;
pil-reloc-sram@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
ipa_modem_tables: modem-tables-sram@3000 {
reg = <0x3000 0x2000>;
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;

120
arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
View File

@ -7,10 +7,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "monaco.dtsi"
#include "monaco-pmics.dtsi"
#include "monaco-monza-som.dtsi"
/ {
@ -118,6 +117,22 @@ platform {
sound-dai = <&q6apm>;
};
};
displayport-0-dai-link {
link-name = "DisplayPort0 Playback";
codec {
sound-dai = <&mdss_dp0>;
};
cpu {
sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
vdc_3v3: regulator-3v3 {
@ -156,6 +171,26 @@ vreg_nvme: regulator-3p3-m2 {
};
};
&cci1 {
status = "okay";
};
&cci1_i2c1 {
fan_controller: fan-controller@2f {
compatible = "microchip,emc2305";
reg = <0x2f>;
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <3>;
fan: fan@0 {
reg = <0x0>;
pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>;
#cooling-cells = <2>;
};
};
};
&ethernet0 {
phy-mode = "2500base-x";
phy-handle = <&hsgmii_phy0>;
@ -246,6 +281,46 @@ &i2c12 {
status = "okay";
typec@8 {
compatible = "cypress,cypd4226";
reg = <0x08>;
pinctrl-0 = <&typec_default_state>;
pinctrl-names = "default";
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
label = "USB-C";
data-role = "dual";
power-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ucsi_hs_ccg_p0: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
port@1 {
reg = <1>;
ucsi_ss_ccg_p0: endpoint {
remote-endpoint = <&usb_1_dwc3_ss>;
};
};
};
};
};
max98091: audio-codec@10 {
compatible = "maxim,max98091";
reg = <0x10>;
@ -291,6 +366,12 @@ adv7535_out: endpoint {
};
};
};
power-sensor@40 {
compatible = "ti,ina232";
reg = <0x40>;
shunt-resistor = <2000>;
};
};
&mdss {
@ -369,6 +450,27 @@ &pcieport1 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
};
&thermal_zones {
cpuss-0-0-thermal {
polling-delay = <2000>;
trips {
cpuss0_active: cpuss-active {
temperature = <32000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map-active {
trip = <&cpuss0_active>;
cooling-device = <&fan 0 THERMAL_NO_LIMIT>;
};
};
};
};
&tlmm {
pcie0_default_state: pcie0-default-state {
wake-pins {
@ -393,6 +495,12 @@ perst-pins {
};
};
typec_default_state: typec-default-state {
pins = "gpio3";
function = "gpio";
bias-disable;
};
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";
@ -469,6 +577,14 @@ &usb_1 {
status = "okay";
};
&usb_1_dwc3_hs {
remote-endpoint = <&ucsi_hs_ccg_p0>;
};
&usb_1_dwc3_ss {
remote-endpoint = <&ucsi_ss_ccg_p0>;
};
/* Internally connected to the MCU (e.g. for DFU). */
&usb_2 {
dr_mode = "host";

85
arch/arm64/boot/dts/qcom/monaco.dtsi
View File

@ -309,16 +309,6 @@ idle-states {
entry-method = "psci";
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <449>;
exit-latency-us = <801>;
min-residency-us = <1574>;
local-timer-stop;
};
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -329,16 +319,6 @@ little_cpu_sleep_1: cpu-sleep-0-1 {
};
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <549>;
exit-latency-us = <901>;
min-residency-us = <1774>;
local-timer-stop;
};
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@ -681,49 +661,49 @@ psci {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd0>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd0>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd0>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd0>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd1>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd1>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd1>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd1>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>;
};
cluster_pd0: power-domain-cluster0 {
@ -2927,7 +2907,7 @@ ws-pins {
};
};
lpi_i2s4_active: lpi_i2s4-active-state {
lpi_i2s4_active: lpi-i2s4-active-state {
data0-pins {
pins = "gpio17";
function = "i2s4_data";
@ -3017,14 +2997,6 @@ in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
swao_rep_out0: endpoint {
remote-endpoint = <&qdss_rep_in>;
};
};
port@1 {
reg = <1>;
@ -3049,6 +3021,7 @@ tpdm@400f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -3311,6 +3284,7 @@ tpdm@4841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -3330,6 +3304,7 @@ tpdm@4850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_pimem";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3351,6 +3326,7 @@ tpdm@4860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dl_ch_south";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3444,6 +3420,7 @@ tpdm@4980000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3487,6 +3464,7 @@ tpdm@4ac0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_mmnoc_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3559,6 +3537,7 @@ tpdm@4ad0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dlct";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3734,6 +3713,14 @@ out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
swao_rep_out0: endpoint {
remote-endpoint = <&qdss_rep_in>;
};
};
port@1 {
reg = <1>;
@ -3811,6 +3798,7 @@ tpdm@4b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3830,6 +3818,7 @@ tpdm@4b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3849,6 +3838,7 @@ tpdm@4b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3868,6 +3858,7 @@ tpdm@4b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -3887,6 +3878,7 @@ tpdm@4b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3906,6 +3898,7 @@ cti@4b13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_aoss";
};
tpdm@4b80000 {
@ -3914,6 +3907,7 @@ tpdm@4b80000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_cdsp_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -3981,6 +3975,7 @@ cti@4b8b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_cdsp_1";
};
tpdm@4c40000 {
@ -3989,6 +3984,7 @@ tpdm@4c40000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_gpdsp_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4082,6 +4078,7 @@ tpdm@4c50000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_dl_south";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4154,6 +4151,7 @@ tpdm@4e00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ddr";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4244,6 +4242,7 @@ tpdm@4e10000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ddr_ch0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4287,6 +4286,7 @@ tpdm@4e20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ddr_ch1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4612,6 +4612,7 @@ cti@682b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_apss";
};
tpdm@6860000 {
@ -4620,6 +4621,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_actpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@ -4639,6 +4641,7 @@ tpdm@6861000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4719,6 +4722,7 @@ tpdm@68a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -4738,6 +4742,7 @@ tpdm@68b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@ -4757,6 +4762,7 @@ tpdm@68c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "tpdm_ext_dsb";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@ -4776,6 +4782,7 @@ cti@68e0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_llm_gold";
};
cti@68f0000 {
@ -4784,6 +4791,7 @@ cti@68f0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_llm_silver";
};
cti@6900000 {
@ -4792,6 +4800,7 @@ cti@6900000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
label = "cti_ext_dsb";
};
sdhc_1: mmc@87c4000 {
@ -6077,7 +6086,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,qcs8300-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>,
reg = <0x0 0xb220000 0x0 0x10000>,
<0x0 0x17c000f0 0x0 0x64>;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;

138
arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
View File

@ -47,9 +47,18 @@ framebuffer@90001000 {
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_key_default>;
pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_key_default>;
pinctrl-names = "default";
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
wakeup-source;
};
key-volume-up {
label = "Volume Up";
gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
@ -78,6 +87,13 @@ vph_pwr: vph-pwr-regulator {
};
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/msm8953/flipkart/rimob/a506_zap.mbn";
};
&hsusb_phy {
vdd-supply = <&pm8953_l3>;
@ -87,11 +103,95 @@ &hsusb_phy {
status = "okay";
};
&i2c_3 {
status = "okay";
touchscreen@5d {
compatible = "goodix,gt5688";
reg = <0x5d>;
interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&tsp_int_rst_default>;
pinctrl-names = "default";
irq-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
VDDIO-supply = <&pm8953_l6>;
AVDD28-supply = <&pm8953_l10>;
touchscreen-size-x = <1080>;
touchscreen-size-y = <1920>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
};
&ibb {
qcom,discharge-resistor-kohms = <32>;
};
&lab {
qcom,soft-start-us = <800>;
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&pm8953_s3>;
vddio-supply = <&pm8953_l6>;
status = "okay";
panel: panel@0 {
compatible = "flipkart,rimob-panel-nt35532-cs";
reg = <0>;
backlight = <&pmi8950_wled>;
reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
avdd-supply = <&lab>;
avee-supply = <&ibb>;
vci-supply = <&pm8953_l17>;
vddi-supply = <&pm8953_l6>;
pinctrl-0 = <&panel_default>;
pinctrl-names = "default";
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&panel_in>;
};
&mdss_dsi0_phy {
vcca-supply = <&pm8953_l3>;
status = "okay";
};
&pm8953_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pmi8950_wled {
qcom,current-limit-microamp = <10000>;
qcom,num-strings = <3>;
qcom,ovp-millivolt = <29500>;
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm8953-regulators";
@ -238,6 +338,27 @@ &sdhc_2 {
&tlmm {
gpio-reserved-ranges = <0 4>, <135 4>;
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio46";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
panel_default: panel-default-state {
pins = "gpio61";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
tsp_int_rst_default: tsp-int-rst-default-state {
pins = "gpio64", "gpio65";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
gpio_key_default: gpio-key-default-state {
pins = "gpio85";
function = "gpio";
@ -253,3 +374,18 @@ &usb3 {
&usb3_dwc3 {
dr_mode = "peripheral";
};
&wcnss {
vddpx-supply = <&pm8953_l5>;
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3660b";
vddxo-supply = <&pm8953_l7>;
vddrfa-supply = <&pm8953_l19>;
vddpa-supply = <&pm8953_l9>;
vdddig-supply = <&pm8953_l5>;
};

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@ -39,7 +39,7 @@ &blsp2_i2c3 {
haptics: drv2604@5a {
compatible = "ti,drv2604";
reg = <0x5a>;
enable-gpio = <&tlmm 93 0x00>;
enable-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>;
mode = <DRV260X_LRA_MODE>;
library-sel = <DRV260X_LIB_LRA>;
pinctrl-names = "default","sleep";

41
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -1632,6 +1632,30 @@ blsp2_i2c5_default: blsp2-i2c5-state {
/* Sleep state for BLSP2_I2C5 is missing.. */
blsp2_spi5_default: blsp2-spi5-default-state {
spi-pins {
pins = "gpio58", "gpio59", "gpio61";
function = "blsp_spi11";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio60";
function = "blsp_spi11";
drive-strength = <16>;
bias-disable;
output-high;
};
};
blsp2_spi5_sleep: blsp2-spi5-sleep-state {
pins = "gpio58", "gpio59", "gpio60", "gpio61";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
cdc_reset_active: cdc-reset-active-state {
pins = "gpio64";
function = "gpio";
@ -3433,6 +3457,23 @@ blsp2_i2c5: i2c@75b9000 {
status = "disabled";
};
blsp2_spi5: spi@75b9000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x75b9000 0x600>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi5_default>;
pinctrl-1 = <&blsp2_spi5_sleep>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c6: i2c@75ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75ba000 0x1000>;

2
arch/arm64/boot/dts/qcom/pm4125.dtsi
View File

@ -37,7 +37,7 @@ pm4125_resin: resin {
};
pm4125_vbus: usb-vbus-regulator@1100 {
compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg";
compatible = "qcom,pm4125-vbus-reg";
reg = <0x1100>;
status = "disabled";
};

61
arch/arm64/boot/dts/qcom/pm7550-eliza.dtsi Normal file
View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm7550-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pm7550_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
/*
* Current Linux driver currently only supports up to
* 125°C, should be updated to 145°C once available.
*/
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pm7550: pmic@1 {
compatible = "qcom,pm7550", "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm7550_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm7550_gpios: gpio@8800 {
compatible = "qcom,pm7550-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pm7550_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

20
arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi
View File

@ -75,6 +75,16 @@ pm8010_m_e1_temp_alarm: temp-alarm@2400 {
interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8010_m_e1_gpios: gpio@c000 {
compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8010_m_e1_gpios 0 0 2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8010_n_e1: pmic@d {
@ -89,5 +99,15 @@ pm8010_n_e1_temp_alarm: temp-alarm@2400 {
interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8010_n_e1_gpios: gpio@c000 {
compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8010_n_e1_gpios 0 0 2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

20
arch/arm64/boot/dts/qcom/pm8010.dtsi
View File

@ -64,6 +64,16 @@ pm8010_m_temp_alarm: temp-alarm@2400 {
interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8010_m_gpios: gpio@c000 {
compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8010_m_gpios 0 0 2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8010_n: pmic@d {
@ -78,5 +88,15 @@ pm8010_n_temp_alarm: temp-alarm@2400 {
interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8010_n_gpios: gpio@c000 {
compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8010_n_gpios 0 0 2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

63
arch/arm64/boot/dts/qcom/pm8550vs-d-eliza.dtsi Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8550vs-d-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pm8550vs_d_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pm8550vs_d: pmic@3 {
compatible = "qcom,pm8550vs", "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550vs_d_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550vs_d_gpios: gpio@8800 {
compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pm8550vs_d_gpios 0 0 6>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

63
arch/arm64/boot/dts/qcom/pm8550vs-g-eliza.dtsi Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8550vs-g-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pm8550vs_g_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pm8550vs_g: pmic@6 {
compatible = "qcom,pm8550vs", "qcom,spmi-pmic";
reg = <6 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550vs_g_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550vs_g_gpios: gpio@8800 {
compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pm8550vs_g_gpios 0 0 6>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

87
arch/arm64/boot/dts/qcom/pmk8550-eliza.dtsi Normal file
View File

@ -0,0 +1,87 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
reboot-mode {
compatible = "nvmem-reboot-mode";
nvmem-cells = <&reboot_reason>;
nvmem-cell-names = "reboot-mode";
mode-recovery = <0x01>;
mode-bootloader = <0x02>;
};
};
&spmi_bus0 {
pmk8550: pmic@0 {
compatible = "qcom,pm8550", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmk8550_pon: pon@1300 {
compatible = "qcom,pmk8350-pon";
reg = <0x1300>, <0x800>;
reg-names = "hlos", "pbs";
pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
status = "disabled";
};
pon_resin: resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
status = "disabled";
};
};
pmk8550_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
pmk8550_sdam_2: nvram@7100 {
compatible = "qcom,spmi-sdam";
reg = <0x7100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x7100 0x100>;
reboot_reason: reboot-reason@48 {
reg = <0x48 0x1>;
bits = <1 7>;
};
};
pmk8550_gpios: gpio@b800 {
compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio";
reg = <0xb800>;
gpio-controller;
gpio-ranges = <&pmk8550_gpios 0 0 6>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmk8550_pwm: pwm {
compatible = "qcom,pmk8550-pwm";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
};
};

63
arch/arm64/boot/dts/qcom/pmr735d-eliza.dtsi Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmr735d-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmr735d_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pmr735d: pmic@a {
compatible = "qcom,pmr735d", "qcom,spmi-pmic";
reg = <0xa SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735d_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmr735d_gpios: gpio@8800 {
compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmr735d_gpios 0 0 2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

4
arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
View File

@ -389,6 +389,10 @@ &gpu_zap_shader {
firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
};
&iris {
status = "okay";
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";

60
arch/arm64/boot/dts/qcom/purwa.dtsi
View File

@ -6,6 +6,8 @@
/* X1P42100 is heavily based on hamoa, with some meaningful differences */
#include "hamoa.dtsi"
#include <dt-bindings/clock/qcom,x1p42100-videocc.h>
/delete-node/ &bwmon_cluster0;
/delete-node/ &cluster_pd2;
/delete-node/ &cpu_map_cluster2;
@ -19,6 +21,7 @@
/delete-node/ &cpu_pd11;
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
/delete-node/ &iris_opp_table;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_aoss3;
/delete-node/ &thermal_cpu2_0_btm;
@ -36,6 +39,10 @@
/delete-node/ &thermal_gpuss_6;
/delete-node/ &thermal_gpuss_7;
&camcc {
compatible = "qcom,x1p42100-camcc";
};
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
};
@ -157,6 +164,55 @@ &gpucc {
compatible = "qcom,x1p42100-gpucc";
};
&iris {
compatible = "qcom,x1p42100-iris";
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>,
<&videocc VIDEO_CC_MVS0_BSE_CLK>;
clock-names = "iface",
"core",
"vcodec0_core",
"vcodec0_bse";
operating-points-v2 = <&iris_opp_table_x1p42100>;
iris_opp_table_x1p42100: opp-table {
compatible = "operating-points-v2";
opp-210000000 {
opp-hz = /bits/ 64 <210000000 105000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>,
<&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000 150000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>,
<&rpmhpd_opp_svs>;
};
opp-335000000 {
opp-hz = /bits/ 64 <335000000 167500000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs_l1>;
};
opp-424000000 {
opp-hz = /bits/ 64 <424000000 212000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_nom>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000 250000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_turbo>;
};
};
};
/* PCIe3 has half the lanes compared to X1E80100 */
&pcie3 {
num-lanes = <4>;
@ -256,3 +312,7 @@ &thermal_nsp3 {
&tsens3 {
status = "disabled";
};
&videocc {
compatible = "qcom,x1p42100-videocc";
};

64
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -40,9 +40,9 @@ chosen {
#size-cells = <2>;
ranges;
framebuffer0: framebuffer@a000000 {
framebuffer {
compatible = "simple-framebuffer";
reg = <0x0 0xe1000000 0x0 (2700 * 1224 * 4)>;
memory-region = <&cont_splash_mem>;
width = <1224>;
height = <2700>;
stride = <(1224 * 4)>;
@ -866,8 +866,33 @@ vibrator@5a {
&i2c2 {
status = "okay";
/* AW88261FCR amplifier @ 34 */
/* AW88261FCR amplifier @ 35 */
/* Top speaker / ear speaker */
aw88261_l: audio-codec@34 {
compatible = "awinic,aw88261";
reg = <0x34>;
dvdd-supply = <&vreg_l18b>;
sound-name-prefix = "Amplifier L";
firmware-name = "qcom/qcm6490/fairphone5/aw88261_acf.bin";
awinic,audio-channel = <0>;
#sound-dai-cells = <0>;
};
/* Bottom speaker */
aw88261_r: audio-codec@35 {
compatible = "awinic,aw88261";
reg = <0x35>;
dvdd-supply = <&vreg_l18b>;
sound-name-prefix = "Amplifier R";
firmware-name = "qcom/qcm6490/fairphone5/aw88261_acf.bin";
awinic,audio-channel = <1>;
#sound-dai-cells = <0>;
};
};
&i2c4 {
@ -913,9 +938,8 @@ &i2c9 {
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mbn";
status = "okay";
};
@ -1161,6 +1185,13 @@ &pon_resin {
status = "okay";
};
&q6afedai {
dai@127 {
reg = <QUINARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
};
&qup_spi13_cs {
drive-strength = <6>;
bias-disable;
@ -1238,6 +1269,11 @@ &sound {
compatible = "fairphone,fp5-sndcard";
model = "Fairphone 5";
pinctrl-0 = <&lpass_i2s1_active>;
pinctrl-1 = <&lpass_i2s1_sleep>;
pinctrl-names = "default",
"sleep";
mm1-dai-link {
link-name = "MultiMedia1";
@ -1246,6 +1282,22 @@ cpu {
};
};
i2s-dai-link {
link-name = "Quinary MI2S Playback";
codec {
sound-dai = <&aw88261_l>, <&aw88261_r>;
};
cpu {
sound-dai = <&q6afedai QUINARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
};
displayport-rx-dai-link {
link-name = "DisplayPort Playback";

16
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
View File

@ -501,8 +501,6 @@ &i2c1 {
&ipa {
firmware-name = "qcom/qcm6490/particle/tachyon/ipa_fws.mbn";
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
status = "okay";
};
@ -545,9 +543,6 @@ &mdss_dp_out {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
@ -561,9 +556,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@ -579,6 +577,10 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
&pmk8350_adc_tm {
status = "okay";

7
arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
View File

@ -39,9 +39,9 @@ chosen {
stdout-path = "serial0:115200n8";
framebuffer0: framebuffer@a000000 {
framebuffer {
compatible = "simple-framebuffer";
reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>;
memory-region = <&cont_splash_mem>;
width = <1080>;
height = <2400>;
stride = <(1080 * 4)>;
@ -553,9 +553,8 @@ &i2c13 {
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/qcm6490/SHIFT/otter/ipa_fws.mbn";
status = "okay";
};

6
arch/arm64/boot/dts/qcom/qcs615-ride.dts
View File

@ -232,8 +232,8 @@ vreg_l1a: ldo1 {
vreg_l2a: ldo2 {
regulator-name = "vreg_l2a";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3100000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
@ -599,7 +599,7 @@ &sdhc_2 {
cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l10a>;
vqmmc-supply = <&vreg_s4a>;
vqmmc-supply = <&vreg_l2a>;
status = "okay";
};

20
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
View File

@ -504,6 +504,10 @@ &i2c13 {
status = "okay";
};
&ipa {
/delete-property/ memory-region;
};
&lpass_audiocc {
compatible = "qcom,qcm6490-lpassaudiocc";
/delete-property/ power-domains;
@ -522,9 +526,6 @@ &lpass_va_macro {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@ -538,10 +539,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
@ -566,6 +569,11 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
&pm7325_gpios {
pm7325_adc_default: adc-default-state {
pins = "gpio2";

7
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@ -806,7 +806,7 @@ &mdss_dp {
};
&mdss_dp_out {
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
@ -841,8 +841,6 @@ &mdss_edp_phy {
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@ -867,6 +865,8 @@ &pcie1_phy {
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -1422,6 +1422,7 @@ &usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
mode-switch;
orientation-switch;
status = "okay";

18
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
View File

@ -653,6 +653,10 @@ redriver_usb_con_sbu: endpoint {
};
};
&ipa {
/delete-property/ memory-region;
};
&mdss {
status = "okay";
};
@ -684,9 +688,6 @@ &mdss_dsi_phy {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
<&pcie0_wake_n>;
@ -702,10 +703,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
<&pcie1_wake_n>;
@ -732,6 +735,9 @@ &pcie1_phy {
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;

20
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
View File

@ -774,6 +774,10 @@ lt9611_out: endpoint {
};
};
&ipa {
/delete-property/ memory-region;
};
&lpass_audiocc {
compatible = "qcom,qcm6490-lpassaudiocc";
/delete-property/ power-domains;
@ -812,9 +816,6 @@ &mdss_dsi_phy {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
<&pcie0_wake_n>;
@ -830,10 +831,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
<&pcie1_wake_n>;
@ -849,6 +852,11 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
&pm7325_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";

1014
arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts Normal file
View File

File diff suppressed because it is too large Load Diff

1573
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -1054,7 +1054,7 @@ usb_1_dwc3_ss: endpoint {
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
reg = <0x0 0xb220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
<94 609 31>, <125 63 1>;
#interrupt-cells = <2>;

4
arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts
View File

@ -235,8 +235,8 @@ &mdss_dsi0_phy {
};
&pm4125_vbus {
regulator-min-microamp = <500000>;
regulator-max-microamp = <500000>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "okay";
};

4
arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso
View File

@ -60,7 +60,7 @@ ov9282_ep: endpoint {
link-frequencies = /bits/ 64 <400000000>;
data-lanes = <1 2>;
remote-endpoint = <&csiphy0_ep>;
};
};
};
};
};
};

4
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
View File

@ -433,8 +433,8 @@ pm4125_ss_in: endpoint {
};
&pm4125_vbus {
regulator-min-microamp = <500000>;
regulator-max-microamp = <500000>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "okay";
};

6
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -741,6 +741,12 @@ &usb_qmpphy_out {
remote-endpoint = <&pmi632_ss_in>;
};
&venus {
firmware-name = "qcom/venus-6.0/venus.mbn";
status = "okay";
};
&wifi {
/* SoC */
vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>;

32
arch/arm64/boot/dts/qcom/sa8295p-adp.dts
View File

@ -453,15 +453,17 @@ &mdss1_dp3_phy {
};
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "okay";
};
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@ -472,15 +474,17 @@ &pcie2a_phy {
&pcie3a {
num-lanes = <2>;
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
status = "okay";
};
&pcie3a_port0 {
reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
};
&pcie3a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@ -489,15 +493,17 @@ &pcie3a_phy {
};
&pcie3b {
perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3b_default>;
status = "okay";
};
&pcie3b_port0 {
reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
};
&pcie3b_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@ -506,15 +512,17 @@ &pcie3b_phy {
};
&pcie4 {
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie4_default>;
status = "okay";
};
&pcie4_port0 {
reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;

16
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
View File

@ -366,15 +366,17 @@ &pcie2a {
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
<0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "disabled";
};
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
};
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@ -387,15 +389,17 @@ &pcie3a {
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
<0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
status = "okay";
};
&pcie3a_port0 {
reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
};
&pcie3a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;

17
arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
View File

@ -1,17 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include "lemans-auto.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
#include "lemans-ride-ethernet-aqr115c.dtsi"
/ {
model = "Qualcomm SA8775P Ride Rev3";
compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p";
};

17
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@ -1,17 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include "lemans-auto.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
#include "lemans-ride-ethernet-88ea1512.dtsi"
/ {
model = "Qualcomm SA8775P Ride";
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
};

2
arch/arm64/boot/dts/qcom/sar2130p.dtsi
View File

@ -2417,7 +2417,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sar2130p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 94>,
<94 609 31>,
<125 63 1>,

5
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@ -99,6 +99,11 @@ chosen {
stdout-path = "serial0:115200n8";
};
firmware {
#address-cells = <2>;
#size-cells = <2>;
};
/* FIXED REGULATORS - parents above children */
/* This is the top level supply and variable voltage */

2
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -3514,7 +3514,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7180-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;

2
arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
View File

@ -22,7 +22,9 @@ mdata_mem: mpss-metadata {
};
&ipa {
/delete-property/ memory-region;
qcom,gsi-loader = "modem";
status = "okay";
};

5
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View File

@ -25,6 +25,11 @@ chosen {
stdout-path = "serial0:115200n8";
};
firmware {
#address-cells = <2>;
#size-cells = <2>;
};
/*
* FIXED REGULATORS
*

5
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -418,7 +418,6 @@ &lpass_va_macro {
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>;
@ -433,6 +432,10 @@ &pcie1_phy {
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
&pmk8350_vadc {
channel@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;

57
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
View File

@ -26,6 +26,7 @@ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pmc8180c_lpg 4 1000000>;
enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>;
power-supply = <&vled_bl_pw>;
pinctrl-0 = <&bl_pwm_default>;
pinctrl-names = "default";
@ -157,14 +158,39 @@ cdsp_mem: cdsp-region@98900000 {
};
};
vph_pwr: vph-pwr-regulator {
vled_bl_pw: regulator-vled-bl-pw {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-name = "VLED_BL_PW";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmc8180_2_gpios 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&bl_pwr_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_s4a_1p8: pm8150-s4-regulator {
vreg_lcm_3v3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_LCM_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&lcm_3v3_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_s4a_1p8: regulator-pm8150-s4 {
compatible = "regulator-fixed";
regulator-name = "vreg_s4a_1p8";
@ -177,6 +203,13 @@ vreg_s4a_1p8: pm8150-s4-regulator {
vin-supply = <&vph_pwr>;
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
usbprim-sbu-mux {
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
@ -438,6 +471,7 @@ &mdss_edp {
aux-bus {
panel {
compatible = "edp-panel";
power-supply = <&vreg_lcm_3v3>;
no-hpd;
backlight = <&backlight>;
@ -472,6 +506,13 @@ &pcie3_phy {
status = "okay";
};
&pmc8180_2_gpios {
bl_pwr_en: bl-pwr-en-state {
pins = "gpio1";
function = "normal";
};
};
&pmc8180_pwrkey {
status = "okay";
};
@ -765,6 +806,12 @@ ts_int_default: ts-int-default-state {
drive-strength = <2>;
};
lcm_3v3_en: lcm-3v3-en-state {
pins = "gpio130";
function = "gpio";
bias-disable;
};
usbprim_sbu_default: usbprim-sbu-state {
oe-n-pins {
pins = "gpio152";

56
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
View File

@ -29,9 +29,10 @@ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pmc8180c_lpg 4 1000000>;
enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>;
power-supply = <&vled_bl_pw>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwm_default>;
pinctrl-names = "default";
};
chosen {
@ -167,7 +168,39 @@ reserved-region@9a500000 {
};
};
vreg_nvme_0p9: nvme-0p9-regulator {
vled_bl_pw: regulator-vled-bl-pw {
compatible = "regulator-fixed";
regulator-name = "VLED_BL_PW";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmc8180_2_gpios 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&bl_pwr_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_lcm_3v3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_LCM_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&lcm_3v3_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_nvme_0p9: regulator-nvme-0p9 {
compatible = "regulator-fixed";
regulator-name = "vreg_nvme_0p9";
@ -177,7 +210,7 @@ vreg_nvme_0p9: nvme-0p9-regulator {
regulator-always-on;
};
vreg_nvme_3p3: nvme-3p3-regulator {
vreg_nvme_3p3: regulator-nvme-3p3 {
compatible = "regulator-fixed";
regulator-name = "vreg_nvme_3p3";
@ -190,7 +223,7 @@ vreg_nvme_3p3: nvme-3p3-regulator {
regulator-always-on;
};
vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator {
vdd_kb_tp_3v3: regulator-vdd-kb-tp-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_kb_tp_3v3";
regulator-min-microvolt = <3300000>;
@ -205,7 +238,7 @@ vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator {
pinctrl-0 = <&kb_tp_3v3_en_active_state>;
};
vph_pwr: vph-pwr-regulator {
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
@ -540,6 +573,7 @@ &mdss_edp {
aux-bus {
panel {
compatible = "edp-panel";
power-supply = <&vreg_lcm_3v3>;
backlight = <&backlight>;
@ -769,6 +803,12 @@ &wifi {
};
/* PINCTRL */
&pmc8180_2_gpios {
bl_pwr_en: bl-pwr-en-state {
pins = "gpio1";
function = "normal";
};
};
&pmc8180c_gpios {
bl_pwm_default: bl-pwm-default-state {
@ -950,4 +990,10 @@ rx-pins {
bias-pull-up;
};
};
lcm_3v3_en: lcm-3v3-en-state {
pins = "gpio130";
function = "gpio";
bias-disable;
};
};

2
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -3554,7 +3554,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8180x-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;

22
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -628,9 +628,6 @@ keyboard@68 {
};
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@ -646,10 +643,12 @@ &pcie2a_phy {
status = "okay";
};
&pcie3a {
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@ -665,12 +664,14 @@ &pcie3a_phy {
status = "okay";
};
&pcie3a_port0 {
reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie4 {
max-link-speed = <2>;
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@ -687,6 +688,9 @@ &pcie4_phy {
};
&pcie4_port0 {
reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;

14
arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
View File

@ -739,9 +739,6 @@ &mdss0_dp1_out {
};
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@ -757,12 +754,14 @@ &pcie2a_phy {
status = "okay";
};
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie4 {
max-link-speed = <2>;
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@ -772,6 +771,9 @@ &pcie4 {
};
&pcie4_port0 {
reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;

38
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -674,8 +674,9 @@ camera@10 {
reg = <0x10>;
reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&cam_rgb_default>, <&cam_mclk3_default>;
pinctrl-names = "default";
pinctrl-0 = <&cam_rgb_default>;
leds = <&privacy_led>;
led-names = "privacy";
@ -932,10 +933,13 @@ keyboard@68 {
};
};
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
&iris {
firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcvss8280.mbn";
status = "okay";
};
&pcie2a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@ -951,10 +955,12 @@ &pcie2a_phy {
status = "okay";
};
&pcie3a {
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@ -970,12 +976,14 @@ &pcie3a_phy {
status = "okay";
};
&pcie3a_port0 {
reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie4 {
max-link-speed = <2>;
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@ -985,6 +993,9 @@ &pcie4 {
};
&pcie4_port0 {
reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -1552,13 +1563,6 @@ cam_indicator_en: cam-indicator-en-state {
};
cam_rgb_default: cam-rgb-default-state {
mclk-pins {
pins = "gpio17";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
sc-rgb-xshut-n-pins {
pins = "gpio15";
function = "gpio";

301
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
View File

@ -6,6 +6,8 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc8280xp.dtsi"
@ -46,11 +48,56 @@ wcd938x: audio-codec {
#sound-dai-cells = <1>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pmc8280c_lpg 3 1000000>;
enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
pinctrl-names = "default";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&hall_int_n_default>, <&vol_down_n>, <&vol_up_n>;
pinctrl-names = "default";
key-vol-down {
label = "Volume Down";
gpios = <&pmc8280_1_gpios 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
key-vol-up {
label = "Volume Up";
gpios = <&pmc8280_1_gpios 9 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
switch-lid {
label = "lid";
gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
wakeup-event-action = <EV_ACT_DEASSERTED>;
};
};
pmic-glink {
compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>,
<&tlmm 49 GPIO_ACTIVE_HIGH>;
/* Left-side top port */
connector@0 {
@ -127,6 +174,22 @@ pmic_glink_con1_sbu: endpoint {
};
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 36 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
@ -243,7 +306,7 @@ map1 {
usb0-sbu-mux {
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
enable-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb0_sbu_default>;
@ -277,6 +340,70 @@ usb1_sbu_mux: endpoint {
};
};
};
wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";
pinctrl-0 = <&bt_default>, <&wlan_en>;
pinctrl-names = "default";
wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
vddio-supply = <&vreg_s10b>;
vddaon-supply = <&vreg_s12b>;
vddpmu-supply = <&vreg_s12b>;
vddpmumx-supply = <&vreg_s12b>;
vddpmucx-supply = <&vreg_s12b>;
vddrfa0p95-supply = <&vreg_s12b>;
vddrfa1p3-supply = <&vreg_s11b>;
vddrfa1p9-supply = <&vreg_s1c>;
vddpcie1p3-supply = <&vreg_s11b>;
vddpcie1p9-supply = <&vreg_s1c>;
regulators {
vreg_pmu_rfa_cmn_0p8: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn_0p8";
};
vreg_pmu_aon_0p8: ldo1 {
regulator-name = "vreg_pmu_aon_0p8";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p8: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p8";
};
vreg_pmu_btcmx_0p8: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p8";
};
vreg_pmu_pcie_1p8: ldo5 {
regulator-name = "vreg_pmu_pcie_1p8";
};
vreg_pmu_pcie_0p9: ldo6 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_rfa_0p8: ldo7 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo8 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo9 {
regulator-name = "vreg_pmu_rfa_1p7";
};
};
};
};
&apps_rsc {
@ -303,7 +430,6 @@ vreg_s11b: smps11 {
regulator-min-microvolt = <1272000>;
regulator-max-microvolt = <1272000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_s12b: smps12 {
@ -311,7 +437,6 @@ vreg_s12b: smps12 {
regulator-min-microvolt = <984000>;
regulator-max-microvolt = <984000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l3b: ldo3 {
@ -335,7 +460,6 @@ vreg_l6b: ldo6 {
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-boot-on;
regulator-always-on; // FIXME: VDD_A_EDP_0_0P9
};
};
@ -439,10 +563,6 @@ &dispcc0 {
status = "okay";
};
&dispcc1 {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
@ -472,7 +592,7 @@ &mdss0_dp0 {
};
&mdss0_dp0_out {
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&usb_0_qmpphy_dp_in>;
};
@ -481,14 +601,47 @@ &mdss0_dp1 {
};
&mdss0_dp1_out {
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
&mdss0_dp3 {
compatible = "qcom,sc8280xp-edp";
/delete-property/ #sound-dai-cells;
data-lanes = <0 1 2 3>;
status = "okay";
aux-bus {
panel {
compatible = "edp-panel";
backlight = <&backlight>;
power-supply = <&vreg_edp_3p3>;
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss0_dp3_out>;
};
};
};
};
};
&mdss0_dp3_out {
remote-endpoint = <&edp_panel_in>;
};
&mdss0_dp3_phy {
compatible = "qcom,sc8280xp-edp-phy";
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;
status = "okay";
};
&pcie2a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@ -504,10 +657,12 @@ &pcie2a_phy {
status = "okay";
};
&pcie3a {
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie3a_default>;
@ -523,12 +678,14 @@ &pcie3a_phy {
status = "okay";
};
&pcie3a_port0 {
reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
};
&pcie4 {
max-link-speed = <2>;
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@ -538,10 +695,23 @@ &pcie4 {
};
&pcie4_port0 {
reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
qcom,calibration-variant = "MS_SP9_5G";
};
};
@ -553,6 +723,10 @@ &pcie4_phy {
status = "okay";
};
&pmc8280c_lpg {
status = "okay";
};
&pmk8280_pon_pwrkey {
status = "okay";
};
@ -562,20 +736,11 @@ &pmk8280_pon_resin {
};
&pmk8280_rtc {
nvmem-cells = <&rtc_offset>;
nvmem-cell-names = "offset";
qcom,uefi-rtc-info;
status = "okay";
};
&pmk8280_sdam_6 {
status = "okay";
rtc_offset: rtc-offset@bc {
reg = <0xbc 0x4>;
};
};
&qup0 {
status = "okay";
};
@ -615,9 +780,6 @@ &sound {
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS1",
"VA DMIC2", "VA MIC BIAS3",
"TX SWR_ADC1", "ADC2_OUTPUT";
wcd-playback-dai-link {
@ -722,20 +884,16 @@ &uart2 {
bluetooth {
compatible = "qcom,wcn6855-bt";
vddio-supply = <&vreg_s10b>;
vddbtcxmx-supply = <&vreg_s12b>;
vddrfacmn-supply = <&vreg_s12b>;
vddrfa0p8-supply = <&vreg_s12b>;
vddrfa1p2-supply = <&vreg_s11b>;
vddrfa1p7-supply = <&vreg_s1c>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
vddaon-supply = <&vreg_pmu_aon_0p8>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
max-speed = <3200000>;
enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&bt_default>;
pinctrl-names = "default";
};
};
@ -778,6 +936,7 @@ &usb_0_qmpphy {
vdda-phy-supply = <&vreg_l9d>;
vdda-pll-supply = <&vreg_l4d>;
mode-switch;
orientation-switch;
status = "okay";
@ -815,6 +974,7 @@ &usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4b>;
vdda-pll-supply = <&vreg_l3b>;
mode-switch;
orientation-switch;
status = "okay";
@ -853,6 +1013,29 @@ &lpass_tlmm {
status = "okay";
};
&pmc8280_1_gpios {
edp_bl_en: edp-bl-en-state {
pins = "gpio8";
function = "normal";
};
vol_down_n: vol-down-n-state {
pins = "gpio6";
function = "normal";
power-source = <1>;
input-enable;
bias-pull-up;
};
vol_up_n: vol-up-n-state {
pins = "gpio9";
function = "normal";
power-source = <1>;
input-enable;
bias-pull-up;
};
};
&pmc8280_2_gpios {
wwan_sw_en: wwan-sw-en-state {
pins = "gpio1";
@ -860,6 +1043,13 @@ wwan_sw_en: wwan-sw-en-state {
};
};
&pmc8280c_gpios {
edp_bl_pwm: edp-bl-pwm-state {
pins = "gpio8";
function = "func1";
};
};
&pmr735a_gpios {
hastings_reg_en: hastings-reg-en-state {
pins = "gpio1";
@ -883,6 +1073,20 @@ hstp-sw-ctrl-pins {
};
};
edp_reg_en: edp-reg-en-state {
pins = "gpio36";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
hall_int_n_default: hall-int-n-state {
pins = "gpio180";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
nvme_reg_en: nvme-reg-en-state {
pins = "gpio135";
function = "gpio";
@ -996,7 +1200,7 @@ tx-pins {
usb0_sbu_default: usb0-sbu-state {
oe-n-pins {
pins = "gpio101";
pins = "gpio100";
function = "gpio";
bias-disable;
drive-strength = <16>;
@ -1035,4 +1239,11 @@ reset-pins {
bias-disable;
};
};
wlan_en: wlan-en-state {
pins = "gpio134";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};

25
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
View File

@ -624,9 +624,6 @@ &mdss0_dp2_phy {
};
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@ -642,12 +639,14 @@ &pcie2a_phy {
status = "okay";
};
&pcie2a_port0 {
reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie4 {
max-link-speed = <2>;
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@ -657,6 +656,9 @@ &pcie4 {
};
&pcie4_port0 {
reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@ -763,20 +765,11 @@ &pmk8280_pon_resin {
};
&pmk8280_rtc {
nvmem-cells = <&rtc_offset>;
nvmem-cell-names = "offset";
qcom,uefi-rtc-info;
status = "okay";
};
&pmk8280_sdam_6 {
status = "okay";
rtc_offset: rtc-offset@bc {
reg = <0xbc 0x4>;
};
};
&pmk8280_vadc {
channel@144 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;

343
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -11,13 +11,16 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sm8350-videocc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
@ -314,78 +317,18 @@ scm: scm {
};
};
aggre1_noc: interconnect-aggre1-noc {
compatible = "qcom,sc8280xp-aggre1-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect-aggre2-noc {
compatible = "qcom,sc8280xp-aggre2-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
clk_virt: interconnect-clk-virt {
compatible = "qcom,sc8280xp-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect-config-noc {
compatible = "qcom,sc8280xp-config-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect-dc-noc {
compatible = "qcom,sc8280xp-dc-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect-gem-noc {
compatible = "qcom,sc8280xp-gem-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_noc: interconnect-lpass-ag-noc {
compatible = "qcom,sc8280xp-lpass-ag-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-mc-virt {
compatible = "qcom,sc8280xp-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect-mmss-noc {
compatible = "qcom,sc8280xp-mmss-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
nspa_noc: interconnect-nspa-noc {
compatible = "qcom,sc8280xp-nspa-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
nspb_noc: interconnect-nspb-noc {
compatible = "qcom,sc8280xp-nspb-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect-system-noc {
compatible = "qcom,sc8280xp-system-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@ -692,8 +635,8 @@ reserved-region@85b00000 {
no-map;
};
pil_gpu_mem: gpu-mem@8bf00000 {
reg = <0 0x8bf00000 0 0x2000>;
pil_video_mem: video-region@86700000 {
reg = <0 0x86700000 0 0x500000>;
no-map;
};
@ -712,6 +655,11 @@ pil_nsp0_mem: cdsp0-region@8a100000 {
no-map;
};
pil_gpu_mem: gpu-mem@8bf00000 {
reg = <0 0x8bf00000 0 0x2000>;
no-map;
};
pil_nsp1_mem: cdsp1-region@8c600000 {
reg = <0 0x8c600000 0 0x1e00000>;
no-map;
@ -2152,6 +2100,63 @@ rng: rng@10d3000 {
clock-names = "core";
};
config_noc: interconnect@1500000 {
compatible = "qcom,sc8280xp-config-noc";
reg = <0 0x01500000 0 0x2c000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,sc8280xp-system-noc";
reg = <0 0x01680000 0 0x1a400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16c0000 {
compatible = "qcom,sc8280xp-aggre1-noc";
reg = <0 0x016c0000 0 0x3af80>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_1_AXI_CLK>,
<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sc8280xp-aggre2-noc";
reg = <0 0x01700000 0 0x3af80>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sc8280xp-mmss-noc";
reg = <0 0x01740000 0 0x1fa80>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie4: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sc8280xp";
@ -2220,9 +2225,6 @@ pcie4: pcie@1c00000 {
power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie4_phy>;
phy-names = "pciephy";
status = "disabled";
pcie4_port0: pcie@0 {
@ -2230,6 +2232,8 @@ pcie4_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie4_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -2331,9 +2335,6 @@ pcie3b: pcie@1c08000 {
power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3b_phy>;
phy-names = "pciephy";
status = "disabled";
pcie3b_port0: pcie@0 {
@ -2341,6 +2342,8 @@ pcie3b_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie3b_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -2442,9 +2445,6 @@ pcie3a: pcie@1c10000 {
power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3a_phy>;
phy-names = "pciephy";
status = "disabled";
pcie3a_port0: pcie@0 {
@ -2452,6 +2452,8 @@ pcie3a_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie3a_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -2556,9 +2558,6 @@ pcie2b: pcie@1c18000 {
power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2b_phy>;
phy-names = "pciephy";
status = "disabled";
pcie2b_port0: pcie@0 {
@ -2566,6 +2565,8 @@ pcie2b_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie2b_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -2667,9 +2668,6 @@ pcie2a: pcie@1c20000 {
power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2a_phy>;
phy-names = "pciephy";
status = "disabled";
pcie2a_port0: pcie@0 {
@ -2677,6 +2675,8 @@ pcie2a_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie2a_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -3379,6 +3379,14 @@ lpasscc: clock-controller@33e0000 {
#reset-cells = <1>;
};
lpass_noc: interconnect@3c40000 {
compatible = "qcom,sc8280xp-lpass-ag-noc";
reg = <0 0x03c40000 0 0xf080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gpu: gpu@3d00000 {
compatible = "qcom,adreno-690.0", "qcom,adreno";
@ -3954,6 +3962,22 @@ opp-6 {
};
};
dc_noc: interconnect@90e0000 {
compatible = "qcom,sc8280xp-dc-noc";
reg = <0 0x090e0000 0 0x5080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
compatible = "qcom,sc8280xp-gem-noc";
reg = <0 0x09100000 0 0xb8400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system-cache-controller@9200000 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
@ -4209,6 +4233,97 @@ usb_1_dwc3_ss: endpoint {
};
};
iris: video-codec@aa00000 {
compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
reg = <0x0 0x0aa00000 0x0 0x100000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>;
clock-names = "iface",
"core",
"vcodec0_core";
power-domains = <&videocc MVS0C_GDSC>,
<&videocc MVS0_GDSC>,
<&rpmhpd SC8280XP_MX>,
<&rpmhpd SC8280XP_MMCX>;
power-domain-names = "venus",
"vcodec0",
"mx",
"mmcx";
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
reset-names = "bus", "core";
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "cpu-cfg",
"video-mem";
operating-points-v2 = <&iris_opp_table>;
iommus = <&apps_smmu 0x2a00 0x400>;
memory-region = <&pil_video_mem>;
status = "disabled";
iris_opp_table: opp-table {
compatible = "operating-points-v2";
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_low_svs>;
};
opp-338000000 {
opp-hz = /bits/ 64 <338000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs>;
};
opp-366000000 {
opp-hz = /bits/ 64 <366000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_svs_l1>;
};
opp-444000000 {
opp-hz = /bits/ 64 <444000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_nom>;
};
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo_l1>;
};
};
};
videocc: clock-controller@abf0000 {
compatible = "qcom,sc8280xp-videocc";
reg = <0 0x0abf0000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
cci0: cci@ac4a000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4a000 0 0x1000>;
@ -5326,7 +5441,7 @@ dispcc0: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>;
qcom,pdc-ranges = <0 480 40>,
<40 140 14>,
<54 263 1>,
@ -5484,6 +5599,62 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 230>;
wakeup-parent = <&pdc>;
cam_mclk0_default: cam-mclk0-default-state {
pins = "gpio119";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk1_default: cam-mclk1-default-state {
pins = "gpio120";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk2_default: cam-mclk2-default-state {
pins = "gpio16";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk3_default: cam-mclk3-default-state {
pins = "gpio17";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk4_default: cam-mclk4-default-state {
pins = "gpio6";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk5_default: cam-mclk5-default-state {
pins = "gpio7";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk6_default: cam-mclk6-default-state {
pins = "gpio33";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cam_mclk7_default: cam-mclk7-default-state {
pins = "gpio34";
function = "cam_mclk";
drive-strength = <6>;
bias-disable;
};
cci0_default: cci0-default-state {
cci0_i2c0_default: cci0-i2c0-default-pins {
/* cci_i2c_sda0, cci_i2c_scl0 */
@ -6004,6 +6175,14 @@ cpufreq_hw: cpufreq@18591000 {
#clock-cells = <1>;
};
nspa_noc: interconnect@1b0c0000 {
compatible = "qcom,sc8280xp-nspa-noc";
reg = <0 0x1b0c0000 0 0x10000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
remoteproc_nsp0: remoteproc@1b300000 {
compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x10000>;
@ -6139,6 +6318,14 @@ compute-cb@14 {
};
};
nspb_noc: interconnect@210c0000 {
compatible = "qcom,sc8280xp-nspb-noc";
reg = <0 0x210c0000 0 0x10000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
remoteproc_nsp1: remoteproc@21300000 {
compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x10000>;

5
arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi
View File

@ -522,6 +522,11 @@ rmi4_f12: rmi4-f12@12 {
};
};
&lpi_tlmm {
/* sensor gpios are protected */
gpio-reserved-ranges = <0 8>, <12 6>;
};
&mdss {
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sdm670.dtsi
View File

@ -1646,7 +1646,7 @@ usb_1_dwc3: usb@a600000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdm670-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
<54 534 24>, <79 559 15>, <94 609 15>,
<115 630 7>;

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