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arm64: dts: NXP device tree updates for v7.3

Browse Source 
New boards and SOM support:
 - Variscite DART-MX8M-MINI, DART-MX8M-PLUS, VAR-SOM-MX8 QuadMax
   (with Sonata and Symphony carrier boards)
 - TQMa8MPxS (i.MX8MP) with LVDS overlays, TQMa9596LA on MBa95xxCA; TQMa91xx
   on MBa93xxCA
 - imx8mm-verdin: Toradex DSI displays (7"/10.1"), HDMI adapter, NAU8822 BTL
   audio, Cortex-M4F remoteproc and UART overlay
 
 i.MX8:
 - PCIe: add power supply properties to Root Port nodes.
 - imx8mp-evk add typec and usb3_phy1 tuning; imx8mq-evk add typec;
 - imx8mp-evk add flexcan2 overlay and CAN2/MICFIL board mux; imx8mp-frdm
   fix HDMI DDC pinctrl
 - imx8mp-var-som-symphony: add second Ethernet, CAN, PWM1, ECSPI2,
   capacitive touchscreen, HDMI, PCIe, USB, TPM, external RTC, input
   keys, header UARTs
 - imx8mq-evk: add DCSS node, uart3/bluetooth node
 - imx8qm: add SCU power key, lsio mu8/mu8b, spdif1, lpuart4 nodes;
   fix LPCG clock indices for ASRC0; add Variscite Symphony board support
 - imx8ulp: add I3C2, eDMA channel properties, LPUART6 (BT) and LPUART7,
   gpio-keys power button; correct SRAM node address/size; update rpmsg
   resource table address; rename 9x9-evk model string
 - imx8mp: enable MU2 for DSP communication (imx8mp-ab2)
 
 i.MX9:
 - PCIe: add Root Port nodes with correct outbound address space for
   imx94/imx943/imx95; add dma/intr/aer/pme interrupts for imx95 PCIe;
   remove 'supports-clkreq' from imx943-evk PCIe1
 - imx95: switch USB3 controller to flattened model; add CM7/CM33S nodes
   for imx943/imx952/imx95-19x19-evk; add imx94 DMA channels (xspi);
   enable NETC block control and in-band SFP status (imx95-var-dart);
   add wm8904 DMICDAT1; add lpuart5 alias (imx95-toradex-smarc)
 - imx93: add LVDS Display Bridge support with DY1212W-4856 panel overlay
   for imx93-11x11-evk; add LVDS overlays for imx93-tqma9352 boards;
   update TMU compatible string; fix memory node for imx93-kontron
 - imx91: add WM8524 and PDM microphone sound cards, CAN overlay, audio
   board muxes (imx91-9x9-qsb); move ELE reserved memory into 512MB
   range; USB phy adjustments (imx91-tqma9131)
 
 Layerscape / S32G:
 - ls1028a/ls1046a/ls1088a/ls208xa/lx2160a/lx2162a: describe Lynx 10G
   SerDes blocks; refactor lx2160a PCIe and SerDes into separate dtsi
   files; transition to device-specific SerDes compatible strings
 - s32g: add GPR syscon region; describe GPIO and EIRQ in SIUL2 pinctrl
 
 Cleanup and warning fixes:
 - correct imx8/s32g3 indentation
 - imx8mp: add missing #sound-dai-cells to xcvr
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Merge tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt

arm64: dts: NXP device tree updates for v7.3

New boards and SOM support:
- Variscite DART-MX8M-MINI, DART-MX8M-PLUS, VAR-SOM-MX8 QuadMax
  (with Sonata and Symphony carrier boards)
- TQMa8MPxS (i.MX8MP) with LVDS overlays, TQMa9596LA on MBa95xxCA; TQMa91xx
  on MBa93xxCA
- imx8mm-verdin: Toradex DSI displays (7"/10.1"), HDMI adapter, NAU8822 BTL
  audio, Cortex-M4F remoteproc and UART overlay

i.MX8:
- PCIe: add power supply properties to Root Port nodes.
- imx8mp-evk add typec and usb3_phy1 tuning; imx8mq-evk add typec;
- imx8mp-evk add flexcan2 overlay and CAN2/MICFIL board mux; imx8mp-frdm
  fix HDMI DDC pinctrl
- imx8mp-var-som-symphony: add second Ethernet, CAN, PWM1, ECSPI2,
  capacitive touchscreen, HDMI, PCIe, USB, TPM, external RTC, input
  keys, header UARTs
- imx8mq-evk: add DCSS node, uart3/bluetooth node
- imx8qm: add SCU power key, lsio mu8/mu8b, spdif1, lpuart4 nodes;
  fix LPCG clock indices for ASRC0; add Variscite Symphony board support
- imx8ulp: add I3C2, eDMA channel properties, LPUART6 (BT) and LPUART7,
  gpio-keys power button; correct SRAM node address/size; update rpmsg
  resource table address; rename 9x9-evk model string
- imx8mp: enable MU2 for DSP communication (imx8mp-ab2)

i.MX9:
- PCIe: add Root Port nodes with correct outbound address space for
  imx94/imx943/imx95; add dma/intr/aer/pme interrupts for imx95 PCIe;
  remove 'supports-clkreq' from imx943-evk PCIe1
- imx95: switch USB3 controller to flattened model; add CM7/CM33S nodes
  for imx943/imx952/imx95-19x19-evk; add imx94 DMA channels (xspi);
  enable NETC block control and in-band SFP status (imx95-var-dart);
  add wm8904 DMICDAT1; add lpuart5 alias (imx95-toradex-smarc)
- imx93: add LVDS Display Bridge support with DY1212W-4856 panel overlay
  for imx93-11x11-evk; add LVDS overlays for imx93-tqma9352 boards;
  update TMU compatible string; fix memory node for imx93-kontron
- imx91: add WM8524 and PDM microphone sound cards, CAN overlay, audio
  board muxes (imx91-9x9-qsb); move ELE reserved memory into 512MB
  range; USB phy adjustments (imx91-tqma9131)

Layerscape / S32G:
- ls1028a/ls1046a/ls1088a/ls208xa/lx2160a/lx2162a: describe Lynx 10G
  SerDes blocks; refactor lx2160a PCIe and SerDes into separate dtsi
  files; transition to device-specific SerDes compatible strings
- s32g: add GPR syscon region; describe GPIO and EIRQ in SIUL2 pinctrl

Cleanup and warning fixes:
- correct imx8/s32g3 indentation
- imx8mp: add missing #sound-dai-cells to xcvr

* tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (131 commits)
  arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe
  arm64: dts: imx94-xspi: add the DMA channels
  arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F UART_4 overlay
  arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F remoteproc
  arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 7" DSI
  arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 10.1" DSI
  arm64: dts: freescale: imx8mm-verdin: Add Toradex DSI to LVDS adapter with 10.1" display
  arm64: dts: freescale: imx8mm-verdin: Add DSI to HDMI adapter overlay
  arm64: dts: freescale: imx8mm-verdin: Add NAU8822 Bridge Tied Load
  arm64: dts: imx95-var-dart-sonata: enable in-band status for SFP
  arm64: dts: imx8ulp-evk: Update rpmsg resource table address
  arm64: dts: imx943-evk: Add CM7 and CM33S nodes
  arm64: dts: imx952-evk: Add CM7 node and related memory nodes
  arm64: dts: imx95-19x19-evk: Add CM7 node and related memory nodes
  arm64: dts: imx8qm-var-som-symphony: enable expansion header UART
  arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size
  arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET
  arm64: dts: imx8ulp-evk: Enable LPUART7
  arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth
  arm64: dts: imx8ulp-evk: Add gpio-keys node for power button
  ...

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Alexandre Belloni 2026-08-08 18:43:27 +02:00
commit b8b3f6e974
103 changed files with 11309 additions and 843 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -1064,6 +1064,12 @@ properties:
- const: solidrun,imx8mm-sr-som
- const: fsl,imx8mm
- description: Variscite DART-MX8MM based boards
items:
- const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board
- const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM
- const: fsl,imx8mm
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
@ -1310,6 +1316,24 @@ properties:
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
- const: fsl,imx8mp
- description:
TQMa8MPxS is a series of SOM featuring NXP i.MX8MP system-on-chip
variants. It has the SMARC-2.0 form factor and is designed to be
placed on different carrier boards. All CPU variants use the same
device tree hence only one compatible is needed. MB-SMARC-2 is a
carrier reference design.
items:
- enum:
- tq,imx8mp-tqma8mpqs-mb-smarc-2 # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM on MB-SMARC-2
- const: tq,imx8mp-tqma8mpqs # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM
- const: fsl,imx8mp
- description: Variscite DART-MX8M Plus based boards
items:
- const: variscite,var-dart-mx8mp-sonata # Variscite DART-MX8MP on Sonata Development Board
- const: variscite,var-dart-mx8mp # Variscite DART-MX8MP SOM
- const: fsl,imx8mp
- description: Variscite VAR-SOM-MX8M Plus based boards
items:
- const: variscite,var-som-mx8mp-symphony
@ -1369,6 +1393,12 @@ properties:
- fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board
- const: fsl,imx8qm
- description: i.MX8QM Variscite VAR-SOM-MX8 based Boards
items:
- const: variscite,var-som-imx8qm-symphony
- const: variscite,var-som-imx8qm
- const: fsl,imx8qm
- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
items:
- enum:
@ -1589,11 +1619,13 @@ properties:
in the assembled SOC.
MBa91xxCA mainboard can be used as starterkit for the SOM
soldered on an adapter board or for the connector variant
MBa91xxLA mainboard is a single board computer using the solderable
SOM variant
to demonstrate parallel display and majority of interfaces while
MBa93xxCA starterkit mainboard is focused on communication
interfaces without display support.
items:
- enum:
- tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA
- tq,imx91-tqma9131-mba93xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa93xxCA
- const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM
- const: fsl,imx91

4
Documentation/devicetree/bindings/input/fsl,scu-key.yaml
View File

@ -18,7 +18,9 @@ allOf:
properties:
compatible:
items:
- const: fsl,imx8qxp-sc-key
- enum:
- fsl,imx8qm-sc-key
- fsl,imx8qxp-sc-key
- const: fsl,imx-sc-key
linux,keycodes:

39
Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
View File

@ -26,6 +26,12 @@ properties:
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
'#power-domain-cells':
const: 1
@ -92,6 +98,11 @@ properties:
- compatible
- ports
bridge@20:
type: object
$ref: /schemas/display/bridge/fsl,ldb.yaml#
unevaluatedProperties: false
allOf:
- if:
properties:
@ -112,6 +123,7 @@ allOf:
- const: lcdif
- const: isi
- const: csi
bridge@20: false
- if:
properties:
compatible:
@ -163,6 +175,8 @@ examples:
<&clk IMX93_CLK_MIPI_DSI_GATE>;
clock-names = "apb", "axi", "nic", "disp", "cam",
"pxp", "lcdif", "isi", "csi", "dsi";
#address-cells = <1>;
#size-cells = <1>;
#power-domain-cells = <1>;
dpi-bridge {
@ -190,4 +204,29 @@ examples:
};
};
};
bridge@20 {
compatible = "fsl,imx93-ldb";
reg = <0x20 0x4>, <0x24 0x4>;
reg-names = "ldb", "lvds";
clocks = <&clk IMX93_CLK_LVDS_GATE>;
clock-names = "ldb";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&lcdif_to_ldb>;
};
};
port@1 {
reg = <1>;
};
};
};
};

65
arch/arm64/boot/dts/freescale/Makefile
View File

@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
@ -176,19 +177,54 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-uart4-mcu.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-uart4-mcu.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia-dsi-to-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb
imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo
imx8mm-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb \
imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo
imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo
imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo
imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo
imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := imx8mm-verdin-wifi-dahlia.dtb \
imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo
imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo
imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \
imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo
imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo
imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := imx8mm-verdin-wifi-dev.dtb \
imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo
imx8mm-verdin-wifi-dev-uart4-mcu-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-uart4-mcu.dtbo
imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo
imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo
imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtb
@ -206,6 +242,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb
DTC_FLAGS_imx8mn-solidsense-n8-compact += -@
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony-legacy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \
@ -361,6 +398,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb \
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
imx8mp-evk-flexcan2-dtbs += imx8mp-evk.dtb imx8mp-evk-flexcan2.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-flexcan2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb
DTC_FLAGS_imx8mp-hummingboard-iiot := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb
@ -439,6 +480,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt101tm023.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2.dtb
imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10-dtbs += imx8mp-tx8p-ml81-moduline-display-106.dtb \
imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtbo
@ -448,6 +490,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb
@ -497,6 +540,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb
imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtbo
imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtbo
imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb
@ -528,6 +578,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-tqma8qm-mba8x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-var-som-symphony.dtb
imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo
dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb
@ -564,10 +615,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
imx91-9x9-qsb-can1-dtbs += imx91-9x9-qsb.dtb imx91-9x9-qsb-can1.dtbo
imx91-phyboard-segin-peb-av-18-dtbs += imx91-phyboard-segin.dtb imx91-phyboard-segin-peb-av-18.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-can1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba93xxca.dtb
imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo
imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo
@ -588,6 +642,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-tianma-tm050rdh03.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
imx93-11x11-evk-dy1212w-4856-dtbs += imx93-11x11-evk.dtb imx93-11x11-evk-dy1212w-4856.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk-dy1212w-4856.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb
imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo
@ -625,9 +683,15 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb im
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb
imx93-tqma9352-mba93xxca-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxca.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo
imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo
imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo
imx93-tqma9352-mba93xxla-mini-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb
@ -649,6 +713,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596la-mba95xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb

29
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
};
};
serdes: phy@1ea0000 {
compatible = "fsl,ls1028a-serdes";
reg = <0x00 0x1ea0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
scfg: syscon@1fc0000 {
compatible = "fsl,ls1028a-scfg", "syscon";
reg = <0x0 0x1fc0000 0x0 0x10000>;

60
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
serdes1: phy@1ea0000 {
compatible = "fsl,ls1046a-serdes1";
reg = <0x00 0x1ea0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
big-endian;
status = "disabled";
serdes1_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes1_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes1_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes1_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
serdes2: phy@1eb0000 {
compatible = "fsl,ls1046a-serdes2";
reg = <0x00 0x1eb0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
big-endian;
status = "disabled";
serdes2_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes2_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes2_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes2_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x1000>;

58
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -239,6 +239,64 @@ reset: syscon@1e60000 {
reg = <0x0 0x1e60000 0x0 0x10000>;
};
serdes1: phy@1ea0000 {
compatible = "fsl,ls1088a-serdes1";
reg = <0x00 0x1ea0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes1_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes1_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes1_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes1_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
serdes2: phy@1eb0000 {
compatible = "fsl,ls1088a-serdes2";
reg = <0x00 0x1eb0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes2_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes2_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes2_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes2_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
isc: syscon@1f70000 {
compatible = "fsl,ls1088a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;

98
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -280,6 +280,104 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
serdes1: phy@1ea0000 {
compatible = "fsl,ls2088a-serdes1";
reg = <0x00 0x1ea0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes1_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes1_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes1_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes1_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
serdes1_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes1_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes1_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes1_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
serdes2: phy@1eb0000 {
compatible = "fsl,ls2088a-serdes2";
reg = <0x00 0x1eb0000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes2_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes2_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes2_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes2_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
serdes2_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes2_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes2_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes2_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
isc: syscon@1f70000 {
compatible = "fsl,ls2080a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
/ {
model = "NXP Layerscape LX2160ABLUEBOX3";

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"

4
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
View File

@ -135,6 +135,10 @@ &sata3 {
status = "okay";
};
&serdes_1 {
status = "okay";
};
&uart0 {
status = "okay";
};

4
arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
View File

@ -805,6 +805,10 @@ &rgmii_phy1 {
status = "disabled";
};
&serdes_1 {
status = "okay";
};
&serdes_2 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"

176
arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi Normal file
View File

@ -0,0 +1,176 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file describing the PCIe Mobiveil's GPEX 4.0 IP
// found on LX2160A Rev1
//
// Copyright 2026 NXP
&soc {
pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <256>;
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
<0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
<0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <256>;
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
<0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
};

4
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
View File

@ -325,6 +325,10 @@ &sata3 {
status = "okay";
};
&serdes_1 {
status = "okay";
};
&uart0 {
status = "okay";
};

9
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree Include file for Layerscape-LX2160A Rev1 SoC.
//
// Copyright 2026 NXP
#include "fsl-lx216x.dtsi"
#include "fsl-lx2160a-pcie-mbvl.dtsi"
#include "fsl-lx2160a-serdes.dtsi"

188
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
View File

@ -6,188 +6,6 @@
/dts-v1/;
#include "fsl-lx2160a.dtsi"
&pcie1 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie2 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie3 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie4 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie5 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie6 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&soc {
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x80 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
0x88 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
0x90 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
num-ib-windows = <24>;
status = "disabled";
};
pcie_ep4: pcie-ep@3700000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03700000 0x0 0x00100000
0x98 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie_ep5: pcie-ep@3800000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03800000 0x0 0x00100000
0xa0 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
num-ib-windows = <24>;
status = "disabled";
};
pcie_ep6: pcie-ep@3900000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03900000 0x0 0x00100000
0xa8 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
};
#include "fsl-lx216x.dtsi"
#include "fsl-lx216xa-pcie-gen3.dtsi"
#include "fsl-lx2160a-serdes.dtsi"

167
arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi Normal file
View File

@ -0,0 +1,167 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2160A
// Rev1 and Rev2
//
// Copyright 2026 NXP
&soc {
/* Note on the interpretation of SerDes lane numbering from
* LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
* The letters (A-H) correspond to logical lane numbers in the
* SerDes register map (lane A's registers start with LNAGCR0),
* while the numbers (0-7) correspond to physical lanes as
* routed to pins. SerDes block #1 is flipped in the LX2160A
* floorplan (logical lane A goes to physical lane 7's pins),
* while SerDes blocks #2 and #3 are not. The lanes below are
* listed right to left when looking at that table.
* Both the numbers and the letters are according to the logical
* numbering scheme, and do not account for the flipping.
*/
serdes_1: phy@1ea0000 {
compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes_1_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes_1_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes_1_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes_1_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
serdes_1_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes_1_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes_1_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes_1_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
serdes_2: phy@1eb0000 {
compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes_2_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes_2_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes_2_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes_2_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
serdes_2_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes_2_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes_2_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes_2_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
serdes_3: phy@1ec0000 {
compatible = "fsl,lx2160a-serdes3";
reg = <0x0 0x1ec0000 0x0 0x1e30>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes_3_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes_3_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes_3_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes_3_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
serdes_3_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes_3_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes_3_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes_3_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
};

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
View File

@ -5,7 +5,7 @@
* Author: Gregor Herburger
*/
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-rev1.dtsi"
/ {
reg_vcc3v3: regulator-vcc3v3 {

6
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
View File

@ -8,7 +8,7 @@
#include <dt-bindings/leds/common.h>
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
@ -367,6 +367,10 @@ &pcs_mdio18 {
status = "okay";
};
&serdes_1 {
status = "okay";
};
&serdes_2 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a.dtsi"
/ {
model = "NXP Layerscape LX2162AQDS";

86
arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A
// SoC
//
// Copyright 2026 NXP
&soc {
serdes_1: phy@1ea0000 {
compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes_1_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes_1_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes_1_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes_1_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
serdes_2: phy@1eb0000 {
compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
serdes_2_lane_a: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
serdes_2_lane_b: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
serdes_2_lane_c: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
serdes_2_lane_d: phy@3 {
reg = <3>;
#phy-cells = <0>;
};
serdes_2_lane_e: phy@4 {
reg = <4>;
#phy-cells = <0>;
};
serdes_2_lane_f: phy@5 {
reg = <5>;
#phy-cells = <0>;
};
serdes_2_lane_g: phy@6 {
reg = <6>;
#phy-cells = <0>;
};
serdes_2_lane_h: phy@7 {
reg = <7>;
#phy-cells = <0>;
};
};
};

9
arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2162 SoC
//
// Copyright 2026 NXP
#include "fsl-lx216x.dtsi"
#include "fsl-lx216xa-pcie-gen3.dtsi"
#include "fsl-lx2162a-serdes.dtsi"

181
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi → arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
View File

@ -621,19 +621,6 @@ soc: soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
serdes_1: phy@1ea0000 {
compatible = "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
#phy-cells = <1>;
};
serdes_2: phy@1eb0000 {
compatible = "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
#phy-cells = <1>;
status = "disabled";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
@ -1177,174 +1164,6 @@ sata3: sata@3230000 {
status = "disabled";
};
pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <256>;
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
<0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
<0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <256>;
ppio-wins = <24>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
<0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "aer", "pme", "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
apio-wins = <8>;
ppio-wins = <8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;

257
arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi Normal file
View File

@ -0,0 +1,257 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file describing the PCIe IPs found on the LX2160A Rev2 and LX2162A SoCs
//
// Copyright 2026 NXP
&soc {
pcie1: pcie@3400000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x80 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie2: pcie@3500000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
0x88 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie3: pcie@3600000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
0x90 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
num-ib-windows = <24>;
status = "disabled";
};
pcie4: pcie@3700000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep4: pcie-ep@3700000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03700000 0x0 0x00100000
0x98 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie5: pcie@3800000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep5: pcie-ep@3800000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03800000 0x0 0x00100000
0xa0 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
num-ib-windows = <24>;
status = "disabled";
};
pcie6: pcie@3900000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
bus-range = <0x0 0xff>;
ranges = /* 16-Bit IO Window */
<0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
/* 32-Bit - non-prefetchable */
<0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
/* 64-Bit - prefetchable - 16GB */
<0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
msi-parent = <&its 0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie_ep6: pcie-ep@3900000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03900000 0x0 0x00100000
0xa8 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
};

2
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -423,7 +423,7 @@ usb-hub@8 {
refclk-frequency = <25000000>;
reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
};
/* On Module Audio Codec */
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";

8
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
View File

@ -124,10 +124,10 @@ asrc0: asrc@59000000 {
compatible = "fsl,imx8qm-asrc";
reg = <0x59000000 0x10000>;
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
<&asrc0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
clocks = <&asrc0_lpcg IMX_LPCG_CLK_4>,
<&asrc0_lpcg IMX_LPCG_CLK_4>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
<&clk_dummy>,

3
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -677,6 +677,7 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
/* This property is deprecated, use power supply from the Root Port node. */
vpcie-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
status = "okay";
@ -692,6 +693,8 @@ &pcie0_ep {
&pcieb_port0 {
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
};
&sai0 {

301
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
View File

@ -35,9 +35,9 @@ leds {
pinctrl-0 = <&pinctrl_gpio_led>;
led-1 {
label = "buzzer";
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
default-state = "off";
label = "buzzer";
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
@ -49,11 +49,11 @@ osc_can: clock-osc-can {
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "wm8904_supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
compatible = "regulator-fixed";
regulator-name = "wm8904_supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_wifi_vmmc: regulator-wifi-vmmc {
@ -68,13 +68,13 @@ reg_wifi_vmmc: regulator-wifi-vmmc {
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,routing =
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
@ -82,45 +82,44 @@ sound-wm8904 {
"Headphone Jack", "MICBIAS",
"IN1L", "Headphone Jack";
simple-audio-card,widgets =
"Microphone","Headphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
simple-audio-card,widgets = "Microphone","Headphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
dailink_master: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
};
/* CAN BUS */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
can: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_canbus>;
clocks = <&osc_can>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <10000000>;
};
can: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_canbus>;
clocks = <&osc_can>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <10000000>;
};
};
&fec1 {
@ -177,29 +176,29 @@ rtc@32 {
/* AUDIO */
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
status = "okay";
};
/* USBOTG */
@ -216,8 +215,8 @@ usb_hs_ep: endpoint {
};
&usbotg2 {
dr_mode = "host";
status = "okay";
dr_mode = "host";
status = "okay";
};
/* Wifi */
@ -246,26 +245,26 @@ wifi: wifi@1 {
/* SD-card */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl_canbus: canbusgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82
MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
@ -274,125 +273,125 @@ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
pinctrl_usb_otg: usbotggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
>;
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -542,6 +542,7 @@ &pcie0 {
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
/* This property is deprecated, use power supply from the Root Port node. */
vpcie-supply = <&reg_pcie0>;
supports-clkreq;
status = "okay";
@ -562,6 +563,7 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pcie0>;
};
&sai2 {

516
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts Normal file
View File

@ -0,0 +1,516 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Sonata carrier board for DART-MX8M-MINI
*
* Link: https://variscite.com/carrier-boards/sonata-board/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-var-dart.dtsi"
/ {
model = "Variscite DART-MX8M-MINI on Sonata-Board";
compatible = "variscite,var-dart-mx8mm-sonata",
"variscite,var-dart-mx8mm",
"fsl,imx8mm";
chosen {
stdout-path = &uart1;
};
gpio-keys {
compatible = "gpio-keys";
button-home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-back {
label = "Back";
linux,code = <KEY_BACK>;
gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-emmc {
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
label = "eMMC";
linux,default-trigger = "mmc2";
};
};
clk40m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "can_osc";
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vmmc_usdhc2>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
/* Resistive touch controller */
ads7846: touchscreen@0 {
compatible = "ti,ads7846";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1500000>;
pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
ti,x-max = /bits/ 16 <4008>;
ti,y-min = /bits/ 16 <282>;
ti,y-max = /bits/ 16 <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
};
can0: can@1 {
compatible = "microchip,mcp251xfd";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&clk40m>;
interrupt-parent = <&gpio1>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
spi-max-frequency = <20000000>;
};
};
&ethphy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca9534: gpio@22 {
compatible = "nxp,pca9534";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rgb_sel";
};
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
extcon_ptn5150: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_extcon>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca6408_1: gpio@20 {
compatible = "nxp,pcal6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca6408>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
};
pca6408_2: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
clocks = <&pcie0_refclk>;
status = "okay";
};
&pcie0 {
reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
/* Console */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
wakeup-source;
status = "okay";
};
/* Header */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* Header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
disable-over-current;
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
>;
};
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13
>;
};
pinctrl_extcon: extcongrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
>;
};
pinctrl_pca6408: pca6408grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c6
>;
};
pinctrl_pwm: pwmgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
>;
};
pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1
>;
};
};

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arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi Normal file
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@ -0,0 +1,558 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite DART-MX8M-MINI
*
* Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include "imx8mm.dtsi"
/ {
model = "Variscite DART-MX8M-MINI Module";
compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reg_audio_supply: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "wm8904-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
reg_phy_vddio: regulator-phy-vddio {
compatible = "regulator-fixed";
regulator-name = "vddio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
phy-supply = <&reg_eth_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
vddio-supply = <&reg_phy_vddio>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 {
// BUCK5 in datasheet
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
// BUCK6 in datasheet
regulator-name = "buck4";
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
// BUCK7 in datasheet
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
// BUCK8 in datasheet
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo5_reg: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
clock-names = "mclk";
AVDD-supply = <&ldo5_reg>;
CPVDD-supply = <&ldo5_reg>;
DBVDD-supply = <&reg_audio_supply>;
DCVDD-supply = <&ldo5_reg>;
MICVDD-supply = <&ldo5_reg>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
&mu {
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <1536000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* BT module */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
assigned-clocks = <&clk IMX8MM_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth_iw61x: bluetooth {
compatible = "nxp,88w8987-bt";
};
};
/* WIFI */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
bus-width = <4>;
keep-power-in-suspend;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec1_sleep: fec1sleepgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x140
>;
};
pinctrl_reg_eth_phy: regeth-phygrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140
MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140
MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1
>;
};
};

12
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
View File

@ -55,18 +55,21 @@ key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
wakeup-source;
};
};
@ -165,6 +168,14 @@ pca6408: gpio@21 {
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rgb_sel";
};
};
st33ktpm2xi2c: tpm@2e {
@ -187,6 +198,7 @@ ft5x06_ts: touchscreen@38 {
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
rtc@68 {

14
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Enable Bridge Tied Load (BTL) speaker mode on the Verdin Development Board,
* combining the two loudspeaker outputs for higher output power.
*/
/dts-v1/;
/plugin/;
&nau8822_1a {
nuvoton,spk-btl;
};

88
arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso Normal file
View File

@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Toradex DSI to HDMI Adapter on Verdin DSI_1.
*
* https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
reg_dsi_hdmi: regulator-dsi-hdmi {
compatible = "regulator-fixed";
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-name = "DSI_1_PWR_EN";
};
};
&hdmi_connector {
status = "okay";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&dsi_hdmi_bridge_out>;
};
};
};
&hdmi_lontium_lt8912 {
vdd-supply = <&reg_dsi_hdmi>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_hdmi_bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
dsi_hdmi_bridge_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
/* Verdin I2C_2_DSI */
&i2c2 {
clock-frequency = <10000>;
status = "okay";
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <16000000>;
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&dsi_hdmi_bridge_in>;
};
/* Verdin PWM_3_DSI (SODIMM 19) repurposed as HDMI HPD GPIO */
&pwm1 {
status = "disabled";
};

104
arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso Normal file
View File

@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Toradex DSI to LVDS Adapter on Verdin DSI_1 with Capacitive Touch Display
* 10.1". Used on Dahlia (X17) and Development Board (X48) that expose DSI_1
* via a Samtec LSS-130 connector.
*
* https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds
* https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds
* https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter
* https://www.toradex.com/accessories/verdin-dsi-to-lvds-adapter
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
&{/} {
backlight_pwm3: backlight-pwm3 {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
brightness-levels = <0 45 63 88 119 158 203 255>;
default-brightness-level = <4>;
/* Verdin I2S_2_D_OUT (SODIMM 46) - DSI_1_BKL_EN_LVDS */
enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_3p3v>;
/* Verdin PWM_3_DSI (SODIMM 19) - PWM_3_DSI_LVDS */
pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
};
panel-lvds-bridge {
compatible = "logictechno,lt170410-2whc";
backlight = <&backlight_pwm3>;
power-supply = <&reg_dsi_lvds>;
port {
panel_lvds_bridge_in: endpoint {
remote-endpoint = <&dsi_lvds_bridge_out>;
};
};
};
reg_dsi_lvds: regulator-dsi-lvds {
compatible = "regulator-fixed";
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-name = "DSI_1_PWR_EN";
};
};
&atmel_mxt_ts {
vdd-supply = <&reg_dsi_lvds>;
status = "okay";
};
&lcdif {
status = "okay";
};
&lvds_ti_sn65dsi84 {
vcc-supply = <&reg_dsi_lvds>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_lvds_bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@2 {
reg = <2>;
dsi_lvds_bridge_out: endpoint {
remote-endpoint = <&panel_lvds_bridge_in>;
};
};
};
};
&mipi_dsi {
samsung,esc-clock-frequency = <16000000>;
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&dsi_lvds_bridge_in>;
};

129
arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso Normal file
View File

@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Toradex Capacitive Touch Display 10.1" on Verdin DSI_1.
* On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a
* Samtec LSS-130 connector and requires the Toradex DSI Display Adapter
* to convert to FFC/FPC connector.
*
* https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi
* https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-dsi
* https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter
* https://www.toradex.com/accessories/verdin-dsi-display-adapter
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
&{/} {
backlight_pwm3: backlight-pwm3 {
compatible = "pwm-backlight";
brightness-levels = <0 45 63 88 119 158 203 255>;
default-brightness-level = <4>;
power-supply = <&reg_3p3v>;
/* Verdin PWM_3_DSI (SODIMM 19) */
pwms = <&pwm1 0 6666667 0>;
};
panel-lvds-bridge {
compatible = "riverdi,rvt101hvlnwc00", "panel-lvds";
backlight = <&backlight_pwm3>;
data-mapping = "vesa-24";
height-mm = <136>;
width-mm = <217>;
panel-timing {
clock-frequency = <71100000>;
de-active = <1>;
hactive = <1280>;
hback-porch = <64 64 64>;
hfront-porch = <36 36 36>;
hsync-active = <0>;
hsync-len = <24 24 24>;
pixelclk-active = <1>;
vactive = <800>;
vback-porch = <24 24 24>;
vfront-porch = <8 8 8>;
vsync-active = <0>;
vsync-len = <8 8 8>;
};
port {
panel_lvds_bridge_in: endpoint {
remote-endpoint = <&dsi_lvds_bridge_out>;
};
};
};
};
/* Verdin I2C_2_DSI */
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
bridge@2c {
compatible = "ti,sn65dsi83";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_10_dsi>;
/* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */
enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
vcc-supply = <&reg_1p8v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_lvds_bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@2 {
reg = <2>;
dsi_lvds_bridge_out: endpoint {
remote-endpoint = <&panel_lvds_bridge_in>;
};
};
};
};
touchscreen@41 {
compatible = "ilitek,ili2132";
reg = <0x41>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
/* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */
/* Rising edge avoids spurious interrupts from the noisy falling edge. */
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_RISING>;
/* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */
reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <16000000>;
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&dsi_lvds_bridge_in>;
};

129
arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso Normal file
View File

@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Toradex Capacitive Touch Display 7" on Verdin DSI_1.
* On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a
* Samtec LSS-130 connector and requires the Toradex DSI Display Adapter
* to convert to FFC/FPC connector.
*
* https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi
* https://www.toradex.com/accessories/capacitive-touch-display-7-inch-dsi
* https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter
* https://www.toradex.com/accessories/verdin-dsi-display-adapter
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
&{/} {
backlight_pwm3: backlight-pwm3 {
compatible = "pwm-backlight";
brightness-levels = <0 45 63 88 119 158 203 255>;
default-brightness-level = <4>;
power-supply = <&reg_3p3v>;
/* Verdin PWM_3_DSI (SODIMM 19) */
pwms = <&pwm1 0 6666667 0>;
};
panel-lvds-bridge {
compatible = "riverdi,rvt70hslnwca0", "panel-lvds";
backlight = <&backlight_pwm3>;
data-mapping = "vesa-24";
height-mm = <86>;
width-mm = <154>;
panel-timing {
clock-frequency = <51200000>;
de-active = <1>;
hactive = <1024>;
hback-porch = <100 100 100>;
hfront-porch = <16 160 216>;
hsync-active = <0>;
hsync-len = <50 60 140>;
pixelclk-active = <1>;
vactive = <600>;
vback-porch = <23 23 23>;
vfront-porch = <1 12 126>;
vsync-active = <0>;
vsync-len = <1 10 20>;
};
port {
panel_lvds_bridge_in: endpoint {
remote-endpoint = <&dsi_lvds_bridge_out>;
};
};
};
};
/* Verdin I2C_2_DSI */
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
bridge@2c {
compatible = "ti,sn65dsi83";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_10_dsi>;
/* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */
enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
vcc-supply = <&reg_1p8v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_lvds_bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@2 {
reg = <2>;
dsi_lvds_bridge_out: endpoint {
remote-endpoint = <&panel_lvds_bridge_in>;
};
};
};
};
touchscreen@41 {
compatible = "ilitek,ili2132";
reg = <0x41>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
/* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */
/* Rising edge avoids spurious interrupts from the noisy falling edge. */
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_RISING>;
/* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */
reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <16000000>;
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&dsi_lvds_bridge_in>;
};

14
arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Verdin iMX8M Mini UART_4 for Cortex-M4F
*/
/dts-v1/;
/plugin/;
/* Verdin UART_4 */
&uart4 {
status = "reserved";
};

33
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@ -52,6 +52,18 @@ hdmi_connector: hdmi-connector {
status = "disabled";
};
imx8mm-cm4 {
compatible = "fsl,imx8mm-cm4";
clocks = <&clk IMX8MM_CLK_M4_DIV>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>,
<&rsc_table>;
syscon = <&src>;
};
/* Carrier Board Supplies */
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
@ -164,6 +176,27 @@ reserved-memory {
/* Use the kernel configuration settings instead */
/delete-node/ linux,cma;
vdev0vring0: vdev0vring0@55000000 {
reg = <0 0x55000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@55008000 {
reg = <0 0x55008000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@550ff000 {
reg = <0 0x550ff000 0 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@55400000 {
compatible = "shared-dma-pool";
reg = <0 0x55400000 0 0x100000>;
no-map;
};
};
};

48
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts
View File

@ -7,6 +7,7 @@
#include <dt-bindings/usb/pd.h>
#include "imx8mn-var-som.dtsi"
#include "imx8mn-var-som-wifi-brcm-legacy.dtsi"
/ {
model = "RVE gateway";
@ -207,8 +208,16 @@ &usbotg1 {
/* SD interface on expansion connector. */
&usdhc2 {
vmmc-supply = <&reg_3p3v>;
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
@ -276,10 +285,45 @@ MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x00000156 /* B */
>;
};
/* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

19
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 Variscite Ltd.
*/
#include "imx8mn-var-som-symphony.dts"
#include "imx8mn-var-som-wifi-brcm-legacy.dtsi"
&bluetooth_iw61x {
status = "disabled";
};
&iw61x_pwrseq {
status = "disabled";
};
&usdhc1 {
/delete-property/ mmc-pwrseq;
};

162
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
View File

@ -8,13 +8,19 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mn-var-som.dtsi"
#include "imx8mn-var-som-wifi-bt-iw61x.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
chosen {
stdout-path = &uart4;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -24,6 +30,7 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
};
gpio-keys {
@ -33,18 +40,21 @@ key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
wakeup-source;
};
};
@ -69,7 +79,24 @@ reg_per_3v3: regulator-peripheral-3v3 {
};
&ethphy {
reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&i2c2 {
@ -136,6 +163,28 @@ typec1_dr_sw: endpoint {
};
&i2c3 {
pca6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rgb_sel";
};
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5406";
@ -149,6 +198,7 @@ ft5x06_ts: touchscreen@38 {
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
rtc@68 {
@ -157,6 +207,26 @@ rtc@68 {
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
/* Header */
&uart1 {
pinctrl-names = "default";
@ -171,6 +241,13 @@ &uart3 {
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@ -189,6 +266,20 @@ usb1_drd_sw: endpoint {
};
};
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
@ -203,6 +294,20 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
@ -215,6 +320,12 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
@ -234,4 +345,53 @@ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

19
arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 Variscite Ltd.
*/
/* WIFI */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
#address-cells = <1>;
#size-cells = <0>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};

46
arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi Normal file
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 Variscite Ltd.
*/
/ {
iw61x_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>;
bluetooth_iw61x: bluetooth {
compatible = "nxp,88w8987-bt";
};
};
/* WIFI */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
mmc-pwrseq = <&iw61x_pwrseq>;
};
&iomuxc {
pinctrl_bt: bluetoothgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x140
MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1
>;
};
};

372
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@ -11,8 +11,11 @@ / {
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
chosen {
stdout-path = &uart4;
clk40m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "can_osc";
};
memory@40000000 {
@ -20,6 +23,14 @@ memory@40000000 {
reg = <0x0 0x40000000 0 0x40000000>;
};
reg_audio_supply: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "wm8904-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -39,6 +50,41 @@ reg_3v3_fixed: regulator-3v3-fixed {
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_phy_vddio: regulator-phy-vddio {
compatible = "regulator-fixed";
regulator-name = "vddio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai5>;
};
};
};
&A53_0 {
@ -91,6 +137,19 @@ touchscreen@0 {
ti,keep-vref-on;
wakeup-source;
};
/* CAN controller */
can0: can@1 {
compatible = "microchip,mcp251xfd";
reg = <1>;
clocks = <&clk40m>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <20000000>;
microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
@ -100,28 +159,29 @@ &fec1 {
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-supply = <&reg_eth_phy>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
ethphy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
/*
* Deassert delay:
* ADIN1300 requires 5ms.
* AR8033 requires 1ms.
*/
reset-deassert-us = <20000>;
reset-deassert-us = <100000>;
vddio-supply = <&reg_phy_vddio>;
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -248,18 +308,55 @@ eeprom_som: eeprom@52 {
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* TODO: configure audio, as of now just put a placeholder */
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
status = "disabled";
#sound-dai-cells = <0>;
clocks = <&clk IMX8MN_CLK_SAI5_ROOT>;
clock-names = "mclk";
AVDD-supply = <&ldo5_reg>;
CPVDD-supply = <&ldo5_reg>;
DBVDD-supply = <&reg_audio_supply>;
DCVDD-supply = <&ldo5_reg>;
MICVDD-supply = <&ldo5_reg>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
&sai5 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MN_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <1536000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -274,23 +371,7 @@ &uart2 {
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
/* WIFI */
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@ -299,25 +380,6 @@ &usdhc1 {
non-removable;
keep-power-in-suspend;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* eMMC */
@ -341,6 +403,13 @@ &wdog1 {
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c0
MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
@ -367,7 +436,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
@ -391,180 +460,161 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
>;
};
pinctrl_reg_eth_phy: regethphygrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};

4
arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
View File

@ -775,6 +775,10 @@ &micfil {
status = "okay";
};
&mu2 {
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";

15
arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
&flexcan2 {
status = "okay"; /* can2 pin conflict with pdm */
};
&micfil {
status = "disabled";
};

97
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
@ -50,6 +51,25 @@ status {
};
};
can_mux: mux-controller-0 {
compatible = "gpio-mux";
#mux-control-cells = <0>;
#mux-state-cells = <1>;
mux-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>;
};
can_mux_pinctrl: pinctrl-gpiomux {
compatible = "pinctrl-multiplexer";
can_fun: can-grp {
mux-states = <&can_mux 1>;
};
pdm_fun: pdm-grp {
mux-states = <&can_mux 0>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
@ -453,7 +473,7 @@ &flexcan1 {
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-0 = <&pinctrl_flexcan2>, <&can_fun>;
phys = <&flexcan_phy 1>;
status = "disabled";/* can2 pin conflict with pdm */
};
@ -636,6 +656,35 @@ adv7535_out: endpoint {
};
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
orientation-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
port {
typec_con_hs: endpoint {
remote-endpoint = <&usb3_data_hs>;
};
};
};
};
};
&i2c3 {
@ -720,7 +769,7 @@ &lcdif3 {
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
@ -772,6 +821,7 @@ &pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
/* This property is deprecated, use power supply from the Root Port node. */
vpcie-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
supports-clkreq;
@ -786,6 +836,8 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
};
&pwm1 {
@ -851,7 +903,41 @@ &uart2 {
status = "okay";
};
&usb3_phy0 {
fsl,phy-tx-vref-tune-percent = <122>;
fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
fsl,phy-comp-dis-tune-percent = <115>;
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
fsl,phy-pcs-tx-swing-full-percent = <100>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
role-switch-default-mode = "peripheral";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_data_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usb3_phy1 {
fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
fsl,phy-tx-vref-tune-percent = <116>;
status = "okay";
};
@ -1179,6 +1265,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10

2
arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
View File

@ -562,6 +562,8 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
>;
};

82
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi
View File

@ -32,29 +32,29 @@ led-0 {
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
cpu-supply = <&buck2>;
};
&i2c1 {
@ -220,7 +220,7 @@ &wdog1 {
&iomuxc {
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19
>;
};
@ -233,15 +233,15 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
>;
};
pinctrl_mcp23018: mcp23018grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100
>;
};
@ -253,15 +253,15 @@ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150
@ -277,8 +277,8 @@ MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154
@ -293,8 +293,8 @@ MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152
@ -309,34 +309,34 @@ MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};

81
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso Normal file
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@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Martin Schmiedel
*/
/dts-v1/;
/plugin/;
&backlight_lvds0 {
status = "okay";
};
&panel_lvds0 {
compatible = "auo,g133han01";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
panel_in_lvds1: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
ldb_lvds_ch0: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
port@2 {
reg = <2>;
ldb_lvds_ch1: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
// Update VIDEO_PLL1 frequency
&media_blk_ctrl {
assigned-clock-rates = <500000000>, <200000000>,
<0>, <0>, <500000000>,
<988400000>;
};
&pwm3 {
status = "okay";
};

43
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Paul Gerber
*/
/dts-v1/;
/plugin/;
&backlight_lvds0 {
status = "okay";
};
&panel_lvds0{
compatible = "tianma,tm070jvhg33";
status = "okay";
panel-timing {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <64>;
hback-porch = <5>;
hsync-len = <1>;
vfront-porch = <40>;
vback-porch = <2>;
vsync-len = <1>;
de-active = <1>;
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
};
&pwm3 {
status = "okay";
};

43
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Paul Gerber
*/
/dts-v1/;
/plugin/;
&backlight_lvds1 {
status = "okay";
};
&panel_lvds1{
compatible = "tianma,tm070jvhg33";
status = "okay";
panel-timing {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <64>;
hback-porch = <5>;
hsync-len = <1>;
vfront-porch = <40>;
vback-porch = <2>;
vsync-len = <1>;
de-active = <1>;
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
};
&pwm2 {
status = "okay";
};

380
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts Normal file
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@ -0,0 +1,380 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Paul Gerber
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mp-tqma8mpqs.dtsi"
/ {
model = "TQ-Systems i.MX8MPlus TQMa8MPxS on MB-SMARC-2";
compatible = "tq,imx8mp-tqma8mpqs-mb-smarc-2", "tq,imx8mp-tqma8mpqs", "fsl,imx8mp";
chassis-type = "embedded";
chosen {
stdout-path = &uart3;
};
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
mmc0 = &usdhc3;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &snvs_rtc;
spi0 = &flexspi;
spi1 = &ecspi1;
spi2 = &ecspi2;
spi3 = &ecspi3;
};
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm3 0 100000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&expander0 0 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_12v0>;
status = "disabled";
};
backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 100000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_12v0>;
status = "disabled";
};
hdmi-connector {
compatible = "hdmi-connector";
label = "X6";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
panel_lvds0: panel-lvds0 {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
backlight = <&backlight_lvds0>;
power-supply = <&reg_lvds0>;
status = "disabled";
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
panel_lvds1: panel-lvds1 {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
backlight = <&backlight_lvds1>;
power-supply = <&reg_lvds1>;
status = "disabled";
port {
panel_in_lvds1: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "12V0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
reg_lvds0: regulator-lvds0 {
compatible = "regulator-fixed";
regulator-name = "LCD0_VDD_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lvds1: regulator-lvds1 {
compatible = "regulator-fixed";
regulator-name = "LCD1_VDD_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x38000000>;
alloc-ranges = <0 0x40000000 0 0x78000000>;
linux,cma-default;
};
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
audio-asrc = <&easrc>;
audio-cpu = <&sai5>;
audio-codec = <&tlv320aic3x04>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
usb-connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
label = "X4";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbcon0>;
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
port {
usb_dr_connector: endpoint {
remote-endpoint = <&usb3_dwc>;
};
};
};
};
&easrc {
status = "okay";
};
&ecspi1 {
status = "okay";
};
&eqos {
status = "okay";
};
&ethphy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <0>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_LAN;
function-enumerator = <0>;
default-state = "keep";
};
};
};
&ethphy3 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <0>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_LAN;
function-enumerator = <0>;
default-state = "keep";
};
};
};
&fec {
status = "okay";
};
&flexcan1 {
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&flexcan2 {
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clock-names = "mclk";
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
iov-supply = <&reg_1v8>;
ldoin-supply = <&reg_3v3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
};
eeprom2: eeprom@57 {
compatible = "atmel,24c32";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_3v3>;
};
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel_in_lvds0>;
};
&ldb_lvds_ch1 {
remote-endpoint = <&panel_in_lvds1>;
};
&lcdif1 {
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pcie_phy {
fsl,clkreq-unsupported;
status = "okay";
};
&pcie {
status = "okay";
};
&reg_usdhc2_vmmc {
startup-delay-us = <100>;
off-on-delay-us = <200000>;
status = "okay";
};
&reg_usdhc2_vqmmc {
status = "okay";
};
&sai3 {
status = "okay";
};
&sai5 {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
port {
usb3_dwc: endpoint {
remote-endpoint = <&usb_dr_connector>;
};
};
};
&usdhc2 {
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
no-mmc;
no-sdio;
status = "okay";
};

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733
arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts Normal file
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@ -0,0 +1,733 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Sonata carrier board for DART-MX8M-PLUS
*
* Link: https://variscite.com/carrier-boards/sonata-board/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-var-dart.dtsi"
/ {
model = "Variscite DART-MX8M-PLUS on Sonata-Board";
compatible = "variscite,var-dart-mx8mp-sonata",
"variscite,var-dart-mx8mp",
"fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
gpio-keys {
compatible = "gpio-keys";
button-home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-back {
label = "Back";
linux,code = <KEY_BACK>;
gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-emmc {
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
label = "eMMC";
linux,default-trigger = "mmc2";
};
};
native-hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI OUT";
type = "a";
port {
hdmi_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
clk40m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "can_osc";
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vmmc_usdhc2>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
sound-xcvr {
compatible = "fsl,imx-audio-card";
model = "imx-audio-xcvr";
pri-dai-link {
link-name = "XCVR PCM";
cpu {
sound-dai = <&xcvr>;
};
};
};
};
&aud2htx {
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
ads7846: touchscreen@0 {
compatible = "ti,ads7846";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1500000>;
pendown-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
ti,x-max = /bits/ 16 <4008>;
ti,y-min = /bits/ 16 <282>;
ti,y-max = /bits/ 16 <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
};
can0: can@1 {
compatible = "microchip,mcp251xfd";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
interrupt-parent = <&gpio1>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
clocks = <&clk40m>;
spi-max-frequency = <20000000>;
};
};
&eqos {
mdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&reg_phy_vddio>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
};
&ethphy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&hdmi_pai {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca9534: gpio@22 {
compatible = "nxp,pca9534";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
eth10g-en-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "eth10g_sel";
};
pcie2-en-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "pcie2_sel";
};
/* RGB_SEL
* Keep signal low and not floating
*/
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds_brg_en";
};
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_extcon>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca6408_1: gpio@20 {
compatible = "nxp,pcal6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca6408>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
};
pca6408_2: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
};
};
&lcdif3 {
status = "okay";
};
&pcie {
reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
/* Console */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* Header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usb3_phy0 {
fsl,phy-tx-vref-tune-percent = <122>;
fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
fsl,phy-comp-dis-tune-percent = <115>;
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
fsl,phy-pcs-tx-swing-full-percent = <100>;
status = "okay";
};
&usb3_phy1 {
fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
fsl,phy-tx-vref-tune-percent = <116>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&xcvr {
#sound-dai-cells = <0>;
status = "okay";
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c6
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16
>;
};
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x12
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x12
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x12
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x12
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x12
>;
};
pinctrl_extcon: extcongrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x1d0
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154
MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0xc6
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c2
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c2
>;
};
pinctrl_pca6408: pca6408grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x1c6
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xc0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
};

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arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite DART-MX8M-PLUS
*
* Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include "imx8mp.dtsi"
/ {
model = "Variscite DART-MX8M-PLUS Module";
compatible = "variscite,var-dart-mx8mp", "fsl,imx8mp";
reg_audio_supply: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "wm8904-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_phy_vddio: regulator-phy-vddio {
compatible = "regulator-fixed";
regulator-name = "vddio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 8 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
vddio-supply = <&reg_phy_vddio>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
clock-names = "mclk";
AVDD-supply = <&reg_audio_supply>;
CPVDD-supply = <&reg_audio_supply>;
DBVDD-supply = <&reg_audio_supply>;
DCVDD-supply = <&reg_audio_supply>;
MICVDD-supply = <&reg_audio_supply>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
pca9450: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&mu2 {
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <11536000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
<&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* BT module */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
assigned-clocks = <&clk IMX8MP_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth_iw61x: bluetooth {
compatible = "nxp,88w8987-bt";
};
};
/* WIFI */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0xc0
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x150
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140
MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0xc0
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0
>;
};
};

389
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts
View File

@ -13,6 +13,31 @@ chosen {
stdout-path = &uart2;
};
gpio-keys {
compatible = "gpio-keys";
button-back {
label = "Back";
linux,code = <KEY_BACK>;
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-menu {
label = "Menu";
linux,code = <KEY_MENU>;
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
@ -23,6 +48,34 @@ led-0 {
};
};
native-hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI OUT";
type = "a";
port {
hdmi_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_fec_phy: regulator-fec-phy {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@ -43,12 +96,92 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
states = <3300000 0x0 1800000 0x1>;
vin-supply = <&ldo5>;
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
};
&aud2htx {
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&eqos {
mdio {
ethphy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <5>;
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&reg_phy_vddio>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&hdmi_pai {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* GPIO expander */
@ -70,6 +203,112 @@ usb3-sata-sel-hog {
line-name = "usb3_sata_sel";
};
};
/* USB Type-C Controller */
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
pinctrl-2 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pcal6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rgb_sel";
};
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
interrupt-parent = <&gpio5>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
&lcdif3 {
status = "okay";
};
&pcie {
reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
clocks = <&pcie0_refclk>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
/* Header UART */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Console */
@ -79,6 +318,59 @@ &uart2 {
status = "okay";
};
/* Header UART */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_0 {
adp-disable;
dr_mode = "otg";
hnp-disable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
srp-disable;
usb-role-switch;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usb3_phy0 {
fsl,phy-comp-dis-tune-percent = <115>;
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
fsl,phy-pcs-tx-swing-full-percent = <100>;
fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
fsl,phy-tx-vref-tune-percent = <122>;
status = "okay";
};
&usb3_phy1 {
fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
fsl,phy-tx-vref-tune-percent = <116>;
status = "okay";
};
/* SD-card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@ -93,6 +385,54 @@ &usdhc2 {
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x16
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x12
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x12
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x12
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
@ -100,12 +440,52 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
@ -113,6 +493,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4

12
arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
View File

@ -180,8 +180,11 @@ led@1 {
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@25 {
@ -415,6 +418,13 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c2
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c2
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0

1
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1599,6 +1599,7 @@ xcvr: xcvr@30cc0000 {
<0x30cc0e00 0x080>;
reg-names = "ram", "regs", "rxfifo",
"txfifo";
#sound-dai-cells = <0>;
interrupts = /* XCVR IRQ 0 */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
/* XCVR IRQ 1 */

84
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mq.dtsi"
/ {
@ -330,6 +331,35 @@ vgen6_reg: vgen6 {
};
};
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio3>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
orientation-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
port {
typec_con_hs: endpoint {
remote-endpoint = <&usb3_data_hs>;
};
};
};
};
};
&lcdif {
@ -403,6 +433,7 @@ &pcie1 {
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
/* This property is deprecated, use power supply from the Root Port node. */
vpcie-supply = <&reg_pcie1>;
vpcie3v3aux-supply = <&reg_pcie1>;
vph-supply = <&vgen5_reg>;
@ -422,6 +453,8 @@ &pcie1_ep {
&pcie1_port0 {
reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pcie1>;
vpcie3v3aux-supply = <&reg_pcie1>;
};
&pgc_gpu {
@ -498,6 +531,41 @@ &uart1 {
status = "okay";
};
&uart3 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
role-switch-default-mode = "peripheral";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_data_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usb3_phy1 {
status = "okay";
};
@ -650,6 +718,13 @@ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
@ -657,6 +732,15 @@ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83

4
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -215,7 +215,7 @@ vibrator {
compatible = "gpio-vibrator";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_haptic>;
enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
vcc-supply = <&reg_3v3_p>;
};
@ -856,7 +856,7 @@ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
pinctrl_wifi_pwr_en: wifipwrengrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
>;
};

23
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1598,6 +1598,29 @@ aips4: bus@32c00000 { /* AIPS4 */
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
dcss: display-controller@32e00000 {
compatible = "nxp,imx8mq-dcss";
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
interrupts = <6>, <8>, <9>;
interrupt-names = "ctxld", "ctxld_kick", "vblank";
interrupt-parent = <&irqsteer>;
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_VIDEO2_PLL_OUT>,
<&clk IMX8MQ_CLK_DISP_DTRC>;
clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
<&clk IMX8MQ_CLK_DISP_RTRM>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_27M>;
assigned-clock-rates = <800000000>,
<400000000>;
status = "disabled";
};
irqsteer: interrupt-controller@32e2d000 {
compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;

3
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -812,6 +812,7 @@ &pciea {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
/* This property is deprecated, use power supply from the Root Port node. */
vpcie-supply = <&reg_pciea>;
vpcie3v3aux-supply = <&reg_pciea>;
supports-clkreq;
@ -820,6 +821,8 @@ &pciea {
&pciea_port0 {
reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pciea>;
vpcie3v3aux-supply = <&reg_pciea>;
};
&pcieb {

38
arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
View File

@ -74,6 +74,31 @@ &asrc1_lpcg {
};
&audio_subsys {
spdif1: spdif@59030000 {
compatible = "fsl,imx8qm-spdif";
reg = <0x59030000 0x10000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
clocks = <&spdif1_lpcg IMX_LPCG_CLK_4>, /* core */
<&clk_dummy>, /* rxtx0 */
<&spdif1_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */
<&clk_dummy>, /* rxtx2 */
<&clk_dummy>, /* rxtx3 */
<&clk_dummy>, /* rxtx4 */
<&audio_ipg_clk>, /* rxtx5 */
<&clk_dummy>, /* rxtx6 */
<&clk_dummy>, /* rxtx7 */
<&clk_dummy>; /* spba */
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
dmas = <&edma0 10 0 5>, <&edma0 11 0 4>;
dma-names = "rx", "tx";
power-domains = <&pd IMX_SC_R_SPDIF_1>;
status = "disabled";
};
sai4: sai@59080000 {
compatible = "fsl,imx8qm-sai";
@ -109,6 +134,19 @@ sai5: sai@59090000 {
status = "disabled";
};
spdif1_lpcg: clock-controller@59430000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59430000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>;
clock-output-names = "spdif1_lpcg_tx_clk",
"spdif1_lpcg_gclkw";
power-domains = <&pd IMX_SC_R_SPDIF_1>;
status = "disabled";
};
sai4_lpcg: clock-controller@59480000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59480000 0x10000>;

15
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View File

@ -8,6 +8,21 @@
/delete-node/ &adma_pwm_lpcg;
&dma_subsys {
lpuart4: serial@5a0a0000 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
reg = <0x5a0a0000 0x1000>;
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&uart4_lpcg IMX_LPCG_CLK_4>, <&uart4_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_4>;
dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
dma-names = "rx","tx";
status = "disabled";
};
uart4_lpcg: clock-controller@5a4a0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a4a0000 0x10000>;

21
arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
View File

@ -3,6 +3,27 @@
* Copyright 2019-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&lsio_subsys {
lsio_mu8: mailbox@5d230000 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d230000 0x10000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_8A>;
status = "disabled";
};
lsio_mu8b: mailbox@5d2c0000 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d2c0000 0x10000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
fsl,mu-side-b;
power-domains = <&pd IMX_SC_R_MU_8B>;
status = "disabled";
};
};
&lsio_gpio0 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";

504
arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts Normal file
View File

@ -0,0 +1,504 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Symphony carrier board for VAR-SOM-MX8 QuadMax
*
* Link: https://variscite.com/carrier-boards/symphony-board/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "imx8qm-var-som.dtsi"
/ {
model = "Variscite VAR-SOM-MX8 on Symphony evaluation board";
compatible = "variscite,var-som-imx8qm-symphony",
"variscite,var-som-imx8qm", "fsl,imx8qm";
chosen {
stdout-path = &lpuart0;
};
gpio-keys {
compatible = "gpio-keys";
button-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
button-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
button-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-heartbeat {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
reg_fec_phy: regulator-fec-phy {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <20000>;
vin-supply = <&reg_vselect>;
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&lsio_gpio0 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vselect: regulator-vselect {
compatible = "regulator-fixed";
regulator-name = "reg_vselect";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
gpio = <&pca9534 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ethphy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&fec1 {
mdio {
ethphy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <5>;
vddio-supply = <&reg_phy_vddio>;
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&hsio_phy {
fsl,hsio-cfg = "pciea-pcieb-sata";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&lsio_gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
};
/* USB Type-C Controller */
typec_ptn5150: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
interrupt-parent = <&lsio_gpio3>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
};
};
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pca6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
/* RGB_SEL */
lvds-brg-enable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds_brg_en";
};
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
};
/* Capacitive touch */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5406";
pinctrl-names = "default";
reg = <0x38>;
pinctrl-0 = <&pinctrl_captouch>;
interrupt-parent = <&lsio_gpio0>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
&lpspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi1>;
cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* console */
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
/* header */
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
/* header */
&lpuart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart4>;
status = "okay";
};
&pca9534 {
usb3-signal-route-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "usb3_signal_route";
};
};
&pciea{
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
status = "okay";
};
&pciea_port0 {
reset-gpios = <&pca6408 1 GPIO_ACTIVE_LOW>;
};
&usb3_phy {
status = "okay";
};
&usbotg1 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
vbus-supply = <&reg_usb_otg1_vbus>;
srp-disable;
hnp-disable;
adp-disable;
disable-over-current;
status = "okay";
};
&usbotg3 {
status = "okay";
};
&usbotg3_cdns3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&usbphy1 {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000021
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048
IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048
IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048
IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048
IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048
IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048
IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048
IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048
IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048
IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048
>;
};
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021
IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021
>;
};
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <
IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021
IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA 0xc6000020
IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL 0xc6000020
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
IMX8QM_ENET1_MDC_DMA_I2C4_SCL 0xc6000020
IMX8QM_ENET1_MDIO_DMA_I2C4_SDA 0xc6000020
>;
};
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <
IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004c
IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004c
IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004c
IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020
IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020
>;
};
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
IMX8QM_M40_GPIO0_01_DMA_UART4_TX 0x06000020
IMX8QM_M40_GPIO0_00_DMA_UART4_RX 0x06000020
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021
>;
};
pinctrl_usbotg1: otg1grp {
fsl,pins = <
IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000048
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x00000021
>;
};
};

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arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite VAR-SOM-MX8
*
* Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include "imx8qm.dtsi"
/ {
model = "Variscite i.MX8QM VAR-SOM-MX8 Module";
compatible = "variscite,var-som-imx8qm", "fsl,imx8qm";
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reg_audio_supply: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "wm8904-supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_phy_vddio: regulator-phy-vddio {
compatible = "regulator-fixed";
regulator-name = "vddio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
vdev0vring0: memory@90000000 {
reg = <0 0x90000000 0 0x8000>;
no-map;
};
vdev0vring1: memory@90008000 {
reg = <0 0x90008000 0 0x8000>;
no-map;
};
vdev1vring0: memory@90010000 {
reg = <0 0x90010000 0 0x8000>;
no-map;
};
vdev1vring1: memory@90018000 {
reg = <0 0x90018000 0 0x8000>;
no-map;
};
rsc_table0: memory@900ff000 {
reg = <0 0x900ff000 0 0x1000>;
no-map;
};
vdev2vring0: memory@90100000 {
reg = <0 0x90100000 0 0x8000>;
no-map;
};
vdev2vring1: memory@90108000 {
reg = <0 0x90108000 0 0x8000>;
no-map;
};
vdev3vring0: memory@90110000 {
reg = <0 0x90110000 0 0x8000>;
no-map;
};
vdev3vring1: memory@90118000 {
reg = <0 0x90118000 0 0x8000>;
no-map;
};
rsc_table1: memory@901ff000 {
reg = <0 0x901ff000 0 0x1000>;
no-map;
};
vdevbuffer: memory@90400000 {
compatible = "shared-dma-pool";
reg = <0 0x90400000 0 0x100000>;
no-map;
};
dsp_reserved: memory@92400000 {
reg = <0 0x92400000 0 0x1000000>;
no-map;
};
dsp_vdev0vring0: memory@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: memory@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: memory@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
/* VAR-SOM-MX8QM doesn't have 1GB variant */
alloc-ranges = <0 0xc0000000 0 0x3c000000>;
size = <0 0x3c000000>;
linux,cma-default;
reusable;
};
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&esai0>;
};
};
};
&acm {
status = "okay";
};
&asrc0 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&asrc1 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&cm41_intmux {
status = "okay";
};
&esai0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&esai0_lpcg IMX_LPCG_CLK_4>;
assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
#sound-dai-cells = <0>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&reg_phy_vddio>;
};
};
};
&gpio0_mipi_csi0 {
status = "disabled";
};
&gpio0_mipi_csi1 {
status = "disabled";
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
AVDD-supply = <&reg_audio_supply>;
CPVDD-supply = <&reg_audio_supply>;
DBVDD-supply = <&reg_audio_supply>;
DCVDD-supply = <&reg_audio_supply>;
MICVDD-supply = <&reg_audio_supply>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
/* Bluetooth */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
uart-has-rtscts;
status = "okay";
};
&mu_m0{
status = "okay";
};
&mu1_m0{
status = "okay";
};
&mu2_m0{
status = "okay";
};
&rtc {
status = "disabled";
};
&sai6 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai6_lpcg IMX_LPCG_CLK_4>;
assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
status = "okay";
};
&sai7 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai7_lpcg IMX_LPCG_CLK_4>;
assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
status = "okay";
};
&thermal_zones {
pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* WIFI */
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_esai0: esai0grp {
fsl,pins = <
IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040
IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040
IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040
IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040
IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040
IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040
IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048
IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041
IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041
IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041
IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041
IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020
IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020
IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020
IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020
IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
>;
};
pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
fsl,pins = <
IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
/* GPIOs used by user space WiFi init */
IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c
IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021
IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021
IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
>;
};
};

7
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#include <dt-bindings/thermal/thermal.h>
@ -330,6 +331,12 @@ clk: clock-controller {
#clock-cells = <2>;
};
scu_key: keys {
compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
iomuxc: pinctrl {
compatible = "fsl,imx8qm-iomuxc";
};

3
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -732,6 +732,7 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
/* This property is deprecated, use power supply from the Root Port node. */
vpcie-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
supports-clkreq;
@ -748,6 +749,8 @@ &pcie0_ep {
&pcieb_port0 {
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pcieb>;
vpcie3v3aux-supply = <&reg_pcieb>;
};
&scu_key {

37
arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts
View File

@ -8,8 +8,20 @@
#include "imx8ulp-evk.dts"
/ {
model = "NXP i.MX8ULP EVK9";
model = "NXP i.MX8ULP 9x9 EVK";
compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp";
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
button-power-on {
label = "PowerOn";
gpios = <&gpiof 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
};
};
&btcpu {
@ -43,6 +55,12 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
&pinctrl_gpio_keys {
fsl,pins = <
MX8ULP_PAD_PTF11__PTF11 0x3
>;
};
&pinctrl_usb1 {
fsl,pins = <
MX8ULP_PAD_PTE16__USB0_ID 0x10003
@ -57,6 +75,23 @@ MX8ULP_PAD_PTE20__USB1_OC 0x10003
>;
};
&pinctrl_lpuart6 {
fsl,pins = <
MX8ULP_PAD_PTF18__LPUART6_TX 0x3
MX8ULP_PAD_PTF19__LPUART6_RX 0x3
MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x3
MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x3
>;
};
&lpspi5 { /* conflict with lpuart6 PAD_PTF16-19 */
status = "disabled";
};
&sai5 {
status = "disabled";
};
&sai6 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai6>;

69
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx8ulp.dtsi"
/ {
@ -20,6 +21,18 @@ chosen {
stdout-path = &lpuart5;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
button-power-on {
label = "PowerOn";
gpios = <&gpiof 31 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
@ -42,8 +55,8 @@ m33_reserved: noncacheable-section@a8600000 {
no-map;
};
rsc_table: rsc-table@1fff8000 {
reg = <0 0x1fff8000 0 0x1000>;
rsc_table: rsc-table@20000000 {
reg = <0 0x20000000 0 0x1000>;
no-map;
};
@ -154,6 +167,24 @@ &lpuart5 {
status = "okay";
};
&lpuart6 {
/* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart6>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&lpuart7 {
/* FT4232 PortD: need to connect J25/J26 2-3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart7>;
status = "okay";
};
&lpi2c7 {
#address-cells = <1>;
#size-cells = <0>;
@ -292,15 +323,15 @@ &mu {
&iomuxc1 {
pinctrl_enet: enetgrp {
fsl,pins = <
MX8ULP_PAD_PTE15__ENET0_MDC 0x43
MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
MX8ULP_PAD_PTE17__ENET0_RXER 0x43
MX8ULP_PAD_PTE15__ENET0_MDC 0x7
MX8ULP_PAD_PTE14__ENET0_MDIO 0x7
MX8ULP_PAD_PTE17__ENET0_RXER 0x7
MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
MX8ULP_PAD_PTE16__ENET0_TXEN 0x7
MX8ULP_PAD_PTE23__ENET0_TXD0 0x7
MX8ULP_PAD_PTE22__ENET0_TXD1 0x7
MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
@ -323,6 +354,12 @@ MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX8ULP_PAD_PTF31__PTF31 0x3
>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
@ -330,6 +367,22 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>;
};
pinctrl_lpuart6: lpuart6grp {
fsl,pins = <
MX8ULP_PAD_PTE10__LPUART6_TX 0x3
MX8ULP_PAD_PTE11__LPUART6_RX 0x3
MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x3
MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
MX8ULP_PAD_PTF22__LPUART7_TX 0x3
MX8ULP_PAD_PTF23__LPUART7_RX 0x3
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20

70
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8ulp-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
@ -153,17 +154,17 @@ sosc: clock-sosc {
#clock-cells = <0>;
};
sram@2201f000 {
sram@22010000 {
compatible = "mmio-sram";
reg = <0x0 0x2201f000 0x0 0x1000>;
reg = <0x0 0x22010000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x2201f000 0x1000>;
ranges = <0 0x0 0x22010000 0x10000>;
scmi_buf: scmi-sram-section@0 {
scmi_buf: scmi-sram-section@f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x400>;
reg = <0xf000 0x400>;
};
};
@ -360,6 +361,22 @@ tpm5: tpm@29340000 {
status = "disabled";
};
i3c2: i3c@29360000 {
compatible = "silvaco,i3c-master-v1";
reg = <0x29360000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&pcc3 IMX8ULP_CLK_I3C2>,
<&pcc3 IMX8ULP_CLK_I3C2>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "pclk", "fast_clk", "slow_clk";
assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
assigned-clock-rates = <24000000>;
status = "disabled";
};
lpi2c4: i2c@29370000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29370000 0x10000>;
@ -370,6 +387,8 @@ lpi2c4: i2c@29370000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 46 0 0>, <&edma1 45 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -383,6 +402,8 @@ lpi2c5: i2c@29380000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 48 0 0>, <&edma1 47 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -392,6 +413,11 @@ lpuart4: serial@29390000 {
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
clock-names = "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 55 0 FSL_EDMA_RX>, <&edma1 56 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -401,6 +427,11 @@ lpuart5: serial@293a0000 {
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
clock-names = "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
assigned-clock-rates = <24000000>;
dmas = <&edma1 57 0 FSL_EDMA_RX>, <&edma1 58 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -416,6 +447,8 @@ lpspi4: spi@293b0000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 64 0 0>, <&edma1 63 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -431,6 +464,8 @@ lpspi5: spi@293c0000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 66 0 0>, <&edma1 65 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -474,6 +509,8 @@ lpi2c6: i2c@29840000 {
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 50 0 0>, <&edma1 49 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -487,6 +524,8 @@ lpi2c7: i2c@29850000 {
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 52 0 0>, <&edma1 51 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -496,6 +535,11 @@ lpuart6: serial@29860000 {
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
clock-names = "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 59 0 FSL_EDMA_RX>, <&edma1 60 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -505,6 +549,11 @@ lpuart7: serial@29870000 {
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
clock-names = "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
dmas = <&edma1 61 0 FSL_EDMA_RX>, <&edma1 62 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -516,7 +565,7 @@ sai4: sai@29880000 {
<&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 67 0 1>, <&edma1 68 0 0>;
dmas = <&edma1 67 0 FSL_EDMA_RX>, <&edma1 68 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x03 0x03>;
@ -531,7 +580,7 @@ sai5: sai@29890000 {
<&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 69 0 1>, <&edma1 70 0 0>;
dmas = <&edma1 69 0 FSL_EDMA_RX>, <&edma1 70 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
@ -814,7 +863,7 @@ sai6: sai@2da90000 {
<&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma2 71 0 1>, <&edma2 72 0 0>;
dmas = <&edma2 71 0 FSL_EDMA_RX>, <&edma2 72 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
@ -829,7 +878,7 @@ sai7: sai@2daa0000 {
<&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma2 73 0 1>, <&edma2 74 0 0>;
dmas = <&edma2 73 0 FSL_EDMA_RX>, <&edma2 74 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
@ -855,7 +904,8 @@ spdif: spdif@2dab0000 {
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
dmas = <&edma2 75 0 5>, <&edma2 76 0 4>;
dmas = <&edma2 75 0 (FSL_EDMA_RX | FSL_EDMA_MULTI_FIFO)>,
<&edma2 76 0 FSL_EDMA_MULTI_FIFO>;
dma-names = "rx", "tx";
status = "disabled";
};

48
arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx91-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
flexcan_phy: can-phy {
compatible = "nxp,tja1057";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_phy>;
silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
};
&flexcan1 {
phys = <&flexcan_phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>, <&can_fun>;
status = "okay";
};
&iomuxc {
pinctrl_flexcan_phy: flexcanphygrp {
fsl,pins = <
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX91_PAD_PDM_CLK__CAN1_TX 0x139e
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
};
/* micfil uses PDM port A pins, conflicts with can1 */
&micfil {
status = "disabled";
};

160
arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts
View File

@ -30,6 +30,79 @@ chosen {
stdout-path = &lpuart1;
};
wm8524: audio-codec {
compatible = "wlf,wm8524";
#sound-dai-cells = <0>;
wlf,mute-gpios = <&pcal6524 2 GPIO_ACTIVE_LOW>;
port {
codec_ep: endpoint {
remote-endpoint = <&sai1_ep1>;
};
};
};
dmic: dmic {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
num-channels = <4>;
port {
dmic_ep: endpoint {
remote-endpoint = <&micfil_ep>;
};
};
};
can_mux: mux-controller-0 {
compatible = "gpio-mux";
#mux-control-cells = <0>;
#mux-state-cells = <1>;
mux-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>;
};
sai1_mux: mux-controller-1 {
compatible = "gpio-mux";
#mux-control-cells = <0>;
#mux-state-cells = <1>;
mux-gpios = <&pcal6524 18 GPIO_ACTIVE_HIGH>;
};
sai1_en_mux: mux-controller-2 {
compatible = "gpio-mux";
#mux-control-cells = <0>;
#mux-state-cells = <1>;
mux-gpios = <&pcal6524 9 GPIO_ACTIVE_HIGH>;
};
pinctrl-gpiomux {
compatible = "pinctrl-multiplexer";
can_fun: can-grp {
mux-states = <&can_mux 1>;
};
m2_fun: m2-grp {
mux-states = <&sai1_mux 1>;
};
pdm_fun: pdm-grp {
mux-states = <&can_mux 0>;
};
sai1_disable: sai1-disable-grp {
mux-states = <&sai1_en_mux 1>;
};
sai1_enable: sai1-enable-grp {
mux-states = <&sai1_en_mux 0>;
};
sai1_fun: sai1-grp {
mux-states = <&sai1_mux 0>;
};
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
@ -61,6 +134,22 @@ linux,cma {
linux,cma-default;
};
};
sound-micfil {
compatible = "audio-graph-card2";
label = "micfil-audio";
links = <&micfil_port>;
};
sound-wm8524 {
compatible = "audio-graph-card2";
label = "wm8524-audio";
links = <&sai1_port1>;
widgets = "Line", "Line Out Jack";
routing =
"Line Out Jack", "LINEVOUTL",
"Line Out Jack", "LINEVOUTR";
};
};
&adc1 {
@ -131,12 +220,29 @@ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX91_PAD_PDM_CLK__PDM_CLK 0x31e
MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e
MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
@ -384,6 +490,60 @@ &lpuart1 {
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>;
assigned-clocks = <&clk IMX93_CLK_PDM>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <49152000>;
status = "okay";
micfil_port: port {
capture-only;
micfil_ep: endpoint {
remote-endpoint = <&dmic_ep>;
};
};
};
&sai1 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>, <&sai1_fun>, <&sai1_enable>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
fsl,sai-mclk-direction-output;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
sai1_port1: port@1 {
reg = <1>;
playback-only;
sai1_ep1: endpoint {
dai-format = "i2s";
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
bitclock-master;
frame-master;
mclk-fs = <256>;
system-clock-direction-out;
remote-endpoint = <&codec_ep>;
};
};
};
};
&usbotg1 {
adp-disable;
disable-over-current;

4
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts
View File

@ -518,6 +518,8 @@ &usbotg1 {
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
@ -532,6 +534,8 @@ &usbotg2 {
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
hub_2_0: hub@1 {

937
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts Normal file
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@ -0,0 +1,937 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel
* Author: Alexander Stein
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx91-tqma9131.dtsi"
/{
model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa93xxCA starter kit";
compatible = "tq,imx91-tqma9131-mba93xxca",
"tq,imx91-tqma9131", "fsl,imx91";
chassis-type = "embedded";
chosen {
stdout-path = &lpuart1;
};
aliases {
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial5 = &lpuart6;
serial7 = &lpuart8;
};
clk_dp: clk-dp {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
status = "disabled";
};
fan0: pwm-fan {
compatible = "pwm-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwmfan>;
fan-supply = <&reg_pwm_fan>;
#cooling-cells = <2>;
/* typical 25 kHz -> 40.000 nsec */
pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>;
cooling-levels = <0 32 64 128 196 240>;
pulses-per-revolution = <2>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
status = "disabled";
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
switch-a {
label = "switcha";
linux,code = <BTN_0>;
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
switch-b {
label = "switchb";
linux,code = <BTN_1>;
gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led-2 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "V_5V0_MB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "V_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_mpcie_1v5: regulator-mpcie-1v5 {
compatible = "regulator-fixed";
regulator-name = "V_1V5_MPCIE";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_mpcie_3v3: regulator-mpcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MPCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_pwm_fan: regulator-pwm-fan {
compatible = "regulator-fixed";
regulator-name = "FAN_PWR";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_12v0>;
};
thermal-zones {
cpu-thermal {
trips {
cpu_active0: trip-active0 {
temperature = <40000>;
hysteresis = <5000>;
type = "active";
};
cpu_active1: trip-active1 {
temperature = <48000>;
hysteresis = <3000>;
type = "active";
};
cpu_active2: trip-active2 {
temperature = <60000>;
hysteresis = <10000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&cpu_active0>;
cooling-device = <&fan0 1 1>;
};
map2 {
trip = <&cpu_active1>;
cooling-device = <&fan0 2 2>;
};
map3 {
trip = <&cpu_active2>;
cooling-device = <&fan0 3 3>;
};
};
};
};
};
&adc1 {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy_eqos: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_fec>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy_fec: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&gpio1 {
gpio-line-names =
/* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",
/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>;
gpio-line-names =
/* 00 */ "SPI6_PCS0#", "", "", "",
/* 04 */ "", "", "", "SPI_CS#",
/* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",
/* 12 */ "", "", "", "",
/* 16 */ "X1_11", "X1_21", "X1_17", "X1_13",
/* 20 */ "X1_15", "X1_9", "", "",
/* 24 */ "", "", "X1_7", "",
/* 28 */ "", "", "", "";
};
&gpio3 {
gpio-line-names =
/* 00 */ "SD2_CD#", "", "", "",
/* 04 */ "", "", "", "SD2_RST#",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
/* 28 */ "", "", "", "";
};
&gpio4 {
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "DP_INT", "", "";
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
};
ptn5110: usb-typec@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
connector {
compatible = "usb-c-connector";
label = "X17";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
typec-power-opmode = "default";
pd-disable;
self-powered;
port {
typec_con_hs: endpoint {
remote-endpoint = <&typec_hs>;
};
};
};
};
eeprom2: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
vcc-supply = <&reg_3v3>;
};
expander0: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pexp_irq>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#",
"MPCIE_1V5_EN", "MPCIE_3V3_EN",
"MPCIE_PERST#", "MPCIE_WDISABLE#",
"BUTTON_A#", "BUTTON_B#";
mpcie-wake-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
input;
line-name = "MPCIE_WAKE#";
};
/*
* Controls the mPCIE slot reset which is low active as
* reset signal. The output-low states, the signal is
* inactive, e.g. not in reset
*/
mpcie_rst_hog: mpcie-rst-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "MPCIE_PERST#";
};
/*
* Controls the mPCIE slot WDISABLE pin which is low active
* as disable signal. The output-low states, the signal is
* inactive, e.g. not disabled
*/
mpcie_wdisable_hog: mpcie-wdisable-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "MPCIE_WDISABLE#";
};
};
expander1: gpio@71 {
compatible = "nxp,pca9538";
reg = <0x71>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
"USB_RESET#", "",
"WLAN_PD#", "WLAN_W_DISABLE#",
"WLAN_PERST#", "12V_EN";
/*
* Controls the WiFi card's low-active power down pin.
* The output-low states, the signal is inactive,
* resulting in high signal at power-down pin
*/
wlan-pd-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_PD#";
};
/*
* Controls the WiFi card's low-active disable pin.
* The output-low states, the signal is inactive,
* resulting in high signal at power-down pin
*/
wlan-wdisable-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_W_DISABLE#";
};
/*
* Controls the WiFi card's reset pin.
* The output-low states, the signal is inactive,
* resulting in high signal at power-down pin
*/
wlan-perst-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_PERST#";
};
};
expander2: gpio@72 {
compatible = "nxp,pca9538";
reg = <0x72>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
"LCD_BLT_EN", "DP_EN",
"MIPI_CSI_EN", "MIPI_CSI_RST#",
"USER_LED1", "USER_LED2";
};
};
&lpi2c5 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c5>;
pinctrl-1 = <&pinctrl_lpi2c5>;
status = "okay";
dp_bridge: dp-bridge@f {
compatible = "toshiba,tc9595", "toshiba,tc358767";
reg = <0x0f>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tc9595>;
clock-names = "ref";
clocks = <&clk_dp>;
reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
toshiba,hpd-pin = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_dsi_in: endpoint {
data-lanes = <1 2 3 4>;
};
};
};
};
};
&lpspi6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>;
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&lpuart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "okay";
};
&lpuart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
status = "okay";
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcf85063>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
};
&se97_som {
/* TEMP_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_temp_sensor_som>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
/* on LVDS connector, not usable */
&tpm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm5>;
};
&tpm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm6>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
typec_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usbotg2 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb424,2517";
reg = <1>;
reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3v3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;
no-mmc;
disable-wp;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000
/* HYS | PD | FSEL_0 | DSE no drive */
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400
/* PD | FSEL_2 | DSE X4 */
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
/* PD | FSEL_3 | DSE X3 */
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
>;
};
pinctrl_eqos_phy: eqosphygrp {
fsl,pins = <
/* HYS | FSEL_0 | DSE no drive */
MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000
/* HYS | PD | FSEL_0 | DSE no drive */
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400
/* PD | FSEL_2 | DSE X4 */
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e
/* PD | FSEL_3 | DSE X3 */
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e
>;
};
pinctrl_fec_phy: fecphygrp {
fsl,pins = <
/* HYS | FSEL_0 | DSE no drive */
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
/* HYS | PU | FSEL_0 | DSE no drive */
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200
/* PU | FSEL_3 | DSE X4 */
MX91_PAD_PDM_CLK__CAN1_TX 0x039e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
/* HYS | PU | FSEL_0 | DSE no drive */
MX91_PAD_GPIO_IO27__CAN2_RX 0x1200
/* PU | FSEL_3 | DSE X4 */
MX91_PAD_GPIO_IO25__CAN2_TX 0x039e
>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <
/* HYS | PD | FSEL_2 | DSE X4 */
MX91_PAD_GPIO_IO16__GPIO2_IO16 0x151e
MX91_PAD_GPIO_IO17__GPIO2_IO17 0x151e
MX91_PAD_GPIO_IO18__GPIO2_IO18 0x151e
MX91_PAD_GPIO_IO19__GPIO2_IO19 0x151e
MX91_PAD_GPIO_IO20__GPIO2_IO20 0x151e
MX91_PAD_GPIO_IO21__GPIO2_IO21 0x151e
MX91_PAD_GPIO_IO26__GPIO2_IO26 0x151e
>;
};
pinctrl_jtag: jtaggrp {
fsl,pins = <
MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e
MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200
MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e
MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
/* SION | HYS | OD | FSEL_3 | DSE X4 */
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
/* SION | HYS | OD | FSEL_3 | DSE X4 */
MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e
MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e
>;
};
pinctrl_lpspi6: lpspi6grp {
fsl,pins = <
/* HYS | PD | FSEL_0 | DSE no drive */
MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x1400
/* PD | FSEL_2 | DSE X4 */
MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e
MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x051e
>;
};
pinctrl_lpspi6_cs: lpspi6csgrp {
fsl,pins = <
/* FSEL_2 | DSE X4 */
MX91_PAD_GPIO_IO00__GPIO2_IO0 0x011e
MX91_PAD_GPIO_IO07__GPIO2_IO7 0x011e
>;
};
pinctrl_mipi_csi: mipicsigrp {
fsl,pins = <
MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */
MX91_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */
MX91_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */
>;
};
pinctrl_pcf85063: pcf85063grp {
fsl,pins = <
MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000
>;
};
pinctrl_pexp_irq: pexpirqgrp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000
>;
};
pinctrl_pwmfan: pwmfangrp {
fsl,pins = <
/* HYS | PU | FSEL_0 | no DSE */
MX91_PAD_GPIO_IO09__GPIO2_IO9 0x1200
>;
};
pinctrl_tc9595: tc9595-grp {
fsl,pins = <
/* HYS | PD | FSEL_0 | no DSE */
MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1400
>;
};
pinctrl_temp_sensor_som: tempsensorsomgrp {
fsl,pins = <
/* HYS | FSEL_0 | no DSE */
MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000
>;
};
pinctrl_tpm5: tpm5grp {
fsl,pins = <
MX91_PAD_GPIO_IO06__TPM5_CH0 0x57e
>;
};
pinctrl_tpm6: tpm6grp {
fsl,pins = <
MX91_PAD_GPIO_IO08__TPM6_CH0 0x57e
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_I2C2_SCL__GPIO1_IO2 0x1000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_UART1_RXD__LPUART1_RX 0x1000
/* FSEL_2 | DSE X4 */
MX91_PAD_UART1_TXD__LPUART1_TX 0x011e
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_UART2_RXD__LPUART2_RX 0x1000
/* FSEL_2 | DSE X4 */
MX91_PAD_UART2_TXD__LPUART2_TX 0x011e
/* FSEL_2 | DSE X4 */
MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_GPIO_IO15__LPUART3_RX 0x1000
/* FSEL_2 | DSE X4 */
MX91_PAD_GPIO_IO14__LPUART3_TX 0x011e
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_GPIO_IO05__LPUART6_RX 0x1000
/* FSEL_2 | DSE X4 */
MX91_PAD_GPIO_IO04__LPUART6_TX 0x011e
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_GPIO_IO13__LPUART8_RX 0x1000
/* FSEL_2 | DSE X4 */
MX91_PAD_GPIO_IO12__LPUART8_TX 0x011e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
/* HYS | FSEL_0 | No DSE */
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000
>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_hs: usdhc2hsgrp {
fsl,pins = <
/* PD | FSEL_3 | DSE X5 */
MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be
/* HYS | PU | FSEL_3 | DSE X4 */
MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
/* HYS | PU | FSEL_3 | DSE X3 */
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
/* FSEL_2 | DSE X3 */
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
fsl,pins = <
/* PD | FSEL_3 | DSE X6 */
MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe
/* HYS | PU | FSEL_3 | DSE X4 */
MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
/* FSEL_2 | DSE X3 */
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
>;
};
};

4
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
View File

@ -33,9 +33,9 @@ linux,cma {
};
/* EdgeLock secure enclave */
ele_reserved: ele-reserved@a4120000 {
ele_reserved: ele-reserved@94120000 {
compatible = "shared-dma-pool";
reg = <0 0xa4120000 0 0x100000>;
reg = <0 0x94120000 0 0x100000>;
no-map;
};
};

14
arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
View File

@ -97,6 +97,17 @@ reg_rgb_sel: regulator-rgb-enable {
enable-active-high;
};
reg_phy1_supply: regulator-phy1 {
compatible = "regulator-fixed";
regulator-name = "SUPPLY_PHY1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -139,9 +150,6 @@ mdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;

81
arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/imx93-clock.h>
&{/} {
panel-lvds {
compatible = "boe,ev121wxm-n10-1850";
backlight = <&backlight_lvds>;
power-supply = <&buck4>;
panel-timing {
/*
* Set clock frequency to 71142858Hz to accommodate
* IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate
* table.
*/
clock-frequency = <71142858>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
vfront-porch = <3>;
vback-porch = <14>;
vsync-len = <6>;
};
port {
panel_lvds_in: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
};
&backlight_lvds {
status = "okay";
};
&lcdif {
status = "okay";
};
&lvds_bridge {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
ldb_lvds_ch0: endpoint {
remote-endpoint = <&panel_lvds_in>;
};
};
};
};
&media_blk_ctrl {
assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>,
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
<&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_VIDEO_PLL>;
/*
* Set IMX93_CLK_MEDIA_DISP_PIX rate to 71142858Hz to accommodate
* IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate table.
*/
assigned-clock-rates = <400000000>, <133333333>, <71142858>, <498000000>;
status = "okay";
};

4
arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi
View File

@ -15,9 +15,9 @@ aliases {
rtc1 = &bbnsm_rtc;
};
memory@40000000 {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
reg = <0x0 0x80000000 0 0x40000000>;
};
chosen {

21
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
View File

@ -67,6 +67,23 @@ backlight_lvds: backlight {
status = "disabled";
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
power-supply = <&reg_3v3>;
enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
backlight = <&backlight_lvds>;
status = "disabled";
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
fan0: pwm-fan {
compatible = "pwm-fan";
pinctrl-names = "default";
@ -571,6 +588,10 @@ &lpuart8 {
status = "okay";
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel_in_lvds0>;
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";

38
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2023-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include <dt-bindings/clock/imx93-clock.h>
/dts-v1/;
/plugin/;
&backlight_lvds {
status = "okay";
};
&display {
compatible = "tianma,tm070jvhg33";
status = "okay";
};
&lcdif {
assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-rates = <477400000>;
status = "okay";
};
&lvds_bridge {
status = "okay";
};
&media_blk_ctrl {
status = "okay";
};
&tpm5 {
status = "okay";
};

45
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts
View File

@ -58,6 +58,37 @@ aliases {
spi5 = &lpspi6;
};
backlight_lvds: backlight {
compatible = "pwm-backlight";
pwms = <&tpm5 0 5000000 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v0>;
enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_display>;
power-supply = <&reg_3v3>;
enable-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
backlight = <&backlight_lvds>;
status = "disabled";
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
@ -311,6 +342,10 @@ &lpuart8 {
status = "okay";
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel_in_lvds0>;
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";
@ -375,6 +410,16 @@ &usdhc3 {
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO05__GPIO2_IO05 0x011e>;
};
pinctrl_display: displaygrp {
fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO07__GPIO2_IO07 0x011e>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e>,

21
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -73,6 +73,23 @@ clk_dp: clk-dp {
clock-frequency = <26000000>;
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
power-supply = <&reg_3v3>;
enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
backlight = <&backlight_lvds>;
status = "disabled";
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@ -534,6 +551,10 @@ &lpuart8 {
status = "okay";
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel_in_lvds0>;
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";

14
arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts
View File

@ -103,6 +103,17 @@ reg_vref_1v8: regulator-adc-vref {
regulator-min-microvolt = <1800000>;
};
reg_phy1_supply: regulator-phy1 {
compatible = "regulator-fixed";
regulator-name = "SUPPLY_PHY1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VDD_SD2_3V3";
@ -180,9 +191,6 @@ mdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
leds {
#address-cells = <1>;

39
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -80,7 +80,7 @@ mu1: mailbox@44230000 {
};
tmu: tmu@44482000 {
compatible = "fsl,qoriq-tmu";
compatible = "fsl,imx93-tmu";
reg = <0x44482000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_TMC_GATE>;
@ -178,6 +178,7 @@ &lcdif {
port {
lcdif_to_ldb: endpoint@1 {
reg = <1>;
remote-endpoint = <&ldb_from_lcdif>;
};
lcdif_to_dsi: endpoint@2 {
@ -186,6 +187,42 @@ lcdif_to_dsi: endpoint@2 {
};
};
&media_blk_ctrl {
#address-cells = <1>;
#size-cells = <1>;
lvds_bridge: bridge@20 {
compatible = "fsl,imx93-ldb";
reg = <0x20 0x4>, <0x24 0x4>;
reg-names = "ldb", "lvds";
clocks = <&clk IMX93_CLK_LVDS_GATE>;
clock-names = "ldb";
assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ldb_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_ldb>;
};
};
port@1 {
reg = <1>;
ldb_lvds_ch0: endpoint {
};
};
};
};
};
&src {
mlmix: power-domain@44461800 {
compatible = "fsl,imx93-src-slice";

20
arch/arm64/boot/dts/freescale/imx94.dtsi
View File

@ -827,6 +827,8 @@ xspi1: spi@42b90000 {
#size-cells = <0>;
clocks = <&scmi_clk IMX94_CLK_XSPI1>;
clock-names = "per";
dmas = <&edma2 27 0 0>, <&edma2 28 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -843,6 +845,8 @@ xspi2: spi@42be0000 {
#size-cells = <0>;
clocks = <&scmi_clk IMX94_CLK_XSPI2>;
clock-names = "per";
dmas = <&edma4 42 0 0>, <&edma4 43 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -1374,8 +1378,9 @@ pcie0: pcie@4c300000 {
<0 0x4c360000 0 0x10000>,
<0 0x4c340000 0 0x4000>;
reg-names = "dbi", "config", "atu", "app";
ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
<0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
<0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
<0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -1410,6 +1415,17 @@ pcie0: pcie@4c300000 {
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
fsl,max-link-speed = <3>;
status = "disabled";
pcie0_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_ep: pcie-ep@4c300000 {

150
arch/arm64/boot/dts/freescale/imx943-evk.dts
View File

@ -133,6 +133,36 @@ reg_audio_pwr: regulator-wm8962-pwr {
enable-active-high;
};
remoteproc-cm70 {
compatible = "fsl,imx94-cm70";
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu11 0 1
&mu11 1 1
&mu11 3 1>;
memory-region = <&cm70_vdev0buffer>, <&cm70_vdev0vring0>, <&cm70_vdev0vring1>,
<&cm70_vdev1vring0>, <&cm70_vdev1vring1>, <&cm70_rsc_table>;
};
remoteproc-cm71 {
compatible = "fsl,imx94-cm71";
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu13 0 1
&mu13 1 1
&mu13 3 1>;
memory-region = <&cm71_vdev0buffer>, <&cm71_vdev0vring0>, <&cm71_vdev0vring1>,
<&cm71_vdev1vring0>, <&cm71_vdev1vring1>, <&cm71_rsc_table>;
};
remoteproc-cm33s {
compatible = "fsl,imx94-cm33s";
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu15 0 1
&mu15 1 1
&mu15 3 1>;
memory-region = <&cm33s_vdev0buffer>, <&cm33s_vdev0vring0>, <&cm33s_vdev0vring1>,
<&cm33s_vdev1vring0>, <&cm33s_vdev1vring1>, <&cm33s_rsc_table>;
};
reserved-memory {
ranges;
#address-cells = <2>;
@ -145,6 +175,99 @@ linux,cma {
size = <0 0x10000000>;
linux,cma-default;
};
cm33s_vdev0vring0: vdev0vring0@20800000 {
reg = <0 0x20800000 0 0x8000>;
no-map;
};
cm33s_vdev0vring1: vdev0vring1@20808000 {
reg = <0 0x20808000 0 0x8000>;
no-map;
};
cm33s_vdev1vring0: vdev1vring0@20810000 {
reg = <0 0x20810000 0 0x8000>;
no-map;
};
cm33s_vdev1vring1: vdev1vring1@20818000 {
reg = <0 0x20818000 0 0x8000>;
no-map;
};
cm33s_rsc_table: rsc-table@208a0000 {
reg = <0 0x208a0000 0 0x1000>;
no-map;
};
cm33s_vdev0buffer: vdev0buffer@20820000 {
compatible = "shared-dma-pool";
reg = <0 0x20820000 0 0x80000>;
no-map;
};
cm70_vdev0vring0: vdev0vring0@82000000 {
reg = <0 0x82000000 0 0x8000>;
no-map;
};
cm70_vdev0vring1: vdev0vring1@82008000 {
reg = <0 0x82008000 0 0x8000>;
no-map;
};
cm70_vdev1vring0: vdev1vring0@82010000 {
reg = <0 0x82010000 0 0x8000>;
no-map;
};
cm70_vdev1vring1: vdev1vring1@82018000 {
reg = <0 0x82018000 0 0x8000>;
no-map;
};
cm70_rsc_table: rsc-table@82220000 {
reg = <0 0x82220000 0 0x1000>;
no-map;
};
cm70_vdev0buffer: vdev0buffer@82020000 {
compatible = "shared-dma-pool";
reg = <0 0x82020000 0 0x100000>;
no-map;
};
cm71_vdev0vring0: vdev0vring0@84000000 {
reg = <0 0x84000000 0 0x8000>;
no-map;
};
cm71_vdev0vring1: vdev0vring1@84008000 {
reg = <0 0x84008000 0 0x8000>;
no-map;
};
cm71_vdev1vring0: vdev1vring0@84010000 {
reg = <0 0x84010000 0 0x8000>;
no-map;
};
cm71_vdev1vring1: vdev1vring1@84018000 {
reg = <0 0x84018000 0 0x8000>;
no-map;
};
cm71_rsc_table: rsc-table@84220000 {
reg = <0 0x84220000 0 0x1000>;
no-map;
};
cm71_vdev0buffer: vdev0buffer@84020000 {
compatible = "shared-dma-pool";
reg = <0 0x84020000 0 0x100000>;
no-map;
};
};
sound-bt-sco {
@ -592,6 +715,18 @@ &micfil {
status = "okay";
};
&mu11 {
status = "okay";
};
&mu13 {
status = "okay";
};
&mu15 {
status = "okay";
};
&netc_blk_ctrl {
assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>,
<&scmi_clk IMX94_CLK_MAC5>;
@ -1034,12 +1169,15 @@ &pcie0 {
<&pcie_ref_clk>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
"ref", "extref";
reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
vpcie3v3aux-supply = <&reg_m2_wlan>;
supports-clkreq;
status = "okay";
};
&pcie0_port0 {
reset-gpios = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
vpcie3v3aux-supply = <&reg_m2_wlan>;
};
&pcie0_ep {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
@ -1058,12 +1196,14 @@ &pcie1 {
<&pcie_ref_clk>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
"ref", "extref";
reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
vpcie3v3aux-supply = <&reg_slot_pwr>;
supports-clkreq;
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
vpcie3v3aux-supply = <&reg_slot_pwr>;
};
&pcie1_ep {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";

16
arch/arm64/boot/dts/freescale/imx943.dtsi
View File

@ -218,8 +218,9 @@ pcie1: pcie@4c380000 {
<0 0x4c3e0000 0 0x10000>,
<0 0x4c3c0000 0 0x4000>;
reg-names = "dbi", "config", "atu", "app";
ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
<0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>;
ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
<0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
<0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -254,6 +255,17 @@ pcie1: pcie@4c380000 {
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
fsl,max-link-speed = <3>;
status = "disabled";
pcie1_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie1_ep: pcie-ep@4c380000 {

4
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
View File

@ -555,8 +555,6 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_m2_pwr>;
vpcie3v3aux-supply = <&reg_m2_pwr>;
supports-clkreq;
status = "disabled";
};
@ -570,6 +568,8 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_m2_pwr>;
vpcie3v3aux-supply = <&reg_m2_pwr>;
};
&sai1 {

54
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -76,6 +76,42 @@ linux_cma: linux,cma {
linux,cma-default;
reusable;
};
m7_reserved: memory@80000000 {
no-map;
reg = <0 0x80000000 0 0x1000000>;
};
vdev0vring0: vdev0vring0@88000000 {
reg = <0 0x88000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@88008000 {
reg = <0 0x88008000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@88010000 {
reg = <0 0x88010000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@88018000 {
reg = <0 0x88018000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@88220000 {
reg = <0 0x88220000 0 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@88020000 {
compatible = "shared-dma-pool";
reg = <0 0x88020000 0 0x100000>;
no-map;
};
};
flexcan1_phy: can-phy0 {
@ -185,6 +221,16 @@ reg_usb_vbus: regulator-vbus {
enable-active-high;
};
remoteproc-cm7 {
compatible = "fsl,imx95-cm7";
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu7 0 1
&mu7 1 1
&mu7 3 1>;
memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
@ -542,8 +588,6 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
supports-clkreq;
status = "okay";
};
@ -557,6 +601,8 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_pcie0>;
vpcie3v3aux-supply = <&reg_pcie0>;
};
&pcie1 {
@ -564,8 +610,6 @@ &pcie1 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_slot_pwr>;
vpcie3v3aux-supply = <&reg_slot_pwr>;
status = "okay";
};
@ -578,6 +622,8 @@ &pcie1_ep {
&pcie1_port0 {
reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
vpcie3v3-supply = <&reg_slot_pwr>;
vpcie3v3aux-supply = <&reg_slot_pwr>;
};
&sai1 {

1
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
View File

@ -24,6 +24,7 @@ aliases {
serial1 = &lpuart1;
serial2 = &lpuart6;
serial3 = &lpuart3;
serial4 = &lpuart5;
};
chosen {

958
arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts Normal file
View File

@ -0,0 +1,958 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
* Author: Markus Niebel
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx95-tqma9596la.dtsi"
/ {
model = "TQ-Systems i.MX95 TQMa95xxLA on MBa95xxCA";
compatible = "tq,imx95-tqma9596la-mba95xxca", "tq,imx95-tqma9596la", "fsl,imx95";
chassis-type = "embedded";
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
ethernet2 = &enetc_port2;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &scmi_bbm;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
spi0 = &flexspi1;
};
chosen {
stdout-path = &lpuart1;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&tpm5 2 100000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_12v0>;
status = "disabled";
};
clk_eth: clk-eth {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <156250000>;
};
/*
* TODO: gate is disabled for now and GPIO are hogged
* ENETC driver switches the clock far too late for ENETC2 + SFP
*/
clk_eth_gate: clk-eth-gate {
compatible = "gpio-gate-clock";
enable-gpios = <&expander2 0 GPIO_ACTIVE_HIGH>;
clocks = <&clk_eth>;
#clock-cells = <0>;
status = "disabled";
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
button-b {
label = "BUTTON_B#";
linux,code = <BTN_1>;
gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&expander2 13 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led-2 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&expander2 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
<&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
};
reg_v1v8_mb: regulator-v1v8-mb {
compatible = "regulator-fixed";
regulator-name = "V_1V8_MB";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_v3v3_mb: regulator-v3v3-mb {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_3v3a_10g: regulator-3v3a-10g {
compatible = "regulator-fixed";
regulator-name = "3V3A_10G";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander2 15 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
enable-active-high;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "12V0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pwm_fan: regulator-pwm-fan {
compatible = "regulator-fixed";
regulator-name = "FAN_PWR";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander3 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_12v0>;
/*
* emc2305 fan driver lacks support for fan-supply, so
* alway enable it for now.
* Remove this line once support is added
*/
regulator-always-on;
};
reg_lvds: regulator-lvds {
compatible = "regulator-fixed";
regulator-name = "LCD_PWR_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander2 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* USB NC limitations, RM 162.1.2 VBUS limitations */
reg_vbus_usb3: regulator-vbus-usb3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "USB3_VBUS";
gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x28000000>;
alloc-ranges = <0 0x80000000 0 0x80000000>;
linux,cma-default;
};
};
sfp_xfi: sfp-xfi {
compatible = "sff,sfp";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sfp>;
i2c-bus = <&lpi2c7>;
maximum-power-milliwatt = <2000>;
mod-def0-gpios = <&expander1 3 GPIO_ACTIVE_LOW>;
tx-fault-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
los-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
audio-codec = <&tlv320aic3x04>;
audio-cpu = <&sai3>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
};
wifi-connector {
compatible = "pcie-m2-e-connector";
vpcie3v3-supply = <&reg_v3v3_mb>;
vpcie1v8-supply = <&reg_v1v8_mb>;
i2c-parent = <&lpi2c2>;
w-disable1-gpios = <&expander2 9 GPIO_ACTIVE_LOW>;
w-disable2-gpios = <&expander2 10 GPIO_ACTIVE_LOW>;
/* UART_WAKE is connected to SM */
/* SDIO_WAKE is connected to SM */
sdio-reset-gpios = <&expander3 2 GPIO_ACTIVE_LOW>;
};
};
&adc1 {
status = "okay";
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&enetc_port1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc1>;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
status = "okay";
};
/* No support for XFI yet */
&enetc_port2 {
sfp = <&sfp_xfi>;
phy-mode = "10gbase-r";
clocks = <&clk_eth>;
managed = "in-band-status";
status = "disabled";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&lpi2c2 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
reset-gpios = <&expander1 14 GPIO_ACTIVE_LOW>;
iov-supply = <&reg_v3v3_mb>;
ldoin-supply = <&reg_v3v3_mb>;
};
sensor_mb: temperature-sensor@1e {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1e>;
};
fan_controller: fan-controller@2f {
compatible = "microchip,emc2301", "microchip,emc2305";
reg = <0x2f>;
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <3>;
status = "okay";
fan: fan@0 {
reg = <0x0>;
pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED 1>;
#cooling-cells = <2>;
fan-supply = <&reg_pwm_fan>;
};
};
ptn5110: usb-typec@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio2>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
typec_con: connector {
compatible = "usb-c-connector";
label = "X9";
power-role = "source";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
self-powered;
port {
typec_con_hs: endpoint {
remote-endpoint = <&typec_hs>;
};
};
};
};
eeprom_mb: eeprom@56 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x56>;
pagesize = <16>;
vcc-supply = <&reg_v3v3_mb>;
};
pcieclk: clock-generator@68 {
compatible = "renesas,9fgv0441";
reg = <0x68>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
/* D39 IN/OUT 3V3 */
expander1: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
vcc-supply = <&reg_v3v3_mb>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_expander1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
gpio-line-names =
/* 00 */ "BUTTON_B#", "CAM0_SYNC_3V3",
/* 02 */ "CAM1_SYNC_3V3", "SFP_MOD_ABS",
/* 04 */ "DIG_IN1", "DIG_IN2",
/* 06 */ "DIG_IN3", "DIG_IN4",
/* 08 */ "DIG_OUT_1_2_STATE", "DIG_OUT_3_4_STATE",
/* 10 */ "DIG_OUT_1_EN", "DIG_OUT_2_EN",
/* 12 */ "DIG_OUT_3_EN", "DIG_OUT_4_EN",
/* 14 */ "AUDIO_RST#", "12V_EN";
};
/* D40 OUT 3V3 */
expander2: gpio@75 {
compatible = "ti,tca9539";
reg = <0x75>;
vcc-supply = <&reg_v3v3_mb>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/* 00 */ "ETH10G_REFCLK_EN", "ETH10G_REFCLK_RST#",
/* 02 */ "SFP_TX_DIS", "USB3_RESET#",
/* 04 */ "USB2_RESET#", "LCD_RESET#",
/* 06 */ "LCD_BLT_EN", "LCD_PWR_EN",
/* 08 */ "M2_KEYE_PERST#", "M2_KEYE_WDISABLE1#",
/* 10 */ "M2_KEYE_WDISABLE2#", "M2_KEYB_PERST#",
/* 12 */ "M2_KEYB_WDISABLE1#", "USER_LED1",
/* 14 */ "USER_LED2", "3V3A_10G_EN";
eth10g-refclk-en-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "ETH10G_REFCLK_EN";
};
eth10g-refclk-rst-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
output-low;
line-name = "ETH10G_REFCLK_RST#";
};
m2-keyb-wdisable1-hog {
gpio-hog;
gpios = <12 GPIO_ACTIVE_LOW>;
output-low;
line-name = "M2_KEYB_WDISABLE1#";
};
};
/* D41 OUT 1V8 */
expander3: gpio@76 {
compatible = "ti,tca9539";
reg = <0x76>;
vcc-supply = <&reg_v1v8_mb>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/* 00 */ "ENET1_RESET#", "ENET2_RESET#",
/* 02 */ "M2_KEYE_SDIO_RST#", "M2_KEYE_DEV_WLAN_WAKE#",
/* 04 */ "M2_KEYE_DEV_BT_WAKE", "M2_KEYB_W_DISABLE2#",
/* 06 */ "M2_KEYB_RST#", "M2_KEYB_FULL_CARD_PWR_OFF#",
/* 08 */ "M2_KEYB_DPR", "CAM0_PWR#",
/* 10 */ "CAM1_PWR#", "CAM0_RST#",
/* 12 */ "CAM1_RST#", "CAM0_TRIGGER",
/* 14 */ "CAM1_TRIGGER", "FAN_PWR_EN";
/* vendor defined pin 42 */
m2-keye-dev_wlan-wake-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
input;
line-name = "M2_KEYE_DEV_WLAN_WAKE#";
};
/* vendor defined pin 40 */
m2-keye-dev_bt-wake-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
input;
line-name = "M2_KEYE_DEV_BT_WAKE#";
};
m2-keyb-wdisable2-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "M2_KEYB_WDISABLE2#";
};
m2-keyb-rst-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "M2_KEYB_RST#";
};
m2-keyb-full-card-pwr-off-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_LOW>;
output-low;
line-name = "M2_KEYB_FULL_CARD_PWR_OFF#";
};
};
};
/* X4 + SFP */
&lpi2c7 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c7>;
pinctrl-1 = <&pinctrl_lpi2c7_recovery>;
scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* TODO: 0x19: retimer */
/* 0x50 / 0x51: SFP EEPROM */
};
/* X4 */
&lpspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi4>;
cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>;
/* max 30 MHz as per datasheet, without SCK loopback via pad (LPSPI_CFGR1[SAMPLE]) */
status = "okay";
};
&lpuart1 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&lpuart2 {
/* SM */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "reserved";
};
&lpuart5 {
/* X16 M.2 KEY E */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart5>;
status = "okay";
};
&lpuart7 {
/* X5 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart7>;
status = "okay";
};
&lpuart8 {
/* X15 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart8>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&netc_blk_ctrl {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emdio>;
status = "okay";
/* IRQ pin is AON GPIO, not usable */
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&expander3 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ethphy1>;
reset-gpios = <&expander3 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio4>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
&netc_timer {
status = "okay";
};
&netcmix_blk_ctrl {
status = "okay";
};
/* X16 M2 / E-Key mPCIe */
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>,
<&pcieclk 1>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref";
reset-gpios = <&expander2 8 GPIO_ACTIVE_LOW>;
/* Not supported on REV.0100 */
/* supports-clkreq; */
status = "okay";
};
/* X17 M2 / B-Key PCIe */
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>,
<&pcieclk 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref";
reset-gpios = <&expander2 11 GPIO_ACTIVE_LOW>;
/* Not supported on REV.0100 */
/* supports-clkreq; */
status = "okay";
};
&reg_sdvmmc {
status = "okay";
};
&sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&scmi_bbm {
linux,code = <KEY_POWER>;
};
&thermal_zones {
a55-thermal {
trips {
cpu_active0: trip-active0 {
temperature = <40000>;
hysteresis = <5000>;
type = "active";
};
cpu_active1: trip-active1 {
temperature = <48000>;
hysteresis = <3000>;
type = "active";
};
cpu_active2: trip-active2 {
temperature = <60000>;
hysteresis = <10000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&cpu_active0>;
cooling-device = <&fan 0 2>;
};
map2 {
trip = <&cpu_active1>;
cooling-device = <&fan 3 5>;
};
map3 {
trip = <&cpu_active2>;
cooling-device = <&fan 6 10>;
};
};
};
};
&tpm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm3>;
status = "okay";
};
&tpm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm5>;
};
&usb2 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
typec_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb451,8142";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_v3v3_mb>;
#address-cells = <1>;
#size-cells = <0>;
hub_2_1: hub@1 {
compatible = "usb424,2514";
reg = <1>;
reset-gpios = <&expander2 4 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_v3v3_mb>;
vdda-supply = <&reg_v3v3_mb>;
};
};
hub_3_0: hub@2 {
compatible = "usb451,8140";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_v3v3_mb>;
};
};
&usb3_phy {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
vbus-supply = <&reg_vbus_usb3>;
status = "okay";
};
/* X7 µSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_sdvmmc>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
disable-wp;
bus-width = <4>;
status = "okay";
};
&scmi_iomuxc {
pinctrl_enetc0: enetc0grp {
fsl,pins = <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x1100>,
<IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x1100>,
<IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x1100>,
<IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x1100>,
<IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x1100>,
<IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x1100>,
<IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x11e>,
<IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x11e>,
<IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x11e>,
<IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x11e>,
<IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x11e>,
<IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x11e>;
};
pinctrl_enetc1: enetc1grp {
fsl,pins = <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x1100>,
<IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x1100>,
<IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x1100>,
<IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x1100>,
<IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x1100>,
<IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x1100>,
<IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x11e>,
<IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x11e>,
<IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x11e>,
<IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x11e>,
<IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x11e>,
<IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x11e>;
};
pinctrl_ethphy1: ethphy1grp {
fsl,pins = <IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x1100>;
};
pinctrl_expander1: expander1grp {
fsl,pins = <IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x1100>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x1300>,
<IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x31e>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x31e>,
<IMX95_PAD_GPIO_IO27__CAN2_RX 0x1300>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x40001b1e>,
<IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x40001b1e>;
};
pinctrl_lpi2c7_recovery: lpi2c7recoverygrp {
fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x40001b1e>,
<IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x40001b1e>;
};
pinctrl_lpspi4: lpspi4grp {
fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x11e>,
<IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x111e>,
<IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x11e>,
<IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x11e>,
<IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x11e>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>,
<IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x1300>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>,
<IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x1300>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e>,
<IMX95_PAD_GPIO_IO01__LPUART5_RX 0x1300>,
<IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x1300>,
<IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>,
<IMX95_PAD_GPIO_IO09__LPUART7_RX 0x1300>,
<IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x1300>,
<IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>;
};
pinctrl_lpuart8: lpuart8grp {
fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>,
<IMX95_PAD_GPIO_IO13__LPUART8_RX 0x1300>,
<IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>;
};
pinctrl_emdio: emdiogrp {
fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x51e>,
<IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x51e>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x111e>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x111e>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x51e>,
<IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x51e>,
<IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x1300>,
<IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x51e>,
<IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x51e>;
};
pinctrl_retimer: retimergrp {
fsl,pins = <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x1100>;
};
pinctrl_sfp: sfpgrp {
fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x1100>,
<IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x1100>;
};
pinctrl_tpm3: tpm3grp {
fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x51e>;
};
pinctrl_tpm5: tpm5grp {
fsl,pins = <IMX95_PAD_GPIO_IO18__TPM5_CH2 0x51e>;
};
pinctrl_typec: typecgrp {
fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x1100>;
};
pinctrl_usb3: usb3grp {
fsl,pins = <IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x31e>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x51e>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x31e>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x131e>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x131e>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x131e>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x131e>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x58e>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x38e>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>,
<IMX95_PAD_SD2_CLK__USDHC2_CLK 0x5fe>,
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x3fe>,
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>,
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>,
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>,
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>,
<IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>;
};
};

278
arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi Normal file
View File

@ -0,0 +1,278 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
* Author: Markus Niebel
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx95.dtsi"
/ {
memory@80000000 {
device_type = "memory";
/*
* DRAM base addr, size : 2048 MiB DRAM
* should be corrected by bootloader
*/
reg = <0 0x80000000 0 0x80000000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "V_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_sdvmmc: regulator-sdvmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdvmmc>;
regulator-name = "SD_PWR_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <12000>;
enable-active-high;
/* can be enabled by mainboard with SD-Card support */
status = "disabled";
};
};
&adc1 {
vref-supply = <&reg_1v8>;
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
vcc-supply = <&reg_1v8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
/* System Manager */
&gpio1 {
status = "reserved";
};
/* System Manager */
&lpi2c1 {
status = "reserved";
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
};
m24c64: eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
vcc-supply = <&reg_3v3>;
};
/* protectable identification memory (part of M24C64-D @54) */
eeprom@5c {
compatible = "atmel,24c64d-wl";
reg = <0x5c>;
pagesize = <32>;
vcc-supply = <&reg_3v3>;
};
imu@6b {
compatible = "st,ism330dhcx";
reg = <0x6b>;
vdd-supply = <&reg_3v3>;
vddio-supply = <&reg_3v3>;
};
};
&thermal_zones {
pf09-thermal {
polling-delay = <2000>;
polling-delay-passive = <250>;
thermal-sensors = <&scmi_sensor 2>;
trips {
pf09_alert: trip0 {
hysteresis = <2000>;
temperature = <140000>;
type = "passive";
};
pf09_crit: trip1 {
hysteresis = <2000>;
temperature = <155000>;
type = "critical";
};
};
};
pf53arm-thermal {
polling-delay = <2000>;
polling-delay-passive = <250>;
thermal-sensors = <&scmi_sensor 4>;
cooling-maps {
map0 {
trip = <&pf5301_alert>;
cooling-device =
<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
pf5301_alert: trip0 {
hysteresis = <2000>;
temperature = <140000>;
type = "passive";
};
pf5301_crit: trip1 {
hysteresis = <2000>;
temperature = <155000>;
type = "critical";
};
};
};
pf53soc-thermal {
polling-delay = <2000>;
polling-delay-passive = <250>;
thermal-sensors = <&scmi_sensor 3>;
trips {
pf5302_alert: trip0 {
hysteresis = <2000>;
temperature = <140000>;
type = "passive";
};
pf5302_crit: trip1 {
hysteresis = <2000>;
temperature = <155000>;
type = "critical";
};
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&wdog3 {
status = "okay";
};
&scmi_iomuxc {
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x19e>,
<IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x19e>,
<IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x19e>,
<IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x19e>,
<IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x19e>,
/* SION to allow clock loopback from pad */
<IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x4000019e>,
<IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x4000019e>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x4000191e>,
<IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x4000191e>;
};
pinctrl_sdvmmc: sdvmmcgrp {
fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>,
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>,
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>,
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>,
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>,
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>,
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>,
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>,
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>,
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>,
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>;
};
};

4
arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts
View File

@ -157,6 +157,7 @@ &enetc_port1 {
};
&enetc_port2 {
managed = "in-band-status";
phy-mode = "10gbase-r";
sfp = <&sfp0>;
status = "okay";
@ -346,9 +347,6 @@ &netc_emdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;

10
arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi
View File

@ -158,6 +158,8 @@ wm8904: audio-codec@1a {
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
/* DMIC is connected to IN1L */
wlf,in1l-as-dmicdat1;
};
};
@ -176,6 +178,10 @@ &mu7 {
status = "okay";
};
&netc_blk_ctrl {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>;
@ -213,6 +219,10 @@ &netc_timer {
status = "okay";
};
&netcmix_blk_ctrl {
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;

78
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -1867,37 +1867,6 @@ pmu@49252000 {
};
};
usb3: usb@4c010010 {
compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
reg = <0x0 0x4c010010 0x0 0x04>,
<0x0 0x4c1f0000 0x0 0x20>;
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_32K>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
status = "disabled";
usb3_dwc3: usb@4c100000 {
compatible = "snps,dwc3";
reg = <0x0 0x4c100000 0x0 0x10000>;
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_24M>,
<&scmi_clk IMX95_CLK_32K>;
clock-names = "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
iommus = <&smmu 0xe>;
};
};
hsio_blk_ctl: syscon@4c0100c0 {
compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
reg = <0x0 0x4c0100c0 0x0 0x1>;
@ -1906,6 +1875,37 @@ hsio_blk_ctl: syscon@4c0100c0 {
power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
};
bus@4c100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
ranges;
usb3: usb3_dwc3: usb@4c100000 {
compatible = "nxp,imx95-dwc3", "nxp,imx8mp-dwc3";
reg = <0x0 0x4c100000 0x0 0x10000>,
<0x0 0x4c010010 0x0 0x04>,
<0x0 0x4c1f0000 0x0 0x20>;
reg-names = "core", "blkctl", "glue";
clocks = <&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_HSIO>,
<&scmi_clk IMX95_CLK_24M>,
<&scmi_clk IMX95_CLK_32K>;
clock-names = "hsio", "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwc_usb3", "wakeup";
power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
phys = <&usb3_phy>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
iommus = <&smmu 0xe>;
status = "disabled";
};
};
usb3_phy: phy@4c1f0040 {
compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
reg = <0x0 0x4c1f0040 0x0 0x40>,
@ -1957,8 +1957,12 @@ pcie0: pcie@4c300000 {
bus-range = <0x00 0xff>;
num-lanes = <1>;
num-viewport = <8>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "dma", "intr", "aer", "pme";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
@ -2044,8 +2048,12 @@ pcie1: pcie@4c380000 {
bus-range = <0x00 0xff>;
num-lanes = <1>;
num-viewport = <8>;
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "dma", "intr", "aer", "pme";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,

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