From d911a33fa8e9fd4c691bc8429180fe1885bc3f2f Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 30 Apr 2026 10:53:33 +0800 Subject: [PATCH 001/131] arm64: dts: imx93: update the tmu compatible string The i.MX93 TMU node compatible need to be updated to apply the SoC specific configuration and TMU errata workaround. Reviewed-by: Frank Li Signed-off-by: Jacky Bai Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index b9abe143cb56..06443d52a429 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -80,7 +80,7 @@ mu1: mailbox@44230000 { }; tmu: tmu@44482000 { - compatible = "fsl,qoriq-tmu"; + compatible = "fsl,imx93-tmu"; reg = <0x44482000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_TMC_GATE>; From ec5c75673cb9d4c9a2a55a70d54a6ccb254f4ba4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 4 May 2026 19:54:40 -0400 Subject: [PATCH 002/131] arm64: dts: imx8mp-evk: add board-level mux for CAN2 and MICFIL The board integrates an on-board mux to route shared signals to either CAN2 or PDM (MICFIL). The mux is controlled by a GPIO. Add a pinctrl-based multiplexer node to describe this routing and ensure proper probe ordering of the dependent devices. Previously, MICFIL operation implicitly depended on the default level of PCA6416 GPIO3. After adding the pinctrl-multiplexer, make the dependency explicit. Reviewed-by: Ahmad Fatoum Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 23 ++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a7f3acdc36d1..2e092b0b52d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -50,6 +50,25 @@ status { }; }; + can_mux: mux-controller-0 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + }; + + can_mux_pinctrl: pinctrl-gpiomux { + compatible = "pinctrl-multiplexer"; + + can_fun: can-grp { + mux-states = <&can_mux 1>; + }; + + pdm_fun: pdm-grp { + mux-states = <&can_mux 0>; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, @@ -453,7 +472,7 @@ &flexcan1 { &flexcan2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-0 = <&pinctrl_flexcan2>, <&can_fun>; phys = <&flexcan_phy 1>; status = "disabled";/* can2 pin conflict with pdm */ }; @@ -720,7 +739,7 @@ &lcdif3 { &micfil { #sound-dai-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdm>; + pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>; assigned-clocks = <&clk IMX8MP_CLK_PDM>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <196608000>; From 368eb597c6ef0263931a3922648e8c7b83cd0536 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 4 May 2026 19:54:41 -0400 Subject: [PATCH 003/131] arm64: dts: imx8mp-evk: add flexcan2 overlay file Add flexcan2 overlay file, which enable flexcan2 node and disable micfil node. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ .../boot/dts/freescale/imx8mp-evk-flexcan2.dtso | 15 +++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 8ddaab127ab9..38b8f02bec82 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -361,6 +361,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb \ dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb + +imx8mp-evk-flexcan2-dtbs += imx8mp-evk.dtb imx8mp-evk-flexcan2.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-flexcan2.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb DTC_FLAGS_imx8mp-hummingboard-iiot := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso new file mode 100644 index 000000000000..f7d2674c45f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +&flexcan2 { + status = "okay"; /* can2 pin conflict with pdm */ +}; + +&micfil { + status = "disabled"; +}; From ffccbd6804e885f0fc23f0005f6bee7789a7a887 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 4 Jun 2026 10:38:20 +0800 Subject: [PATCH 004/131] arm64: dts: imx94: Correct PCIe outbound address space configuration Fix the PCIe outbound memory ranges for both pcie0 controllers on i.MX94. The memory window size was incorrectly set to 256MB during initial bring-up, but the hardware supports up to 4GB of outbound address space per controller. Additionally, the ECAM region cannot be mapped as I/O space. Use a memory-mapped region for I/O space instead, and relocate the 1MB I/O region to immediately follow the memory region at offset 0xf0000000 within each window. Update the outbound address space layout per controller as follows: - 3.5GB 64-bit prefetchable memory - 256MB 32-bit non-prefetchable memory - 1MB I/O Fixes: 8cd439f17758 ("arm64: dts: imx94: Add pcie0 and pcie0-ep supports") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index a6cb5a6e848b..1f9035e6cf15 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1374,8 +1374,9 @@ pcie0: pcie@4c300000 { <0 0x4c360000 0 0x10000>, <0 0x4c340000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; - ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, - <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>; + ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>, + <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>, + <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; From 6de3a7d7a4f653be4901d07425719c4e55805167 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 4 Jun 2026 10:38:21 +0800 Subject: [PATCH 005/131] arm64: dts: imx943: Correct PCIe outbound address space configuration Fix the PCIe outbound memory ranges for both pcie1 controllers on i.MX943. The memory window size was incorrectly set to 256MB during initial bring-up, but the hardware supports up to 4GB of outbound address space per controller. Additionally, the ECAM region cannot be mapped as I/O space. Use a memory-mapped region for I/O space instead, and relocate the 1MB I/O region to immediately follow the memory region at offset 0xf0000000 within each window. Update the outbound address space layout per controller as follows: - 3.5GB 64-bit prefetchable memory - 256MB 32-bit non-prefetchable memory - 1MB I/O Fixes: fa6067fd8ea7 ("arm64: dts: imx943: Add pcie1 and pcie1-ep supports") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index ed030d4bc7bd..cf5b3dbb47ff 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -218,8 +218,9 @@ pcie1: pcie@4c380000 { <0 0x4c3e0000 0 0x10000>, <0 0x4c3c0000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; - ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, - <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>; + ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>, + <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>, + <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; From c10743c09d5d6183117a6fb96b50a8016f437cdd Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:02 +0200 Subject: [PATCH 006/131] arm64: dts: imx8mp-var-som-symphony: add input keys Add the Back, Home and Menu keys connected through the GPIO expander on the Symphony carrier board. Also enable the SNVS power key. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 291f65e36865..25f707012f62 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -13,6 +13,31 @@ chosen { stdout-path = &uart2; }; + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-menu { + label = "Menu"; + linux,code = ; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + gpio-leds { compatible = "gpio-leds"; @@ -72,6 +97,10 @@ usb3-sata-sel-hog { }; }; +&snvs_pwrkey { + status = "okay"; +}; + /* Console */ &uart2 { pinctrl-names = "default"; From 9497ab2868eec57352b72ada3efec10e0428bb3e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:03 +0200 Subject: [PATCH 007/131] arm64: dts: imx8mp-var-som-symphony: enable USB support Enable the USB controllers on the Symphony carrier board. Add the PTN5150 Type-C controller for USB role switching, enable the USB3 PHYs and controllers, configure the I2C bus used by the Type-C controller, and set the first USB port in OTG mode and the second port in host mode. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 80 ++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 25f707012f62..cb27853ba281 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -72,8 +72,11 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* GPIO expander */ @@ -95,6 +98,22 @@ usb3-sata-sel-hog { line-name = "usb3_sata_sel"; }; }; + + /* USB Type-C Controller */ + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; }; &snvs_pwrkey { @@ -108,6 +127,52 @@ &uart2 { status = "okay"; }; +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + srp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-comp-dis-tune-percent = <115>; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <122>; + status = "okay"; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; + status = "okay"; +}; + /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -129,12 +194,25 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 >; }; + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 From 342414b800bfea45cbc118d51dc66a066411c033 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:04 +0200 Subject: [PATCH 008/131] arm64: dts: imx8mp-var-som-symphony: add TPM support Add the ST33KTPM2XI2C TPM device on the Symphony carrier board. Enable the I2C4 bus, add the PCAL6408 GPIO expander used by the TPM and describe the TPM reset line. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index cb27853ba281..7cf58198ef14 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -116,6 +116,31 @@ typec_dr_sw: endpoint { }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio", "sleep"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + pinctrl-2 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -201,6 +226,20 @@ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 From 5babe7594543573b57bff15bdda7f3343789f02f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:05 +0200 Subject: [PATCH 009/131] arm64: dts: imx8mp-var-som-symphony: add external RTC Add the DS1337 RTC on the Symphony carrier board and disable the internal SNVS RTC. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 7cf58198ef14..cb3348aafa07 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -139,12 +139,21 @@ st33ktpm2xi2c: tpm@2e { label = "tpm"; reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; }; &snvs_pwrkey { status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + /* Console */ &uart2 { pinctrl-names = "default"; From 6b680f24454cb5ce8a87df430b622bb5a602c91e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:06 +0200 Subject: [PATCH 010/131] arm64: dts: imx8mp-var-som-symphony: enable header UARTs Enable UART1 and UART4 on the Symphony carrier board and add the corresponding pinctrl configurations. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index cb3348aafa07..fdac4ceb4c19 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -154,6 +154,13 @@ &snvs_rtc { status = "disabled"; }; +/* Header UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + /* Console */ &uart2 { pinctrl-names = "default"; @@ -161,6 +168,13 @@ &uart2 { status = "okay"; }; +/* Header UART */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usb3_0 { status = "okay"; }; @@ -261,6 +275,13 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 @@ -268,6 +289,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40 + >; + }; + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 From 0ff57bce947f361a19e0c29945ed72cedef1f913 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 10 Jun 2026 17:26:21 +0800 Subject: [PATCH 011/131] dt-bindings: soc: imx: fsl,imx93-media-blk-ctrl: Allow LVDS Display Bridge child node i.MX93 SoC mediamix blk-ctrl contains one LDB_CTRL register and one LVDS register which control video output through a LVDS interface. Allow the LVDS Display Bridge(LDB) child node and add the child node to example. i.MX93 LDB child node(bridge@20) is an addressable node, while i.MX93 Parallel Display Format Configuration(PDFC) child node(dpi-bridge) is a non-addressable node. Mixing the addressable and non-addressable child nodes is allowed according to discussion [1]. Link: https://lore.kernel.org/all/n6akxiayi3g6gxcqhreb4iaohmeokoalnqup6h5r2fwdt4zijt@u2wyps55ayqm/ [1] Signed-off-by: Liu Ying Reviewed-by: Rob Herring (Arm) Signed-off-by: Frank Li --- .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index d828c2e82965..124f5c206ee3 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -26,6 +26,12 @@ properties: reg: maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#power-domain-cells': const: 1 @@ -92,6 +98,11 @@ properties: - compatible - ports + bridge@20: + type: object + $ref: /schemas/display/bridge/fsl,ldb.yaml# + unevaluatedProperties: false + allOf: - if: properties: @@ -112,6 +123,7 @@ allOf: - const: lcdif - const: isi - const: csi + bridge@20: false - if: properties: compatible: @@ -163,6 +175,8 @@ examples: <&clk IMX93_CLK_MIPI_DSI_GATE>; clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; + #address-cells = <1>; + #size-cells = <1>; #power-domain-cells = <1>; dpi-bridge { @@ -190,4 +204,29 @@ examples: }; }; }; + + bridge@20 { + compatible = "fsl,imx93-ldb"; + reg = <0x20 0x4>, <0x24 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; }; From 9c4d966c046c117ec690a24ef50a83605d004c7d Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 10 Jun 2026 17:26:22 +0800 Subject: [PATCH 012/131] arm64: dts: imx93: Add LVDS Display Bridge support Add LVDS Display Bridge(LDB) child node to mediamix blk-ctrl node so that video could be output through a LVDS interface. Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 06443d52a429..e926b6360a9d 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -178,6 +178,7 @@ &lcdif { port { lcdif_to_ldb: endpoint@1 { reg = <1>; + remote-endpoint = <&ldb_from_lcdif>; }; lcdif_to_dsi: endpoint@2 { @@ -186,6 +187,42 @@ lcdif_to_dsi: endpoint@2 { }; }; +&media_blk_ctrl { + #address-cells = <1>; + #size-cells = <1>; + + lvds_bridge: bridge@20 { + compatible = "fsl,imx93-ldb"; + reg = <0x20 0x4>, <0x24 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + }; + }; +}; + &src { mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; From 69e50e84bbcefdb534e1bd2a8e3f472be98aae2c Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 10 Jun 2026 17:26:23 +0800 Subject: [PATCH 013/131] arm64: dts: imx93-11x11-evk: Add DY1212W-4856 LVDS panel DY1212W-4856 [1] is a 12.1" (WXGA) TFT LCD panel with LVDS interface. The panel's 40-pin connector allows it to be directly connected to i.MX93 11x11 EVK board. Link: https://www.nxp.com/design/design-center/development-boards-and-designs/dy1212w-4856-tft-lcd-panel-with-lvds-interface:DY1212W-4856 [1] Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../imx93-11x11-evk-dy1212w-4856.dtso | 81 +++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 38b8f02bec82..447c5f7721d4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -592,6 +592,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-tianma-tm050rdh03.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb + +imx93-11x11-evk-dy1212w-4856-dtbs += imx93-11x11-evk.dtb imx93-11x11-evk-dy1212w-4856.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk-dy1212w-4856.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso new file mode 100644 index 000000000000..35f7c5699e3a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + panel-lvds { + compatible = "boe,ev121wxm-n10-1850"; + backlight = <&backlight_lvds>; + power-supply = <&buck4>; + + panel-timing { + /* + * Set clock frequency to 71142858Hz to accommodate + * IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate + * table. + */ + clock-frequency = <71142858>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vfront-porch = <3>; + vback-porch = <14>; + vsync-len = <6>; + }; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight_lvds { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +&media_blk_ctrl { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_VIDEO_PLL>; + /* + * Set IMX93_CLK_MEDIA_DISP_PIX rate to 71142858Hz to accommodate + * IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate table. + */ + assigned-clock-rates = <400000000>, <133333333>, <71142858>, <498000000>; + status = "okay"; +}; From c33b03ac7ff7ca0267ae7a4284a2b9258483614d Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 11 Jun 2026 10:18:59 +0200 Subject: [PATCH 014/131] arm64: dts: imx8mp-frdm: Add missing HDMI DDC pinctrl Configure HDMI DDC SCL/SDA pins to support reading EDID. Signed-off-by: Philipp Zabel Fixes: 95d7d7d2ad27 ("arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi support") Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts index 5fb9714215bf..f43330d1ff8b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -562,6 +562,8 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 pinctrl_hdmi: hdmigrp { fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 >; }; From 67a6b5ef7edf76236f1afe5d11c35bb94a4e41f9 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 16 Jun 2026 18:52:00 +0800 Subject: [PATCH 015/131] arm64: dts: imx8mq-evk: add uart3 and bluetooth node Add uart3 and bluetooth node. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e7d87ea81b69..b9b03416aa39 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -498,6 +498,19 @@ &uart1 { status = "okay"; }; +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -657,6 +670,15 @@ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 From e4e7ced4ad38d4b9a3883766ccb2d1dae0df4f34 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 4 Jun 2026 00:53:59 +0200 Subject: [PATCH 016/131] arm64: dts: imx8mm-var-som-symphony: add wakeup sources Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 857325ef4461..090752014ee2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -55,18 +55,21 @@ key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; }; @@ -187,6 +190,7 @@ ft5x06_ts: touchscreen@38 { touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { From 47f8149d31535adafff43ff23084a97600686ddd Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 4 Jun 2026 00:54:00 +0200 Subject: [PATCH 017/131] arm64: dts: imx8mm-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 090752014ee2..fd0a1862ce90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -168,6 +168,14 @@ pca6408: gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e { From dd7858bbdfa84beddf7d08bb82eacc8010221493 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:07 +0200 Subject: [PATCH 018/131] arm64: dts: imx8mp-var-som-symphony: enable PCIe Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board. Describe the PERST# reset GPIO and configure the PHY to use an external reference clock input. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index fdac4ceb4c19..698f02fc39a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,12 @@ led-0 { }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -146,6 +152,18 @@ rtc@68 { }; }; +&pcie { + reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; From dfee5fefc3ecd29794c79b3f5284d759cfdc869e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:08 +0200 Subject: [PATCH 019/131] arm64: dts: imx8mp-var-som-symphony: add HDMI support Enable the HDMI display pipeline and HDMI audio support on the Symphony carrier board. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 698f02fc39a5..0beaee5f81c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,18 @@ led-0 { }; }; + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -74,6 +86,43 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { states = <3300000 0x0 1800000 0x1>; vin-supply = <&ldo5>; }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; }; &i2c3 { @@ -152,6 +201,10 @@ rtc@68 { }; }; +&lcdif3 { + status = "okay"; +}; + &pcie { reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; status = "okay"; @@ -253,6 +306,15 @@ &usdhc2 { }; &iomuxc { + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 From 6651fb350bff74652edf8fdd2193ad33d69a968d Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:09 +0200 Subject: [PATCH 020/131] arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen Add the FT5206 capacitive touchscreen controller on the Symphony carrier board. Describe the interrupt pin and touchscreen geometry. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 0beaee5f81c9..f8a4b5b2e9fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -195,6 +195,21 @@ st33ktpm2xi2c: tpm@2e { reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; }; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; @@ -306,6 +321,12 @@ &usdhc2 { }; &iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x16 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 From c0cb98e3230fd5959bb8075e059fef60d0477698 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:10 +0200 Subject: [PATCH 021/131] arm64: dts: imx8mp-var-som-symphony: enable ECSPI2 Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl configuration for the SPI signals and chip select GPIO. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index f8a4b5b2e9fb..387bbe3454c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -99,6 +99,13 @@ &aud2htx { status = "okay"; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &hdmi_pai { status = "okay"; }; @@ -327,6 +334,15 @@ MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x16 >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x12 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x12 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x12 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 From a062ace84151ca83d39e6470c0a23c51c0d343df Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:11 +0200 Subject: [PATCH 022/131] arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 387bbe3454c3..7f5109bb4182 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -193,6 +193,14 @@ pcal6408: gpio@21 { reg = <0x21>; #gpio-cells = <2>; gpio-controller; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e { From 2558c810a6d28614a8b076123762ff53f4acef5e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:12 +0200 Subject: [PATCH 023/131] arm64: dts: imx8mp-var-som-symphony: enable PWM1 Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-var-som-symphony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 7f5109bb4182..54cb5725c4bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -247,6 +247,12 @@ &pcie_phy { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -400,6 +406,12 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 From 8d7fc066c18a99cd95226a660f4ddcf353d91bd8 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:13 +0200 Subject: [PATCH 024/131] arm64: dts: imx8mp-var-som-symphony: enable CAN Enable the FlexCAN2 controller on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-var-som-symphony.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 54cb5725c4bf..93dee9ec0b9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -106,6 +106,12 @@ &ecspi2 { status = "okay"; }; +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + &hdmi_pai { status = "okay"; }; @@ -357,6 +363,13 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 >; }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 From 0bfd9e56f4868b66bdafed6a9f867629899bc199 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:14 +0200 Subject: [PATCH 025/131] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port Add support for the second Ethernet interface available on the Symphony carrier board. Enable the FEC controller, add the MaxLinear MXL86110 Gigabit Ethernet PHY on the MDIO bus, describe its reset and power configuration, and add the required RGMII pinctrl settings. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 93dee9ec0b9b..e928a3d44b1d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -66,6 +66,16 @@ pcie0_refclk: pcie0-refclk { clock-frequency = <100000000>; }; + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -106,6 +116,33 @@ &ecspi2 { status = "okay"; }; +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -363,6 +400,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 >; }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 + >; + }; + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 From 417b121ab93cd5a0929a663b9dc5da5595e290d3 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:15 +0200 Subject: [PATCH 026/131] arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs Add the GPIO pinctrl state and GPIO descriptors required for I2C1 bus recovery on the VAR-SOM-MX8M-PLUS. This allows the I2C controller to recover the bus if SDA or SCL are held low by a device. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 49467b48d0b0..61786eee0e82 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -180,8 +180,11 @@ led@1 { &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -415,6 +418,13 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c2 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c2 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 From 4596f1624bf3abdc7782fbca0385bc0a8afb3d51 Mon Sep 17 00:00:00 2001 From: Paul Gerber Date: Thu, 25 Jun 2026 07:14:44 +0200 Subject: [PATCH 027/131] dt-bindings: arm: fsl: add TQMa8MPxS board TQMa8MPxS is a SOM family using NXP i.MX8MP CPU family. MB-SMARC-2 is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mp-" for the module and "tq,imx8mp--" Signed-off-by: Paul Gerber Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 86876311ec59..6237fb2ae50e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1310,6 +1310,18 @@ properties: - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM - const: fsl,imx8mp + - description: + TQMa8MPxS is a series of SOM featuring NXP i.MX8MP system-on-chip + variants. It has the SMARC-2.0 form factor and is designed to be + placed on different carrier boards. All CPU variants use the same + device tree hence only one compatible is needed. MB-SMARC-2 is a + carrier reference design. + items: + - enum: + - tq,imx8mp-tqma8mpqs-mb-smarc-2 # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM on MB-SMARC-2 + - const: tq,imx8mp-tqma8mpqs # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM + - const: fsl,imx8mp + - description: Variscite VAR-SOM-MX8M Plus based boards items: - const: variscite,var-som-mx8mp-symphony From 6f0c003f0ddbfde3a311d350d2b3c1c38ac95dd4 Mon Sep 17 00:00:00 2001 From: Paul Gerber Date: Thu, 25 Jun 2026 07:14:45 +0200 Subject: [PATCH 028/131] arm64: dts: freescale: add initial device tree for TQMa8MPQS with i.MX8MP This adds support for TQMa8MPQS module on MB-SMARC-2 board. Signed-off-by: Paul Gerber Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts | 380 ++++++ .../boot/dts/freescale/imx8mp-tqma8mpqs.dtsi | 1178 +++++++++++++++++ 3 files changed, 1559 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 447c5f7721d4..33ed09e49871 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -443,6 +443,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt101tm023.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10-dtbs += imx8mp-tx8p-ml81-moduline-display-106.dtb \ imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts new file mode 100644 index 000000000000..f01af630a7c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +/dts-v1/; + +#include +#include "imx8mp-tqma8mpqs.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxS on MB-SMARC-2"; + compatible = "tq,imx8mp-tqma8mpqs-mb-smarc-2", "tq,imx8mp-tqma8mpqs", "fsl,imx8mp"; + chassis-type = "embedded"; + + chosen { + stdout-path = &uart3; + }; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander0 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "X6"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + panel_lvds0: panel-lvds0 { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds0>; + power-supply = <®_lvds0>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + + panel_lvds1: panel-lvds1 { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds1>; + power-supply = <®_lvds1>; + status = "disabled"; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_lvds0: regulator-lvds0 { + compatible = "regulator-fixed"; + regulator-name = "LCD0_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds1: regulator-lvds1 { + compatible = "regulator-fixed"; + regulator-name = "LCD1_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x38000000>; + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-asrc = <&easrc>; + audio-cpu = <&sai5>; + audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; + + usb-connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "X4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; +}; + +&easrc { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; +}; + +&eqos { + status = "okay"; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + }; +}; + +ðphy3 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + }; +}; + +&fec { + status = "okay"; +}; + +&flexcan1 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clock-names = "mclk"; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + }; + + eeprom2: eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + +&ldb_lvds_ch1 { + remote-endpoint = <&panel_in_lvds1>; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcie_phy { + fsl,clkreq-unsupported; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +®_usdhc2_vmmc { + startup-delay-us = <100>; + off-on-delay-us = <200000>; + status = "okay"; +}; + +®_usdhc2_vqmmc { + status = "okay"; +}; + +&sai3 { + status = "okay"; +}; + +&sai5 { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi new file mode 100644 index 000000000000..20d55eeead57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi @@ -0,0 +1,1178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxS"; + compatible = "tq,imx8mp-tqma8mpqs", "fsl,imx8mp"; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "SDIO_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5>; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&audio_blk_ctrl { + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <147333333>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 12 GPIO_ACTIVE_LOW>; +}; + +/* GBE0 */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + ethphy3: ethernet-phy@3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio2>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +/* GBE1 */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + fsl,magic-packet; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66666666>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <&buck5>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "SLEEP", "BATLOW#", "", "LID", + "", "GPIO10", "CHARGING#", "CHG_PRSNT#", + "PMIC_IRQ#", "ESPI_CS1_ALERT#", "USB1_OTG_ID", "USB2_OTG_ID", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + pmic_irq_hog: pmic-irq-hog { + gpio-hog; + gpios = <8 0>; + input; + line-name = "PMIC_IRQ#"; + }; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hoggpio2>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "PERST#", "PEWAKE#", + "SDIO_CD#", "", "", "", + "", "", "", "SDIO_PWR_EN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + enet0-int-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "ENET0_INT#"; + }; + + enet1-int-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "ENET_INT#"; + }; + + pewake-hog { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PEWAKE#"; + }; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "GPIO4", + "GPIO3", "", "", "", + "", "", "", "", + "TEMP_EVENT#", "", "", ""; + + temp-event-hog { + gpio-hog; + gpios = <28 0>; + input; + line-name = "TEMP_EVENT#"; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_sdp>, <&pinctrl_espi_rst>; + + gpio-line-names = "RTC_INT#", "GPIO8", "", "", + "GPIO9", "ESPI_RST#", "", "", + "", "", "", "", + "", "", "", "", + "", "", "GBE0_SDP_DIR", "", + "GPIO7", "", "", "", + "", "GPIO0", "GPIO1", "", + "GPIO2", "GPIO6", "", ""; + + rtc-int-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "RTC_INT#"; + }; + + espi-reset-hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "ESPI_RST#"; + }; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + + gpio-line-names = "", "", "", "", + "", "GPIO5", "", "", + "", "", "GPIO12", "GPIO11", + "", "GPIO13", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + dp-hpd-int-hog { + gpio-hog; + gpios = <21 0>; + input; + line-name = "DP_HPD_INT"; + }; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; +}; + +&i2c1 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + vcc-supply = <&buck5>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio4>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom1: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <&buck5>; + }; + + /* protectable identification memory (part of M24C64-D @50) */ + eeprom@58 { + compatible = "atmel,24c64d-wl"; + reg = <0x58>; + size = <32>; + pagesize = <32>; + vcc-supply = <&buck5>; + }; + + /* protectable identification memory (part of M24C64-D @54) */ + eeprom@5c { + compatible = "atmel,24c64d-wl"; + reg = <0x5c>; + size = <32>; + pagesize = <32>; + vcc-supply = <&buck5>; + }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; + + inertial-sensor@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + vdd-supply = <&buck4>; + vddio-supply = <&buck4>; + }; +}; + +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* unused */ + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tmp1075>; + vs-supply = <&buck4>; + }; + + expander0: gpio@73 { + compatible = "nxp,pca9538"; + reg = <0x73>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5>; + gpio-line-names = "LCD0_BKLT_EN", "LCD0_VDD_EN", + "LCD1_BKLT_EN", "LCD1_VDD_EN", + "DP_BRIDGE_EN", "HUB_RST#", + "ENET0_RESET#", "ENET1_RESET#"; + }; +}; + +&i2c3 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0xf>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; + toshiba,hpd-pin = <0>; + interrupts-extended = <&gpio5 21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + toshiba,pre-emphasis = /bits/ 8 <1 1>; + }; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +// Change parent clock of disp1 pixel clock to audio_pll2 +&media_blk_ctrl { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_500M>; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <1000000000>; + samsung,esc-clock-frequency = <10000000>; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&dsi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + clock-names = "ref"; + clocks = <&pcieclk 0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; +}; + +&uart3 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; +}; + +&usb3_phy0 { + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + fsl,over-current-active-low; +}; + +&usb3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented, but not a full featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + /* SMARC-2 USB0 interface only supports USB 2.0 signals */ + maximum-speed = "high-speed"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vqmmc-supply = <®_usdhc2_vqmmc>; + /* NOTE: CD / WP and VMMC support depends on mainboard */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_eqos_event: eqosevtgrp { + fsl,pins = , + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = ; + }; + + pinctrl_espi_rst: espirstgrp { + fsl,pins = ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec_event: fecevtgrp { + fsl,pins = , + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_sdp: gbegrp { + fsl,pins = , + ; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = , + ; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = , + , + ; + }; + + pinctrl_hoggpio2: hoggpio2grp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = , + ; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = , + ; + }; + + pinctrl_i2c6_gpio: i2c6-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = ; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x94 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x94 + MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x94 + MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x94 + >; + }; + + pinctrl_tc9595: tc9595grp { + fsl,pins = ; + }; + + pinctrl_tmp1075: tmp1075grp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = , + ; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = , + ; + }; + + pinctrl_usbcon0: usb0congrp { + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; From 0d8c74f493e941ff61ce4dcfee75f2891bd44454 Mon Sep 17 00:00:00 2001 From: Paul Gerber Date: Thu, 25 Jun 2026 07:14:46 +0200 Subject: [PATCH 029/131] arm64: dts: freescale: add LVDS overlays for TQMa8MPxS This adds overlays for the supported LVDS display tianma tm070jvhg33 for both LVDS channels. The display timings have to be specified explicitly. Using the typical pixel clock, the LDB clock can not be configured as the 7-fold of that. By setting pixel clock to 74.25 MHz, LDB can be configured to exactly 519.75 MHz. Signed-off-by: Paul Gerber Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 5 +++ ...qma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso | 43 +++++++++++++++++++ ...qma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso | 43 +++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 33ed09e49871..b56afb1956ca 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -502,6 +502,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb +imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtbo +imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso new file mode 100644 index 000000000000..2cf1de8c05b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + status = "okay"; +}; + +&panel_lvds0{ + compatible = "tianma,tm070jvhg33"; + status = "okay"; + + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <64>; + hback-porch = <5>; + hsync-len = <1>; + vfront-porch = <40>; + vback-porch = <2>; + vsync-len = <1>; + de-active = <1>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso new file mode 100644 index 000000000000..cbad0cfab292 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +/dts-v1/; +/plugin/; + +&backlight_lvds1 { + status = "okay"; +}; + +&panel_lvds1{ + compatible = "tianma,tm070jvhg33"; + status = "okay"; + + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <64>; + hback-porch = <5>; + hsync-len = <1>; + vfront-porch = <40>; + vback-porch = <2>; + vsync-len = <1>; + de-active = <1>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; From 3ee55e19db02d25d7c1155c3a6ab954aacfc55c5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 25 Jun 2026 07:14:47 +0200 Subject: [PATCH 030/131] arm64: dts: freescale: Add dual-channel LVDS overlay for TQMa8MPxS This adds an overlay for the supported LVDS display AUO G133HAN01. Configure the video PLL frequency to exactly match typical pixel clock of 141.200 MHz. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...p-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso | 81 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b56afb1956ca..430085123b4e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -502,8 +502,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb +imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtbo imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtbo imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso new file mode 100644 index 000000000000..2d2dfda944fa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + status = "okay"; +}; + +&panel_lvds0 { + compatible = "auo,g133han01"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_in_lvds1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +// Update VIDEO_PLL1 frequency +&media_blk_ctrl { + assigned-clock-rates = <500000000>, <200000000>, + <0>, <0>, <500000000>, + <988400000>; +}; + +&pwm3 { + status = "okay"; +}; From 9c269fe7eae8cb60d8d6c326dd8955818722fae9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 16 Jun 2026 12:43:09 +0200 Subject: [PATCH 031/131] arm64: dts: imx93-kontron: set memory node to 0x80000000/1GiB The start address of the DRAM area is 0x80000000. The minimal size of the DDR on the SoM is 1 GiB. Fixes: 2b52fd6035b7 ("arm64: dts: Add support for Kontron i.MX93 OSM-S SoM and BL carrier board") Signed-off-by: Frieder Schrempf Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index c79b1df339db..f881912cde46 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -15,9 +15,9 @@ aliases { rtc1 = &bbnsm_rtc; }; - memory@40000000 { + memory@80000000 { device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; + reg = <0x0 0x80000000 0 0x40000000>; }; chosen { From 3385e2f77182469940c136b9eeedf01f27b7441f Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 22 Jun 2026 11:35:06 +0200 Subject: [PATCH 032/131] arm64: dts: freescale: imx95-toradex-smarc: add alias for lpuart5 Add alias for lpuart5 so the UART gets a stable line number. Without this alias, the lpuart driver fails: fsl-lpuart 42590000.serial: failed to get alias id, errno -19 This prevents the Bluetooth controller connected to this UART from working. Fixes: 104a391bb6ff ("arm64: dts: freescale: imx95-toradex-smarc: Enable bluetooth on lpuart5") Signed-off-by: Francesco Dolcini Acked-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 7d760470201f..a6c5398a81e3 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -24,6 +24,7 @@ aliases { serial1 = &lpuart1; serial2 = &lpuart6; serial3 = &lpuart3; + serial4 = &lpuart5; }; chosen { From b1b6c1c4d3c63d8097c933009bdb618d1be18305 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 25 Jun 2026 13:47:09 +0800 Subject: [PATCH 033/131] arm64: dts: imx8mp-ab2: Enable MU2 for DSP communication Enable the MU2 (Message Unit 2) node on the i.MX8MP Audio Board v2. MU2 is required for inter-processor communication between the application CPU and the HiFi4 DSP, allowing DSP firmware to exchange control and status messages with the Linux host. Without this change, the DSP driver cannot establish the message channel and DSP audio processing is non-functional. Fixes: bf68c18150efc ("arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2)") Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts index 443e4fd5b9bf..285bf79864eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -775,6 +775,10 @@ &micfil { status = "okay"; }; +&mu2 { + status = "okay"; +}; + &pwm1 { pinctrl-0 = <&pinctrl_pwm1>; pinctrl-names = "default"; From 65a02d82c59dcf1148f8325c176fba6c2172564f Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 30 Jun 2026 10:30:05 +0800 Subject: [PATCH 034/131] arm64: dts: imx94: add PCIe Root Port node Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the root port node and pave the path to add the reset-gpios and so on properties in root port later. Signed-off-by: Richard Zhu Reviewed-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 11 +++++++++++ arch/arm64/boot/dts/freescale/imx943.dtsi | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 1f9035e6cf15..dfbb73603cb2 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1411,6 +1411,17 @@ pcie0: pcie@4c300000 { power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; fsl,max-link-speed = <3>; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie-ep@4c300000 { diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index cf5b3dbb47ff..01152fd0efa5 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -255,6 +255,17 @@ pcie1: pcie@4c380000 { power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; fsl,max-link-speed = <3>; status = "disabled"; + + pcie1_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_ep: pcie-ep@4c380000 { From eeaf1a44be8354c197107535727db9e1fa53472f Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 30 Jun 2026 10:30:06 +0800 Subject: [PATCH 035/131] arm64: dts: imx943-evk: add PCIe root port node and according properties Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the root port node and add the reset-gpios property in root port. Move the regulator to root port nodes as well, because that the PCI pwrctrl framework had been integrated into pci-imx6 driver. The backward compatibility is not a concern since i.MX94 is a newly introduced platform that is still under active development. Signed-off-by: Richard Zhu Reviewed-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 7cfd42468950..674410e541cb 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -1034,12 +1034,15 @@ &pcie0 { <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; - reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; - vpcie3v3aux-supply = <®_m2_wlan>; supports-clkreq; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_m2_wlan>; +}; + &pcie0_ep { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; @@ -1058,12 +1061,15 @@ &pcie1 { <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; - reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; - vpcie3v3aux-supply = <®_slot_pwr>; supports-clkreq; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_slot_pwr>; +}; + &pcie1_ep { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; From 5206b2eec56ee5d50b02a0aac2c8a66f76556d37 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 3 Jul 2026 17:06:49 +0200 Subject: [PATCH 036/131] arm64: dts: freescale: imx95-var-dart: enable NETC block control Enable the NETC and NETCMIX block control nodes on the DART-MX95 SoM. These block control nodes are required to enable and use the NETC Ethernet ports. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi index a20fadacaa6d..f3b44a866917 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi @@ -176,6 +176,10 @@ &mu7 { status = "okay"; }; +&netc_blk_ctrl { + status = "okay"; +}; + &netc_emdio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>; @@ -213,6 +217,10 @@ &netc_timer { status = "okay"; }; +&netcmix_blk_ctrl { + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; From 68427905850302612bd68dcec7baf791ca6f8032 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 17:53:08 +0200 Subject: [PATCH 037/131] arm64: dts: imx95-var-dart: wm8904: Add INL1 as DMICDAT1 On the DART-MX95 platform, INL1/DMICDAT1 is used as the DMIC data line. Add the wlf,in1l-as-dmicdat1 property to reflect this configuration. This enables the internal MUX to switch between the ADC and DMIC as the capture input. Co-developed-by: Alexander Herfurtner Signed-off-by: Alexander Herfurtner Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi index f3b44a866917..b4c55bd33858 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi @@ -158,6 +158,8 @@ wm8904: audio-codec@1a { /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; /* GPIO1 = DMIC_CLK, don't touch others */ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; }; }; From 66738404bd0ab5b515d32bf4bd64f2cbe91a4b4d Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:30 +0800 Subject: [PATCH 038/131] arm64: dts: imx8mm-evk: Add power supply property to Root Port node Add the power supply property to the Root Port child node to support the new PCI pwrctrl framework. Legacy power supply property is retained for backward compatibility with existing kernels. New device trees should specify power supply at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e03aba825c18..ec49cbbfd9ce 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -542,6 +542,7 @@ &pcie0 { assigned-clock-rates = <10000000>, <250000000>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie0>; supports-clkreq; status = "okay"; @@ -562,6 +563,7 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie0>; }; &sai2 { From 6320522f617d020b0e65cabb4cc4b35518fc8222 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:31 +0800 Subject: [PATCH 039/131] arm64: dts: imx8mp-evk: Add power supply properties to Root Port node Add the power supply properties to the Root Port child nodes to support the new PCI pwrctrl framework. Legacy power supply properties are retained for backward compatibility with existing kernels. New device trees should specify power supplies at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2e092b0b52d9..3b1b90af34a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -791,6 +791,7 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie0>; vpcie3v3aux-supply = <®_pcie0>; supports-clkreq; @@ -805,6 +806,8 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie0>; + vpcie3v3aux-supply = <®_pcie0>; }; &pwm1 { From 919519e84ea2aaf9ccab968e0aa9d97586bd9ab8 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:32 +0800 Subject: [PATCH 040/131] arm64: dts: imx8mq-evk: Add power supply properties to Root Port node Add the power supply properties to the Root Port child nodes to support the new PCI pwrctrl framework. Legacy power supply properties are retained for backward compatibility with existing kernels. New device trees should specify power supplies at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index b9b03416aa39..1f07f1089026 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -403,6 +403,7 @@ &pcie1 { <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie1>; vpcie3v3aux-supply = <®_pcie1>; vph-supply = <&vgen5_reg>; @@ -422,6 +423,8 @@ &pcie1_ep { &pcie1_port0 { reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie1>; + vpcie3v3aux-supply = <®_pcie1>; }; &pgc_gpu { From c4dad11102b34dfcb8facb29b0270f8fd71206d3 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:33 +0800 Subject: [PATCH 041/131] arm64: dts: imx8dxl/qm/qxp: Add power supply properties to Root Port node Add the power supply properties to the Root Port child nodes to support the new PCI pwrctrl framework. Legacy power supply properties are retained for backward compatibility with existing kernels. New device trees should specify power supplies at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 78e8d41e6791..0ede0c7ed422 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -677,6 +677,7 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; status = "okay"; @@ -692,6 +693,8 @@ &pcie0_ep { &pcieb_port0 { reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcieb>; + vpcie3v3aux-supply = <®_pcieb>; }; &sai0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index f706c86137c0..9e49ac377162 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -812,6 +812,7 @@ &pciea { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pciea>; vpcie3v3aux-supply = <®_pciea>; supports-clkreq; @@ -820,6 +821,8 @@ &pciea { &pciea_port0 { reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pciea>; + vpcie3v3aux-supply = <®_pciea>; }; &pcieb { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 2af32eca612a..857a6e512228 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -732,6 +732,7 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; supports-clkreq; @@ -748,6 +749,8 @@ &pcie0_ep { &pcieb_port0 { reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcieb>; + vpcie3v3aux-supply = <®_pcieb>; }; &scu_key { From d61fa5049fcfd3a9d048038acf6c0d5993baee12 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:34 +0800 Subject: [PATCH 042/131] arm64: dts: imx95: Move power supply properties to Root Port node Move the power supply properties from the PCIe controller nodes to the Root Port child nodes to support the new PCI pwrctrl framework. Since i.MX95 is the new platform that under development phase, it should be fine to simply move the power supply properties. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 7d820a0f80b2..6aedcbbe915a 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -555,8 +555,6 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_m2_pwr>; - vpcie3v3aux-supply = <®_m2_pwr>; supports-clkreq; status = "disabled"; }; @@ -570,6 +568,8 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_m2_pwr>; + vpcie3v3aux-supply = <®_m2_pwr>; }; &sai1 { diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 2e463bc7c601..340ab0253ec2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -542,8 +542,6 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie0>; - vpcie3v3aux-supply = <®_pcie0>; supports-clkreq; status = "okay"; }; @@ -557,6 +555,8 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie0>; + vpcie3v3aux-supply = <®_pcie0>; }; &pcie1 { @@ -564,8 +564,6 @@ &pcie1 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_slot_pwr>; - vpcie3v3aux-supply = <®_slot_pwr>; status = "okay"; }; @@ -578,6 +576,8 @@ &pcie1_ep { &pcie1_port0 { reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_slot_pwr>; + vpcie3v3aux-supply = <®_slot_pwr>; }; &sai1 { From 77c0d4cfd43353e8bdebc4eab8e579518e2dbf5f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 12:05:55 +0200 Subject: [PATCH 043/131] dt-bindings: arm: fsl: add Variscite DART-MX8M PLUS Boards Add DT compatible strings for Variscite DART-MX8MP SoM and Variscite development carrier Board. Acked-by: Conor Dooley Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6237fb2ae50e..f96f3d31dac1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1322,6 +1322,12 @@ properties: - const: tq,imx8mp-tqma8mpqs # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM - const: fsl,imx8mp + - description: Variscite DART-MX8M Plus based boards + items: + - const: variscite,var-dart-mx8mp-sonata # Variscite DART-MX8MP on Sonata Development Board + - const: variscite,var-dart-mx8mp # Variscite DART-MX8MP SOM + - const: fsl,imx8mp + - description: Variscite VAR-SOM-MX8M Plus based boards items: - const: variscite,var-som-mx8mp-symphony From d08607aa231e026cd94b4c33077f8b8d28731952 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 12:05:56 +0200 Subject: [PATCH 044/131] arm64: dts: freescale: Add support for Variscite DART-MX8M-PLUS Add device tree support for the Variscite DART-MX8MP system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8M Plus MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-var-dart.dtsi | 475 ++++++++++++++++++ 1 file changed, 475 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi new file mode 100644 index 000000000000..889e41f2af14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX8M-PLUS + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "Variscite DART-MX8M-PLUS Module"; + compatible = "variscite,var-dart-mx8mp", "fsl,imx8mp"; + + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 8 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&mu2 { + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <11536000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* BT module */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0xc0 + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x150 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0xc0 + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 + >; + }; +}; From 41cd3d91ca8595f48cae5169ff8e4089c88670f2 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 12:05:57 +0200 Subject: [PATCH 045/131] arm64: dts: imx8mp-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-PLUS system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - HDMI support - GPIO Expanders - RTC module - TPM module - CAN peripherals Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-var-dart-sonata.dts | 733 ++++++++++++++++++ 2 files changed, 734 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 430085123b4e..01d4ddfde098 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -453,6 +453,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts new file mode 100644 index 000000000000..983d67a0c1de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX8M-PLUS + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-var-dart.dtsi" + +/ { + model = "Variscite DART-MX8M-PLUS on Sonata-Board"; + compatible = "variscite,var-dart-mx8mp-sonata", + "variscite,var-dart-mx8mp", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-emmc { + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + label = "eMMC"; + linux,default-trigger = "mmc2"; + }; + }; + + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vmmc_usdhc2>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; + + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + clocks = <&clk40m>; + spi-max-frequency = <20000000>; + }; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + eth10g-en-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "eth10g_sel"; + }; + + pcie2-en-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie2_sel"; + }; + + /* RGB_SEL + * Keep signal low and not floating + */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6408>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcie { + reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +/* Console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-vref-tune-percent = <122>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-comp-dis-tune-percent = <115>; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + status = "okay"; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c6 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x12 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x12 + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x1d0 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0xc6 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c2 + >; + }; + + pinctrl_pca6408: pca6408grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x1c6 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xc0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; From 5e7e00f811fb1808352a22d18e20aa8026c6d73c Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Tue, 30 Jun 2026 14:54:03 +0200 Subject: [PATCH 046/131] arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node Update the SIUL2 pinctrl node to describe the additional register ranges and DT properties used by the updated SIUL2 driver. Besides the MSCR and IMCR ranges used for pinmux and pin configuration, the SIUL2 block also provides PGPDO and PGPDI registers for GPIO output and input operations, as well as an EIRQ register window for external interrupt configuration. The driver supports both legacy pinctrl-only DTs and extended DTs with GPIO and IRQ. Reflect these resources in the SIUL2 pinctrl node by adding: - the PGPDO and PGPDI register ranges - the EIRQ register range - gpio-controller, #gpio-cells and gpio-ranges - interrupt-controller, #interrupt-cells and interrupts Keep the hardware description aligned with the updated SIUL2 driver, where pinctrl, GPIO data access and the EIRQ register block are described under the same device node. Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Bartosz Golaszewski Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 21 ++++++++++++++++++++- arch/arm64/boot/dts/freescale/s32g3.dtsi | 21 ++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 809019ea0e29..8dc0c5d9f368 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -135,7 +135,26 @@ pinctrl: pinctrl@4009c240 { /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ window: DISR0..IFEER0 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; jtag_pins: jtag-pins { jtag-grp0 { diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 22e80fc03f9c..129d6ad8e5c6 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -193,7 +193,26 @@ pinctrl: pinctrl@4009c240 { /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ window: DISR0..IFEER0 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; jtag_pins: jtag-pins { jtag-grp0 { From 6e62bc736674601a8764f01217ac539e75d71fc8 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:26 +0800 Subject: [PATCH 047/131] arm64: dts: imx8mp-evk: add typec node The first USB port features a Type-C connector with dual data role and dual power role capabilities. Add the Type-C device node and enable the corresponding USB controller and phy node. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 69 ++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 3b1b90af34a0..627fbe2b6a16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx8mp.dtsi" / { @@ -655,6 +656,35 @@ adv7535_out: endpoint { }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + orientation-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + }; + }; }; &i2c3 { @@ -873,6 +903,38 @@ &uart2 { status = "okay"; }; +&usb3_phy0 { + fsl,phy-tx-vref-tune-percent = <122>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-comp-dis-tune-percent = <115>; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -1201,6 +1263,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + pinctrl_usb1_vbus: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 From 05d5a7fcb2399d4398a651dcf3b4a01290418435 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:27 +0800 Subject: [PATCH 048/131] arm64: dts: imx8mp-evk: add usb3_phy1 tuning properties Add some tuning properties for usb3_phy1 to improve signal. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 627fbe2b6a16..7bdd641292fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -936,6 +936,8 @@ usb3_data_hs: endpoint { }; &usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; status = "okay"; }; From 94aad340fbf22a8a2484879c1e862c856d0e946f Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:28 +0800 Subject: [PATCH 049/131] arm64: dts: imx95: switch usb3 controller to flattened model Switch to use flattened model for USB3 controller. To enable USB controller with restricted DMA access range to work correctly, add a simple-bus to constrain the dma address. Note: This changes the USB controller compatible string from "fsl,imx95-dwc3" to "nxp,imx95-dwc3". This requires a kernel with CONFIG_USB_DWC3_IMX enabled; otherwise, the new DTB will not be compatible with older one. As i.MX95 is a new SoC and is still under development, it's acceptable at development early phase. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++------------ 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index d6c549c16047..305751046d66 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1867,37 +1867,6 @@ pmu@49252000 { }; }; - usb3: usb@4c010010 { - compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; - reg = <0x0 0x4c010010 0x0 0x04>, - <0x0 0x4c1f0000 0x0 0x20>; - clocks = <&scmi_clk IMX95_CLK_HSIO>, - <&scmi_clk IMX95_CLK_32K>; - clock-names = "hsio", "suspend"; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; - dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; - status = "disabled"; - - usb3_dwc3: usb@4c100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x4c100000 0x0 0x10000>; - clocks = <&scmi_clk IMX95_CLK_HSIO>, - <&scmi_clk IMX95_CLK_24M>, - <&scmi_clk IMX95_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - interrupts = ; - phys = <&usb3_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,gfladj-refclk-lpm-sel-quirk; - snps,parkmode-disable-ss-quirk; - iommus = <&smmu 0xe>; - }; - }; - hsio_blk_ctl: syscon@4c0100c0 { compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; reg = <0x0 0x4c0100c0 0x0 0x1>; @@ -1906,6 +1875,37 @@ hsio_blk_ctl: syscon@4c0100c0 { power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; }; + bus@4c100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges; + + usb3: usb3_dwc3: usb@4c100000 { + compatible = "nxp,imx95-dwc3", "nxp,imx8mp-dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>, + <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + reg-names = "core", "blkctl", "glue"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_24M>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "hsio", "bus_early", "ref", "suspend"; + interrupts = , + ; + interrupt-names = "dwc_usb3", "wakeup"; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + iommus = <&smmu 0xe>; + status = "disabled"; + }; + }; + usb3_phy: phy@4c1f0040 { compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; reg = <0x0 0x4c1f0040 0x0 0x40>, From b9fff21cbd480f47f04debbce6c14f48dd715f0a Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:29 +0800 Subject: [PATCH 050/131] arm64: dts: imx8mq-evk: add typec node The first USB port features a Type-C connector with dual data role and dual power role capabilities. Add the Type-C device node and enable the corresponding USB controller and phy node. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 59 ++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 1f07f1089026..5ea04703ddd7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include "imx8mq.dtsi" / { @@ -330,6 +331,35 @@ vgen6_reg: vgen6 { }; }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + orientation-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + }; + }; }; &lcdif { @@ -514,6 +544,28 @@ bluetooth { }; }; +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -666,6 +718,13 @@ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 From 43c17d862977492ea7c4a21e4c8f22582c603508 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 3 Jul 2026 17:27:31 +0200 Subject: [PATCH 051/131] arm64: dts: freescale: imx9-var-dart-sonata: fix Ethernet PHY configuration Fix the Ethernet PHY description on the DART-MX9 Sonata boards. The GPIO previously described as the PHY reset line is actually a board-level enable signal required by the PHY. Model it accordingly and remove the incorrect reset GPIO description from the PHY nodes. On i.MX91 and i.MX93 the signal is described as a fixed regulator, whereas the existing regulator description on i.MX95 is reused. Keeping the PHY enable asserted during boot ensures that Ethernet initialization completes successfully. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-var-dart-sonata.dts | 14 +++++++++++--- .../boot/dts/freescale/imx93-var-dart-sonata.dts | 14 +++++++++++--- .../boot/dts/freescale/imx95-var-dart-sonata.dts | 3 --- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts index 3f0fd321d95f..f7e32f9375f5 100644 --- a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts @@ -97,6 +97,17 @@ reg_rgb_sel: regulator-rgb-enable { enable-active-high; }; + reg_phy1_supply: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "SUPPLY_PHY1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -139,9 +150,6 @@ mdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <15000>; - reset-deassert-us = <100000>; leds { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts index 5513d3b148a2..1ca3ec8330d0 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts @@ -103,6 +103,17 @@ reg_vref_1v8: regulator-adc-vref { regulator-min-microvolt = <1800000>; }; + reg_phy1_supply: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "SUPPLY_PHY1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VDD_SD2_3V3"; @@ -180,9 +191,6 @@ mdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-assert-us = <15000>; - reset-deassert-us = <100000>; - reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; leds { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index 7a58ad38ffb4..ccf7e77016e4 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -346,9 +346,6 @@ &netc_emdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <100000>; leds { #address-cells = <1>; From c8cb123cde467117f69ae57f83bf02d374f81609 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:31 +0200 Subject: [PATCH 052/131] arm64: dts: imx8: Correct indentation and whitespace Correct spaces or mix of tabs+spaces into proper tab-indented lines and remove other whitespace violations. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Acked-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 2 +- .../dts/freescale/imx8mm-emtop-baseboard.dts | 301 +++++++++--------- .../dts/freescale/imx8mp-evk-flexcan2.dtso | 4 +- .../freescale/imx8mp-nitrogen-smarc-som.dtsi | 82 ++--- .../dts/freescale/imx8mq-librem5-devkit.dts | 4 +- 5 files changed, 196 insertions(+), 197 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 6fc82b5eb58c..681f24810d52 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -423,7 +423,7 @@ usb-hub@8 { refclk-frequency = <25000000>; reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; }; - + /* On Module Audio Codec */ sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts index 87fe3ebedb8d..b031a9308dda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts @@ -35,9 +35,9 @@ leds { pinctrl-0 = <&pinctrl_gpio_led>; led-1 { - label = "buzzer"; - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; + label = "buzzer"; + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; }; }; @@ -49,11 +49,11 @@ osc_can: clock-osc-can { }; reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "wm8904_supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "wm8904_supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; reg_wifi_vmmc: regulator-wifi-vmmc { @@ -68,13 +68,13 @@ reg_wifi_vmmc: regulator-wifi-vmmc { }; sound-wm8904 { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "wm8904-audio"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,routing = + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", @@ -82,45 +82,44 @@ sound-wm8904 { "Headphone Jack", "MICBIAS", "IN1L", "Headphone Jack"; - simple-audio-card,widgets = - "Microphone","Headphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; + simple-audio-card,widgets = "Microphone","Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; - dailink_master: simple-audio-card,codec { - sound-dai = <&wm8904>; - }; + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; }; sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; }; }; /* CAN BUS */ &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; - can: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_canbus>; - clocks = <&osc_can>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - spi-max-frequency = <10000000>; - }; + can: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_canbus>; + clocks = <&osc_can>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <10000000>; + }; }; &fec1 { @@ -177,29 +176,29 @@ rtc@32 { /* AUDIO */ &sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; }; &spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, - <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; - clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", - "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; }; /* USBOTG */ @@ -216,8 +215,8 @@ usb_hs_ep: endpoint { }; &usbotg2 { - dr_mode = "host"; - status = "okay"; + dr_mode = "host"; + status = "okay"; }; /* Wifi */ @@ -246,26 +245,26 @@ wifi: wifi@1 { /* SD-card */ &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; }; &iomuxc { pinctrl_canbus: canbusgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14 + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14 >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 @@ -274,125 +273,125 @@ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 pinctrl_usb_otg: usbotggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */ - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */ >; }; pinctrl_fec1: fec1grp { fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; }; pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; }; pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - >; + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc1_gpio: usdhc1-gpiogrp { fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */ - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */ - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */ >; }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso index f7d2674c45f7..d87119842027 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso @@ -7,9 +7,9 @@ /plugin/; &flexcan2 { - status = "okay"; /* can2 pin conflict with pdm */ + status = "okay"; /* can2 pin conflict with pdm */ }; &micfil { - status = "disabled"; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi index 5da0f1b3ed8a..347e1bc13b3a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi @@ -32,29 +32,29 @@ led-0 { }; reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; &A53_0 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &A53_1 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &A53_2 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &A53_3 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &i2c1 { @@ -220,7 +220,7 @@ &wdog1 { &iomuxc { pinctrl_gpio_led: gpioledgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 >; }; @@ -233,15 +233,15 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 pinctrl_i2c6: i2c6grp { fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 - MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 >; }; pinctrl_mcp23018: mcp23018grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 >; }; @@ -253,15 +253,15 @@ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0 pinctrl_uart2: uart2grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150 @@ -277,8 +277,8 @@ MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154 @@ -293,8 +293,8 @@ MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152 @@ -309,34 +309,34 @@ MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12 pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index aadaeef928bd..0c3f1b20b3d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -215,7 +215,7 @@ vibrator { compatible = "gpio-vibrator"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_haptic>; - enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; vcc-supply = <®_3v3_p>; }; @@ -856,7 +856,7 @@ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 >; }; From 972e858b01fbc724947f8ec825e0897e545b380f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:32 +0200 Subject: [PATCH 053/131] arm64: dts: s32g3: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Ghennadi Procopciuc Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 129d6ad8e5c6..24fa3057e929 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -553,22 +553,22 @@ usbmisc: usbmisc@44064200 { reg = <0x44064200 0x200>; }; - usbotg: usb@44064000 { - compatible = "nxp,s32g3-usb", "nxp,s32g2-usb"; - reg = <0x44064000 0x200>; - interrupt-parent = <&gic>; - interrupts = , /* OTG Core */ - ; /* OTG Wakeup */ - clocks = <&clks 94>, <&clks 95>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x3>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - phy_type = "ulpi"; - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "disabled"; - }; + usbotg: usb@44064000 { + compatible = "nxp,s32g3-usb", "nxp,s32g2-usb"; + reg = <0x44064000 0x200>; + interrupt-parent = <&gic>; + interrupts = , /* OTG Core */ + ; /* OTG Wakeup */ + clocks = <&clks 94>, <&clks 95>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x3>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + phy_type = "ulpi"; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "disabled"; + }; spi0: spi@401d4000 { compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; From 3d04a8aa8e7a274b2ec2218d4e863b3befcdc64e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jul 2026 08:51:47 +0200 Subject: [PATCH 054/131] arm64: dts: imx93-tqma9352-mba93xxla: Add LVDS overlay Add the overlay for the Tianma TM070JVHG33 LVDS display. Reviewed-by: Frank Li Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...3-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso | 38 +++++++++++++++++++ .../freescale/imx93-tqma9352-mba93xxla.dts | 21 ++++++++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 01d4ddfde098..6f1dbd7dbab6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -642,8 +642,10 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb +imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..4cb2d08b671e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds { + status = "okay"; +}; + +&display { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <477400000>; + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&tpm5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index a78bbc46c59b..914efa9b1c22 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -73,6 +73,23 @@ clk_dp: clk-dp { clock-frequency = <26000000>; }; + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -534,6 +551,10 @@ &lpuart8 { status = "okay"; }; +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + &pcf85063 { /* RTC_EVENT# from SoM is connected on mainboard */ pinctrl-names = "default"; From 2b73b844564e4099fc43c4bbdea0c7abd65fae5c Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jul 2026 08:51:48 +0200 Subject: [PATCH 055/131] arm64: dts: imx93-tqma9352-mba93xxca: Add LVDS overlay Add the overlay for the Tianma TM070JVHG33 LVDS display. Reviewed-by: Frank Li Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ .../freescale/imx93-tqma9352-mba93xxca.dts | 21 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6f1dbd7dbab6..cf802b6f0611 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -642,9 +642,11 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb +imx93-tqma9352-mba93xxca-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxca.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 9108181e6592..39a8742de1da 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -67,6 +67,23 @@ backlight_lvds: backlight { status = "disabled"; }; + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + fan0: pwm-fan { compatible = "pwm-fan"; pinctrl-names = "default"; @@ -571,6 +588,10 @@ &lpuart8 { status = "okay"; }; +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + &pcf85063 { /* RTC_EVENT# from SoM is connected on mainboard */ pinctrl-names = "default"; From fcf306c5f504e5dc4e25a0e81beccf29a58af261 Mon Sep 17 00:00:00 2001 From: Martin Schmiedel Date: Tue, 7 Jul 2026 08:51:49 +0200 Subject: [PATCH 056/131] arm64: dts: imx93-tqma9352-mba93xxla-mini: Add LVDS overlay Add the overlay for the Tianma TM070JVHG33 LVDS display. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx93-tqma9352-mba93xxla-mini.dts | 45 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index cf802b6f0611..842c98a91bb7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -645,10 +645,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb imx93-tqma9352-mba93xxca-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxca.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo +imx93-tqma9352-mba93xxla-mini-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts index 4afd6b650d9d..0d553a8da713 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts @@ -58,6 +58,37 @@ aliases { spi5 = &lpspi6; }; + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm5 0 5000000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display>; + power-supply = <®_3v3>; + enable-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + iio-hwmon { compatible = "iio-hwmon"; io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; @@ -311,6 +342,10 @@ &lpuart8 { status = "okay"; }; +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + &pcf85063 { /* RTC_EVENT# from SoM is connected on mainboard */ pinctrl-names = "default"; @@ -375,6 +410,16 @@ &usdhc3 { }; &iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_display: displaygrp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + pinctrl_eqos: eqosgrp { fsl,pins = /* PD | FSEL_2 | DSE X4 */ , From 4b407eaff92dbac9f31a61040e40ef05a82eb3a5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jul 2026 11:41:25 +0200 Subject: [PATCH 057/131] arm64: dts: imx8mp: add missing #sound-dai-cells to xcvr This device is used for 'sound-dai' and needs #sound-dai-cells. dtbs_check raises a warning regarding sound_dai_property. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5ce2825182fd..9cf9f6f08654 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1599,6 +1599,7 @@ xcvr: xcvr@30cc0000 { <0x30cc0e00 0x080>; reg-names = "ram", "regs", "rxfifo", "txfifo"; + #sound-dai-cells = <0>; interrupts = /* XCVR IRQ 0 */ , /* XCVR IRQ 1 */ From b463d4de9d365690d44fac9b8136190332639de1 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 7 Jul 2026 10:55:42 +0200 Subject: [PATCH 058/131] arm64: dts: imx91-tqma9131-mba91xxca: USB phy adjustments Add samsung,picophy-pre-emp-curr-control and samsung,picophy-dc-vol-level-adjust using the same values as other TQ-Systems GmbH mainboards. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts index 5c430e6fca65..60d11a4573e3 100644 --- a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts @@ -518,6 +518,8 @@ &usbotg1 { adp-disable; usb-role-switch; disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; port { @@ -532,6 +534,8 @@ &usbotg2 { #address-cells = <1>; #size-cells = <0>; disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; hub_2_0: hub@1 { From 96927ebe2610849ebdd78635b2e63a7af7a94eae Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Tue, 7 Jul 2026 10:55:43 +0200 Subject: [PATCH 059/131] arm64: dts: imx91-tqma9131: move ele-reserved memory into 512MB range TQMa91 has a 512MiB RAM variant for which the edgelock memory location exceeds the valid memory area. Signed-off-by: Alexander Feilke Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi index c99d7bc16848..a8c79731eace 100644 --- a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi @@ -33,9 +33,9 @@ linux,cma { }; /* EdgeLock secure enclave */ - ele_reserved: ele-reserved@a4120000 { + ele_reserved: ele-reserved@94120000 { compatible = "shared-dma-pool"; - reg = <0 0xa4120000 0 0x100000>; + reg = <0 0x94120000 0 0x100000>; no-map; }; }; From e5f7c88d3ad8c617db4c8bc381001d272b02ca21 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 13 Jul 2026 11:22:46 +0900 Subject: [PATCH 060/131] arm64: dts: imx91-9x9-qsb: Add audio-related board muxes The board uses GPIO-controlled muxes to route shared signals between different functions. Add the audio-related mux states for: - selecting PDM or CAN1 - selecting SAI1 or M.2 - enabling the SAI1 audio path or not Signed-off-by: Chancel Liu Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-9x9-qsb.dts | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index ea8cf14e0bc6..4821ac312ab2 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -30,6 +30,55 @@ chosen { stdout-path = &lpuart1; }; + can_mux: mux-controller-0 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + }; + + sai1_mux: mux-controller-1 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pcal6524 18 GPIO_ACTIVE_HIGH>; + }; + + sai1_en_mux: mux-controller-2 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pcal6524 9 GPIO_ACTIVE_HIGH>; + }; + + pinctrl-gpiomux { + compatible = "pinctrl-multiplexer"; + + can_fun: can-grp { + mux-states = <&can_mux 1>; + }; + + m2_fun: m2-grp { + mux-states = <&sai1_mux 1>; + }; + + pdm_fun: pdm-grp { + mux-states = <&can_mux 0>; + }; + + sai1_disable: sai1-disable-grp { + mux-states = <&sai1_en_mux 1>; + }; + + sai1_enable: sai1-enable-grp { + mux-states = <&sai1_en_mux 0>; + }; + + sai1_fun: sai1-grp { + mux-states = <&sai1_mux 0>; + }; + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; From de6ed1fd9b97ed143b10de7064c6d30a9b545379 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 13 Jul 2026 11:22:47 +0900 Subject: [PATCH 061/131] arm64: dts: imx91-9x9-qsb: Add WM8524 sound card support Add WM8524 sound card support which connects to SAI1. Signed-off-by: Chancel Liu Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-9x9-qsb.dts | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 4821ac312ab2..089d999196d6 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -30,6 +30,18 @@ chosen { stdout-path = &lpuart1; }; + wm8524: audio-codec { + compatible = "wlf,wm8524"; + #sound-dai-cells = <0>; + wlf,mute-gpios = <&pcal6524 2 GPIO_ACTIVE_LOW>; + + port { + codec_ep: endpoint { + remote-endpoint = <&sai1_ep1>; + }; + }; + }; + can_mux: mux-controller-0 { compatible = "gpio-mux"; #mux-control-cells = <0>; @@ -110,6 +122,16 @@ linux,cma { linux,cma-default; }; }; + + sound-wm8524 { + compatible = "audio-graph-card2"; + label = "wm8524-audio"; + links = <&sai1_port1>; + widgets = "Line", "Line Out Jack"; + routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; }; &adc1 { @@ -186,6 +208,15 @@ MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x31e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX91_PAD_UART1_RXD__LPUART1_RX 0x31e @@ -433,6 +464,42 @@ &lpuart1 { status = "okay"; }; +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>, <&sai1_fun>, <&sai1_enable>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + fsl,sai-mclk-direction-output; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sai1_port1: port@1 { + reg = <1>; + playback-only; + + sai1_ep1: endpoint { + dai-format = "i2s"; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + bitclock-master; + frame-master; + mclk-fs = <256>; + system-clock-direction-out; + remote-endpoint = <&codec_ep>; + }; + }; + }; +}; + &usbotg1 { adp-disable; disable-over-current; From 25f7d6026e2549a73e529bef85c80579528ebb33 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 13 Jul 2026 11:22:48 +0900 Subject: [PATCH 062/131] arm64: dts: imx91-9x9-qsb: Add PDM microphone sound card support Add PDM microphone sound card support, configure the pinmux. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Chancel Liu Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-9x9-qsb.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 089d999196d6..044b37fcc0ba 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -42,6 +42,18 @@ codec_ep: endpoint { }; }; + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <4>; + + port { + dmic_ep: endpoint { + remote-endpoint = <&micfil_ep>; + }; + }; + }; + can_mux: mux-controller-0 { compatible = "gpio-mux"; #mux-control-cells = <0>; @@ -123,6 +135,12 @@ linux,cma { }; }; + sound-micfil { + compatible = "audio-graph-card2"; + label = "micfil-audio"; + links = <&micfil_port>; + }; + sound-wm8524 { compatible = "audio-graph-card2"; label = "wm8524-audio"; @@ -202,6 +220,14 @@ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e @@ -464,6 +490,24 @@ &lpuart1 { status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; + + micfil_port: port { + capture-only; + + micfil_ep: endpoint { + remote-endpoint = <&dmic_ep>; + }; + }; +}; + &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; From ed93dafad1121ad5c8e48185789e4eee551a0434 Mon Sep 17 00:00:00 2001 From: Esben Haabendal Date: Sat, 11 Jul 2026 12:18:42 +0200 Subject: [PATCH 063/131] arm64: dts: imx8mq: Add DCSS node Add node for iMX8MQ Display Controller Subsystem. Reviewed-by: Lucas Stach Signed-off-by: Esben Haabendal Acked-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index e60872aeeb49..d75710cdb5b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1598,6 +1598,29 @@ aips4: bus@32c00000 { /* AIPS4 */ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + dcss: display-controller@32e00000 { + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; From df9b9d59586f3d8bdeba5b3c7b7ea68cb0302fb7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Oct 2025 16:01:28 -0400 Subject: [PATCH 064/131] dt-bindings: input: fsl,scu-key: Add compatible string fsl,imx8qm-sc-key Add compatible string fsl,imx8qm-sc-key for i.MX8QM and fallback to fsl,imx-sc-key. Acked-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/input/fsl,scu-key.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml index 29921aab9d97..2566cffc252d 100644 --- a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml +++ b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml @@ -18,7 +18,9 @@ allOf: properties: compatible: items: - - const: fsl,imx8qxp-sc-key + - enum: + - fsl,imx8qm-sc-key + - fsl,imx8qxp-sc-key - const: fsl,imx-sc-key linux,keycodes: From f9c8aaffc782cae682d3606037f2d02fb4e0035a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Oct 2025 16:01:29 -0400 Subject: [PATCH 065/131] arm64: dts: imx8qm: add scu power key support Add scu power key node. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index ae7de9f99055..9f9b34153ad5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -330,6 +331,12 @@ clk: clock-controller { #clock-cells = <2>; }; + scu_key: keys { + compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key"; + linux,keycodes = ; + wakeup-source; + }; + iomuxc: pinctrl { compatible = "fsl,imx8qm-iomuxc"; }; From 949e5a6a8f349ff3098f4dc2aa3483723e4209c1 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 14 Jul 2026 18:33:51 +0200 Subject: [PATCH 066/131] dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards Add DT compatible strings for Variscite DART-MX8MM SoM and Variscite development carrier Board. Acked-by: Krzysztof Kozlowski Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f96f3d31dac1..7b57a6ee1b50 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1064,6 +1064,12 @@ properties: - const: solidrun,imx8mm-sr-som - const: fsl,imx8mm + - description: Variscite DART-MX8MM based boards + items: + - const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board + - const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony From 5297deef08bc3ddc1a27b3518b770dbc3a14da81 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 14 Jul 2026 18:33:52 +0200 Subject: [PATCH 067/131] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI Add device tree support for the Variscite DART-MX8MM system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8M Mini MPU processor - Up to 4GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-var-dart.dtsi | 558 ++++++++++++++++++ 1 file changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file mode 100644 index 000000000000..2324063f8fd9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX8M-MINI + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "Variscite DART-MX8M-MINI Module"; + compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + phy-supply = <®_eth_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&mu { + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* BT module */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_fec1_sleep: fec1sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 + MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 + MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 + MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 + MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 + MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x140 + >; + }; + + pinctrl_reg_eth_phy: regeth-phygrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 + >; + }; +}; From 770aba46ea0fad62631848d4cf2c0c8a5fac7ba5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 14 Jul 2026 18:33:53 +0200 Subject: [PATCH 068/131] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-MINI system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-var-dart-sonata.dts | 516 ++++++++++++++++++ 2 files changed, 517 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 842c98a91bb7..be3c858f1eeb 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file mode 100644 index 000000000000..57d29a5c3821 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX8M-MINI + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8mm-var-dart.dtsi" + +/ { + model = "Variscite DART-MX8M-MINI on Sonata-Board"; + compatible = "variscite,var-dart-mx8mm-sonata", + "variscite,var-dart-mx8mm", + "fsl,imx8mm"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-emmc { + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + label = "eMMC"; + linux,default-trigger = "mmc2"; + }; + }; + + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vmmc_usdhc2>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; + + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&clk40m>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + extcon_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6408>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +/* Console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + wakeup-source; + status = "okay"; +}; + +/* Header */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + disable-over-current; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13 + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + + pinctrl_pca6408: pca6408grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c6 + >; + }; + + pinctrl_pwm: pwmgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; + + pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1 + >; + }; +}; From 4185d10a60d617c5ba7dae4cc56498621c11cd00 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 14 Jul 2026 16:31:52 +0200 Subject: [PATCH 069/131] arm64: dts: add tqma9596la-mba95xxca This adds support for TQMa95xxLA modules, designed to be soldered on a carrier board. MBa95xxCA is a carrier reference board / starter kit design. There is a common device tree for all variants with e.g. reduced CPU core / feature count. Enable the external accessible PCIe controllers as host, add clocking and reset GPIO. While at it, add hogs for GPIO lines from the M.2 slots until M.2 connector driver is available. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx95-tqma9596la-mba95xxca.dts | 958 ++++++++++++++++++ .../boot/dts/freescale/imx95-tqma9596la.dtsi | 278 +++++ 3 files changed, 1237 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index be3c858f1eeb..9a864990d7e3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -673,6 +673,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596la-mba95xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts new file mode 100644 index 000000000000..1d745d66997c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "imx95-tqma9596la.dtsi" + +/ { + model = "TQ-Systems i.MX95 TQMa95xxLA on MBa95xxCA"; + compatible = "tq,imx95-tqma9596la-mba95xxca", "tq,imx95-tqma9596la", "fsl,imx95"; + chassis-type = "embedded"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + ethernet2 = &enetc_port2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &scmi_bbm; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &flexspi1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&tpm5 2 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + clk_eth: clk-eth { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + /* + * TODO: gate is disabled for now and GPIO are hogged + * ENETC driver switches the clock far too late for ENETC2 + SFP + */ + clk_eth_gate: clk-eth-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&expander2 0 GPIO_ACTIVE_HIGH>; + clocks = <&clk_eth>; + #clock-cells = <0>; + status = "disabled"; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-b { + label = "BUTTON_B#"; + linux,code = ; + gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + reg_v1v8_mb: regulator-v1v8-mb { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_MB"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_v3v3_mb: regulator-v3v3-mb { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3a_10g: regulator-3v3a-10g { + compatible = "regulator-fixed"; + regulator-name = "3V3A_10G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + enable-active-high; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_12v0>; + /* + * emc2305 fan driver lacks support for fan-supply, so + * alway enable it for now. + * Remove this line once support is added + */ + regulator-always-on; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "LCD_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* USB NC limitations, RM 162.1.2 VBUS limitations */ + reg_vbus_usb3: regulator-vbus-usb3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "USB3_VBUS"; + gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + }; + + sfp_xfi: sfp-xfi { + compatible = "sff,sfp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sfp>; + i2c-bus = <&lpi2c7>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander1 3 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + los-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-codec = <&tlv320aic3x04>; + audio-cpu = <&sai3>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; + + wifi-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <®_v3v3_mb>; + vpcie1v8-supply = <®_v1v8_mb>; + i2c-parent = <&lpi2c2>; + w-disable1-gpios = <&expander2 9 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&expander2 10 GPIO_ACTIVE_LOW>; + /* UART_WAKE is connected to SM */ + /* SDIO_WAKE is connected to SM */ + sdio-reset-gpios = <&expander3 2 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +/* No support for XFI yet */ +&enetc_port2 { + sfp = <&sfp_xfi>; + phy-mode = "10gbase-r"; + clocks = <&clk_eth>; + managed = "in-band-status"; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&lpi2c2 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + reset-gpios = <&expander1 14 GPIO_ACTIVE_LOW>; + iov-supply = <®_v3v3_mb>; + ldoin-supply = <®_v3v3_mb>; + }; + + sensor_mb: temperature-sensor@1e { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1e>; + }; + + fan_controller: fan-controller@2f { + compatible = "microchip,emc2301", "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + status = "okay"; + + fan: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + fan-supply = <®_pwm_fan>; + }; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio2>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "X9"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom_mb: eeprom@56 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x56>; + pagesize = <16>; + vcc-supply = <®_v3v3_mb>; + }; + + pcieclk: clock-generator@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; + + /* D39 IN/OUT 3V3 */ + expander1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + vcc-supply = <®_v3v3_mb>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + gpio-line-names = + /* 00 */ "BUTTON_B#", "CAM0_SYNC_3V3", + /* 02 */ "CAM1_SYNC_3V3", "SFP_MOD_ABS", + /* 04 */ "DIG_IN1", "DIG_IN2", + /* 06 */ "DIG_IN3", "DIG_IN4", + /* 08 */ "DIG_OUT_1_2_STATE", "DIG_OUT_3_4_STATE", + /* 10 */ "DIG_OUT_1_EN", "DIG_OUT_2_EN", + /* 12 */ "DIG_OUT_3_EN", "DIG_OUT_4_EN", + /* 14 */ "AUDIO_RST#", "12V_EN"; + }; + + /* D40 OUT 3V3 */ + expander2: gpio@75 { + compatible = "ti,tca9539"; + reg = <0x75>; + vcc-supply = <®_v3v3_mb>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + /* 00 */ "ETH10G_REFCLK_EN", "ETH10G_REFCLK_RST#", + /* 02 */ "SFP_TX_DIS", "USB3_RESET#", + /* 04 */ "USB2_RESET#", "LCD_RESET#", + /* 06 */ "LCD_BLT_EN", "LCD_PWR_EN", + /* 08 */ "M2_KEYE_PERST#", "M2_KEYE_WDISABLE1#", + /* 10 */ "M2_KEYE_WDISABLE2#", "M2_KEYB_PERST#", + /* 12 */ "M2_KEYB_WDISABLE1#", "USER_LED1", + /* 14 */ "USER_LED2", "3V3A_10G_EN"; + + eth10g-refclk-en-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ETH10G_REFCLK_EN"; + }; + + eth10g-refclk-rst-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "ETH10G_REFCLK_RST#"; + }; + + m2-keyb-wdisable1-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_WDISABLE1#"; + }; + }; + + /* D41 OUT 1V8 */ + expander3: gpio@76 { + compatible = "ti,tca9539"; + reg = <0x76>; + vcc-supply = <®_v1v8_mb>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + /* 00 */ "ENET1_RESET#", "ENET2_RESET#", + /* 02 */ "M2_KEYE_SDIO_RST#", "M2_KEYE_DEV_WLAN_WAKE#", + /* 04 */ "M2_KEYE_DEV_BT_WAKE", "M2_KEYB_W_DISABLE2#", + /* 06 */ "M2_KEYB_RST#", "M2_KEYB_FULL_CARD_PWR_OFF#", + /* 08 */ "M2_KEYB_DPR", "CAM0_PWR#", + /* 10 */ "CAM1_PWR#", "CAM0_RST#", + /* 12 */ "CAM1_RST#", "CAM0_TRIGGER", + /* 14 */ "CAM1_TRIGGER", "FAN_PWR_EN"; + + /* vendor defined pin 42 */ + m2-keye-dev_wlan-wake-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + input; + line-name = "M2_KEYE_DEV_WLAN_WAKE#"; + }; + + /* vendor defined pin 40 */ + m2-keye-dev_bt-wake-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "M2_KEYE_DEV_BT_WAKE#"; + }; + + m2-keyb-wdisable2-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_WDISABLE2#"; + }; + + m2-keyb-rst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_RST#"; + }; + + m2-keyb-full-card-pwr-off-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_FULL_CARD_PWR_OFF#"; + }; + }; +}; + +/* X4 + SFP */ +&lpi2c7 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c7>; + pinctrl-1 = <&pinctrl_lpi2c7_recovery>; + scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* TODO: 0x19: retimer */ + + /* 0x50 / 0x51: SFP EEPROM */ +}; + +/* X4 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>; + /* max 30 MHz as per datasheet, without SCK loopback via pad (LPSPI_CFGR1[SAMPLE]) */ + status = "okay"; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart2 { + /* SM */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "reserved"; +}; + +&lpuart5 { + /* X16 M.2 KEY E */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&lpuart7 { + /* X5 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; + status = "okay"; +}; + +&lpuart8 { + /* X15 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart8>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + /* IRQ pin is AON GPIO, not usable */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&expander3 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy1>; + reset-gpios = <&expander3 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio4>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +/* X16 M2 / E-Key mPCIe */ +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcieclk 1>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; + reset-gpios = <&expander2 8 GPIO_ACTIVE_LOW>; + /* Not supported on REV.0100 */ + /* supports-clkreq; */ + status = "okay"; +}; + +/* X17 M2 / B-Key PCIe */ +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcieclk 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; + reset-gpios = <&expander2 11 GPIO_ACTIVE_LOW>; + /* Not supported on REV.0100 */ + /* supports-clkreq; */ + status = "okay"; +}; + +®_sdvmmc { + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + a55-thermal { + trips { + cpu_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + cpu_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_active0>; + cooling-device = <&fan 0 2>; + }; + + map2 { + trip = <&cpu_active1>; + cooling-device = <&fan 3 5>; + }; + + map3 { + trip = <&cpu_active2>; + cooling-device = <&fan 6 10>; + }; + }; + }; +}; + +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; + status = "okay"; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usb2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + vdd-supply = <®_v3v3_mb>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_1: hub@1 { + compatible = "usb424,2514"; + reg = <1>; + reset-gpios = <&expander2 4 GPIO_ACTIVE_LOW>; + vdd-supply = <®_v3v3_mb>; + vdda-supply = <®_v3v3_mb>; + }; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + vdd-supply = <®_v3v3_mb>; + }; +}; + +&usb3_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + vbus-supply = <®_vbus_usb3>; + status = "okay"; +}; + +/* X7 µSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_sdvmmc>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_enetc0: enetc0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_ethphy1: ethphy1grp { + fsl,pins = ; + }; + + pinctrl_expander1: expander1grp { + fsl,pins = ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c7_recovery: lpi2c7recoverygrp { + fsl,pins = , + ; + }; + + pinctrl_lpspi4: lpspi4grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart8: lpuart8grp { + fsl,pins = , + , + ; + }; + + pinctrl_emdio: emdiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = ; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_retimer: retimergrp { + fsl,pins = ; + }; + + pinctrl_sfp: sfpgrp { + fsl,pins = , + ; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = ; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = ; + }; + + pinctrl_typec: typecgrp { + fsl,pins = ; + }; + + pinctrl_usb3: usb3grp { + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi new file mode 100644 index 000000000000..aa2756c14e46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx95.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, size : 2048 MiB DRAM + * should be corrected by bootloader + */ + reg = <0 0x80000000 0 0x80000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdvmmc: regulator-sdvmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdvmmc>; + regulator-name = "SD_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + /* can be enabled by mainboard with SD-Card support */ + status = "disabled"; + }; +}; + +&adc1 { + vref-supply = <®_1v8>; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +/* System Manager */ +&gpio1 { + status = "reserved"; +}; + +/* System Manager */ +&lpi2c1 { + status = "reserved"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + m24c64: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; + + /* protectable identification memory (part of M24C64-D @54) */ + eeprom@5c { + compatible = "atmel,24c64d-wl"; + reg = <0x5c>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; + + imu@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + }; +}; + +&thermal_zones { + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + trip = <&pf5301_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = , + , + , + , + , + /* SION to allow clock loopback from pad */ + , + ; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , + ; + }; + + pinctrl_sdvmmc: sdvmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; +}; From 259bd77e9f635e058c045a880427570e534c8737 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:31 +0200 Subject: [PATCH 070/131] arm64: dts: freescale: imx8mn-var-som: Move UART4 description to Symphony The VAR-SOM-MX8MN module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART. Move the UART4 node from the SOM device tree to the imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-var-som-symphony.dts | 18 ++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 3434b189fa58..b07e71d3adee 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -15,6 +15,10 @@ / { model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; + chosen { + stdout-path = &uart4; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -171,6 +175,13 @@ &uart3 { status = "okay"; }; +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -234,4 +245,11 @@ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 38ef9e4fdf07..32f101ef2850 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -11,10 +11,6 @@ / { model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; - chosen { - stdout-path = &uart4; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x40000000>; @@ -274,13 +270,6 @@ &uart2 { status = "okay"; }; -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - &usbotg1 { dr_mode = "otg"; usb-role-switch; @@ -432,13 +421,6 @@ MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 From bc5217a4e354ebe0a2f52d2188ef952fd630defc Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:32 +0200 Subject: [PATCH 071/131] arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier boards The VAR-SOM-MX8MN module does not provide an onboard SD card slot. USDHC2 is routed to the SD card slot on the carrier boards. Move the USDHC2 node and pinctrl configuration from the SOM device tree to imx8mn-var-som-symphony.dts and imx8mn-rve-gateway.dts, keeping the SOM dtsi limited to hardware present on the module itself. Add the required off-on-delay-us property for the USDHC2 regulator on the Symphony carrier board. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-rve-gateway.dts | 47 ++++++++++++++- .../dts/freescale/imx8mn-var-som-symphony.dts | 57 +++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 56 ------------------ 3 files changed, 102 insertions(+), 58 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts index ea1855171fb0..056ea2f9e963 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts @@ -207,8 +207,16 @@ &usbotg1 { /* SD interface on expansion connector. */ &usdhc2 { - vmmc-supply = <®_3p3v>; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; }; &iomuxc { @@ -276,10 +284,45 @@ MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x00000156 /* B */ >; }; - /* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */ pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 >; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index b07e71d3adee..7308613a48b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -28,6 +28,7 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { regulator-max-microvolt = <3300000>; gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; enable-active-high; + off-on-delay-us = <20000>; }; gpio-keys { @@ -200,6 +201,20 @@ usb1_drd_sw: endpoint { }; }; +/* SD */ +&usdhc2 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + &iomuxc { pinctrl_captouch: captouchgrp { fsl,pins = < @@ -252,4 +267,46 @@ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 >; }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 32f101ef2850..e1d2e2a72e1f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -295,20 +295,6 @@ brcmf: wifi@1 { }; }; -/* SD */ -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; @@ -454,48 +440,6 @@ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 From 763a267bc2ccf637bd0f35492ca1e6ab6c9dc13b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:33 +0200 Subject: [PATCH 072/131] arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables Reformat the fsl,pins tables in the i.MX8MN VAR-SOM device tree to use consistent column alignment across all pinctrl groups. Align the entries to match the formatting already used in the pinctrl_fec1 group, which contains the longest pin definitions, for improved readability and consistency. No functional changes intended. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 126 +++++++++--------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index e1d2e2a72e1f..71a2f0866822 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -368,129 +368,129 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 >; }; pinctrl_reg_eth_phy: regethphygrp { fsl,pins = < - MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 >; }; pinctrl_restouch: restouchgrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; From a6c8d4f9c2db6254681d78ec93f5bd944a0cf89d Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:34 +0200 Subject: [PATCH 073/131] arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY. Add the PHY VDDIO supply regulator and adjust reset timings. The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring. Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony). Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-var-som-symphony.dts | 20 ++++++++++++++++++- .../boot/dts/freescale/imx8mn-var-som.dtsi | 20 ++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 7308613a48b2..520aff23e587 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include #include #include "imx8mn-var-som.dtsi" @@ -74,7 +75,24 @@ reg_per_3v3: regulator-peripheral-3v3 { }; ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; &i2c2 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 71a2f0866822..09146ab76385 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -35,6 +35,13 @@ reg_3v3_fixed: regulator-3v3-fixed { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &A53_0 { @@ -96,24 +103,19 @@ &fec1 { phy-mode = "rgmii"; phy-handle = <ðphy>; phy-supply = <®_eth_phy>; - fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; - ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */ + ethphy: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - /* - * Deassert delay: - * ADIN1300 requires 5ms. - * AR8033 requires 1ms. - */ - reset-deassert-us = <20000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; }; }; }; @@ -342,7 +344,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159 + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 >; }; From ed99c5c5c5e88f31ed8de6eff9c3da2ca188d947 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:35 +0200 Subject: [PATCH 074/131] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec The VAR-SOM-MX8MN can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications. Add the WM8904 device to the appropriate I2C bus, enable the SAI peripheral, and introduce the sound node to expose the sound card to the system. Add I2C3 recovery gpio properties. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 98 ++++++++++++++++++- 1 file changed, 95 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 09146ab76385..e2e04ad2fbb6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -16,6 +16,14 @@ memory@40000000 { reg = <0x0 0x40000000 0 0x40000000>; }; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_eth_phy: regulator-eth-phy { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; }; &A53_0 { @@ -246,18 +282,55 @@ eeprom_som: eeprom@52 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - /* TODO: configure audio, as of now just put a placeholder */ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - status = "disabled"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MN_CLK_SAI5_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -375,6 +448,13 @@ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -400,6 +480,18 @@ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 From 42a066c24cc673b4317acb382597c0a3230b9f6f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:36 +0200 Subject: [PATCH 075/131] arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MN VAR-SOM. The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO. Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index e2e04ad2fbb6..ac22dd3e6542 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -11,6 +11,13 @@ / { model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x40000000>; @@ -130,6 +137,19 @@ touchscreen@0 { ti,keep-vref-on; wakeup-source; }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + clocks = <&clk40m>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <20000000>; + microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + }; }; &fec1 { @@ -391,6 +411,13 @@ &wdog1 { }; &iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c0 + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 From 040bf14c102570fee953fc2124737a988c3fb6a6 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:37 +0200 Subject: [PATCH 076/131] arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts The VAR-SOM-MX8MN currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART. Move the wireless module configuration out of the base imx8mn-var-som.dtsi and provide dedicated variant includes. The IW61x configuration is moved to imx8mn-var-som-wifi-bt-iw61x.dtsi and used by the Symphony evaluation board device tree. A separate imx8mn-var-som-wifi-brcm-legacy.dtsi include is added to keep the configuration for the legacy Broadcom SDIO WiFi module used on earlier SOM revisions. To preserve compatibility with older SOM revisions, add a separate imx8mn-var-som-symphony-legacy.dtb, which disables the IW61x setup and applies the Broadcom-specific configuration. The Broadcom-based SOM revision is no longer in production, but support is kept for existing users. This keeps the VAR-SOM-MX8MN support aligned with the existing VAR-SOM-MX8MM implementation. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-rve-gateway.dts | 1 + .../imx8mn-var-som-symphony-legacy.dts | 19 ++++++++ .../dts/freescale/imx8mn-var-som-symphony.dts | 1 + .../imx8mn-var-som-wifi-brcm-legacy.dtsi | 19 ++++++++ .../imx8mn-var-som-wifi-bt-iw61x.dtsi | 46 +++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 8 ---- 7 files changed, 87 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9a864990d7e3..7021c2db54df 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -207,6 +207,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb DTC_FLAGS_imx8mn-solidsense-n8-compact += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts index 056ea2f9e963..d9981d9a7362 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts @@ -7,6 +7,7 @@ #include #include "imx8mn-var-som.dtsi" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" / { model = "RVE gateway"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file mode 100644 index 000000000000..5998ebcef474 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +#include "imx8mn-var-som-symphony.dts" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" + +&bluetooth_iw61x { + status = "disabled"; +}; + +&iw61x_pwrseq { + status = "disabled"; +}; + +&usdhc1 { + /delete-property/ mmc-pwrseq; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 520aff23e587..53130b521b5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -11,6 +11,7 @@ #include #include #include "imx8mn-var-som.dtsi" +#include "imx8mn-var-som-wifi-bt-iw61x.dtsi" / { model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi new file mode 100644 index 000000000000..9ca2038943d4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi new file mode 100644 index 000000000000..9ec341ed57d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/ { + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + mmc-pwrseq = <&iw61x_pwrseq>; +}; + +&iomuxc { + pinctrl_bt: bluetoothgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x140 + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index ac22dd3e6542..5d8cd8c13633 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -371,10 +371,7 @@ &usbotg1 { status = "okay"; }; -/* WIFI */ &usdhc1 { - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; @@ -383,11 +380,6 @@ &usdhc1 { non-removable; keep-power-in-suspend; status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; }; /* eMMC */ From 0504e4d12fd3c3b5062b49086ce17a2743c60658 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:38 +0200 Subject: [PATCH 077/131] arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node The VAR-SOM-MX8MN module does not provide an onboard USB connector. The complete USB OTG description, including the Type-C role switch configuration, is already provided by the Symphony carrier board device tree. Remove the duplicate USB OTG node from the SOM dtsi to avoid describing the same hardware in two places. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 5d8cd8c13633..7a4c7455a162 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -365,12 +365,6 @@ &uart2 { status = "okay"; }; -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; From 5580a6278c5ce77a8492d76571929321894934f3 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:39 +0200 Subject: [PATCH 078/131] arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface Enable the FlexSPI controller on the VAR-SOM-MX8MN and add the corresponding pin multiplexing configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 7a4c7455a162..0bc9fb44069e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -176,6 +176,12 @@ ethphy: ethernet-phy@4 { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -454,6 +460,17 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 From 8576126c7ccf632c8edeeb69f57f17ee5e125de5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:40 +0200 Subject: [PATCH 079/131] arm64: dts: imx8mn-var-som-symphony: Add TPM2 support Add support for the TPM2 device on the VAR-SOM Symphony carrier board. The ST33K TPM2 is connected over I2C, and A PCA6408 GPIO expander is used to control the reset signal required to release the TPM from reset. Add the PCA6408 GPIO expander and the ST33K TPM2 device node. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 53130b521b5b..7d016ed5e911 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -160,6 +160,20 @@ typec1_dr_sw: endpoint { }; &i2c3 { + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5406"; From ab80a67f5cdb42797d0a92d7951242291bb97f3a Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:41 +0200 Subject: [PATCH 080/131] arm64: dts: imx8mn-var-som-symphony: Enable I2C4 Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-var-som-symphony.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 7d016ed5e911..4898018f030c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -195,6 +195,16 @@ rtc@68 { }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -262,6 +272,20 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 From e2e47af10c90f4c5eaf415fa98f6ca2f33ef30da Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:42 +0200 Subject: [PATCH 081/131] arm64: dts: imx8mn-var-som-symphony: add wakeup sources Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 4898018f030c..c98dca8e7889 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -40,18 +40,21 @@ key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; }; @@ -187,6 +190,7 @@ ft5x06_ts: touchscreen@38 { touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { From 164cb0d61a3fd0d9376005aae3b112a3dbba2e07 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:43 +0200 Subject: [PATCH 082/131] arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index c98dca8e7889..ddd4651b35d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -168,6 +168,14 @@ pca6408: gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e { From 8a6c812cd5a721aa0af9b7dd35b43d12c831349e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:44 +0200 Subject: [PATCH 083/131] arm64: dts: imx8mn-var-som-symphony: enable PWM1 Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index ddd4651b35d7..2afb5b438b68 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -217,6 +217,12 @@ &i2c4 { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -310,6 +316,12 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 From be578db51f789f0b88ec4f5e5f78e232b42c6b15 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:45 +0200 Subject: [PATCH 084/131] arm64: dts: imx8mn-var-som-symphony: Disable internal RTC Disable the internal SNVS RTC on the Symphony carrier board and use the external DS1337 RTC instead. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 2afb5b438b68..364127257309 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -223,6 +223,10 @@ &pwm1 { status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; From 4a3f4d08f53242dd6524285fd37c01886aacd0bc Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 17 Jul 2026 12:29:37 +0200 Subject: [PATCH 085/131] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX8 QuadMax Boards Add DT compatible strings for Variscite VAR-SOM-MX8 QuadMax SoM and Variscite Symphony development carrier Board. Acked-by: Krzysztof Kozlowski Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7b57a6ee1b50..52f08bc1f8ea 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1393,6 +1393,12 @@ properties: - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - const: fsl,imx8qm + - description: i.MX8QM Variscite VAR-SOM-MX8 based Boards + items: + - const: variscite,var-som-imx8qm-symphony + - const: variscite,var-som-imx8qm + - const: fsl,imx8qm + - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules items: - enum: From 868ced4df4ef1169802c400a685820f2f1fc059b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 17 Jul 2026 12:29:38 +0200 Subject: [PATCH 086/131] arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMax Add device tree support for the Variscite VAR-SOM-MX8 QuadMax system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8 QuadMax MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-var-som.dtsi | 531 ++++++++++++++++++ 1 file changed, 531 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi new file mode 100644 index 000000000000..b11da10c5ae3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite VAR-SOM-MX8 + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8qm.dtsi" + +/ { + model = "Variscite i.MX8QM VAR-SOM-MX8 Module"; + compatible = "variscite,var-som-imx8qm", "fsl,imx8qm"; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_audio_supply: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: memory@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table0: memory@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdev2vring0: memory@90100000 { + reg = <0 0x90100000 0 0x8000>; + no-map; + }; + + vdev2vring1: memory@90108000 { + reg = <0 0x90108000 0 0x8000>; + no-map; + }; + + vdev3vring0: memory@90110000 { + reg = <0 0x90110000 0 0x8000>; + no-map; + }; + + vdev3vring1: memory@90118000 { + reg = <0 0x90118000 0 0x8000>; + no-map; + }; + + rsc_table1: memory@901ff000 { + reg = <0 0x901ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: memory@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + dsp_reserved: memory@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + + dsp_vdev0vring0: memory@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: memory@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: memory@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + /* VAR-SOM-MX8QM doesn't have 1GB variant */ + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&esai0>; + }; + }; +}; + +&acm { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&gpio0_mipi_csi0 { + status = "disabled"; +}; + +&gpio0_mipi_csi1 { + status = "disabled"; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +/* Bluetooth */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + uart-has-rtscts; + status = "okay"; +}; + +&mu_m0{ + status = "okay"; +}; + +&mu1_m0{ + status = "okay"; +}; + +&mu2_m0{ + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* WIFI */ +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041 + IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041 + IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041 + IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* GPIOs used by user space WiFi init */ + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021 + IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; +}; From a40fdbf706cc643671e41b9ac2f9ec3a832e769e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 17 Jul 2026 12:29:39 +0200 Subject: [PATCH 087/131] arm64: dts: imx8qm-var-som: Add support for Variscite Symphony board Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-MX8 QuadMax system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals - PCIE support Link: https://variscite.com/carrier-boards/symphony-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qm-var-som-symphony.dts | 490 ++++++++++++++++++ 2 files changed, 491 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7021c2db54df..7d77856d3e7d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -543,6 +543,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-tqma8qm-mba8x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-var-som-symphony.dtb imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts new file mode 100644 index 000000000000..c7d3073b4041 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Symphony carrier board for VAR-SOM-MX8 QuadMax + * + * Link: https://variscite.com/carrier-boards/symphony-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8qm-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8 on Symphony evaluation board"; + compatible = "variscite,var-som-imx8qm-symphony", + "variscite,var-som-imx8qm", "fsl,imx8qm"; + chosen { + stdout-path = &lpuart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-heartbeat { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + vin-supply = <®_vselect>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio0 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vselect: regulator-vselect { + compatible = "regulator-fixed"; + regulator-name = "reg_vselect"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&pca9534 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&fec1 { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + vddio-supply = <®_phy_vddio>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&hsio_phy { + fsl,hsio-cfg = "pciea-pcieb-sata"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + }; + + /* USB Type-C Controller */ + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + + /* Capacitive touch */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + reg = <0x38>; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&lsio_gpio0>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&lpspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi1>; + cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* console */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +/* header */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&pca9534 { + usb3-signal-route-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "usb3_signal_route"; + }; +}; + +&pciea{ + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + status = "okay"; +}; + +&pciea_port0 { + reset-gpios = <&pca6408 1 GPIO_ACTIVE_LOW>; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usbphy1 { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA 0xc6000020 + IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL 0xc6000020 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + IMX8QM_ENET1_MDC_DMA_I2C4_SCL 0xc6000020 + IMX8QM_ENET1_MDIO_DMA_I2C4_SDA 0xc6000020 + >; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins = < + IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004c + IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004c + IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004c + IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021 + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + >; + }; + + pinctrl_usbotg1: otg1grp { + fsl,pins = < + IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000048 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x00000021 + >; + }; +}; From 356894c37aa1f8ab430cef5d69176123b0ec98b3 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 10 Jul 2026 18:12:20 +0800 Subject: [PATCH 088/131] arm64: dts: imx91-9x9-qsb: add CAN support overlay file On the i.MX91 9x9 QSB, CAN1 and MICFIL share pins. A TMUX1574RSVR analog mux controls the routing: when SEL is driven high, CAN1 is selected; when SEL is driven low, MICFIL is selected. By default, SEL is kept low. To enable CAN1, SEL must be driven high. This is done via the can_fun function defined in the pinctrl-gpiomux node. CAN1 uses the TJA1057GT/3 PHY. Signed-off-by: Haibo Chen Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx91-9x9-qsb-can1.dtso | 48 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7d77856d3e7d..b60b43071936 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -580,7 +580,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb +imx91-9x9-qsb-can1-dtbs += imx91-9x9-qsb.dtb imx91-9x9-qsb-can1.dtbo imx91-phyboard-segin-peb-av-18-dtbs += imx91-phyboard-segin.dtb imx91-phyboard-segin-peb-av-18.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso new file mode 100644 index 000000000000..b8343d653e51 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +#include +#include "imx91-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_phy>; + silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&flexcan1 { + phys = <&flexcan_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>, <&can_fun>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexcan_phy: flexcanphygrp { + fsl,pins = < + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; + +/* micfil uses PDM port A pins, conflicts with can1 */ +&micfil { + status = "disabled"; +}; From e0e1a9712fb1767dcf5ab69ae47dac2d1a080c3c Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 14 Jul 2026 12:05:18 +0800 Subject: [PATCH 089/131] arm64: dts: imx943-evk: Remove 'supports-clkreq' from PCIe1 Remove the 'supports-clkreq' property from PCIe1 as the standard PCIe slot on i.MX943 EVK may not have CLKREQ# signal wired, causing compatibility issues with some PCIe cards. Fixes: 9a8f11f6f786 ("arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 674410e541cb..49fb1744d992 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -1061,7 +1061,6 @@ &pcie1 { <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; - supports-clkreq; status = "okay"; }; From d879cc948e6f7046af65c867a496bc9cde1da8ef Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:43 -0400 Subject: [PATCH 090/131] arm64: dts: imx8qm-ss-dma: add lpuart4 node Add lpuart4 node for imx8qm. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 974e193f8dcb..738c6f05c4ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -8,6 +8,21 @@ /delete-node/ &adma_pwm_lpcg; &dma_subsys { + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + reg = <0x5a0a0000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart4_lpcg IMX_LPCG_CLK_4>, <&uart4_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_4>; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx","tx"; + status = "disabled"; + }; + uart4_lpcg: clock-controller@5a4a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a4a0000 0x10000>; From f57bf4c11d7fa95afaea45a14d91b067406c60f0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:44 -0400 Subject: [PATCH 091/131] arm64: dts: imx8qm-ss-audio: add spdif1 node Add spdif1 and related lpcg node for imx8qm. Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-ss-audio.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi index 7c5386d4ab2b..5cb644837d93 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -74,6 +74,31 @@ &asrc1_lpcg { }; &audio_subsys { + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59030000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif1_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif1_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; sai4: sai@59080000 { compatible = "fsl,imx8qm-sai"; @@ -109,6 +134,19 @@ sai5: sai@59090000 { status = "disabled"; }; + spdif1_lpcg: clock-controller@59430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59430000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + sai4_lpcg: clock-controller@59480000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59480000 0x10000>; From 617bcacbf0905d2ac25c1fe6d2ab45afc4f9fc3c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:45 -0400 Subject: [PATCH 092/131] arm64: dts: imx8qm-ss-lsio: add lsio mu8 and mu8b Add mu8 and mu8b mailbox nodes. Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index b483134f84d1..e055d41f77cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -3,6 +3,27 @@ * Copyright 2019-2020 NXP * Dong Aisheng */ +&lsio_subsys { + lsio_mu8: mailbox@5d230000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d230000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_8A>; + status = "disabled"; + }; + + lsio_mu8b: mailbox@5d2c0000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d2c0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + fsl,mu-side-b; + power-domains = <&pd IMX_SC_R_MU_8B>; + status = "disabled"; + }; + +}; &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; From 8563591f76ca02c1a6fd70ce986df1d0dde8d249 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:46 -0400 Subject: [PATCH 093/131] arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0 The LPCG clock indices for ASRC0 and AUD_PLL_DIV0 are swapped. The ASRC0 LPCG provides only IMX_LPCG_CLK_4, so update the ASRC0 clock consumer to use IMX_LPCG_CLK_4 instead of the non-existent IMX_LPCG_CLK_0. Likewise, the AUD_PLL_DIV0 LPCG provides only IMX_LPCG_CLK_0, so update its clock consumer to use IMX_LPCG_CLK_0 instead of the non-existent IMX_LPCG_CLK_4. Fixes: 5125617c7a4d3 ("arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]") Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 5e4233ccfde4..f473d81f67ff 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -124,10 +124,10 @@ asrc0: asrc@59000000 { compatible = "fsl,imx8qm-asrc"; reg = <0x59000000 0x10000>; interrupts = ; - clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, - <&asrc0_lpcg IMX_LPCG_CLK_0>, - <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, - <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, + clocks = <&asrc0_lpcg IMX_LPCG_CLK_4>, + <&asrc0_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, <&clk_dummy>, From 174b7dfb7dce9017e482c1fb2aa04ed28a141936 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 13 Jul 2026 11:19:21 +0200 Subject: [PATCH 094/131] dt-bindings: arm: add MBa93xxCA as mainboard for TQMa91xxCA and TQMa91xxLA SOM TQMa91xxLA and TQMa91xxCA are two series of feature compatible SOM using NXP i.MX91 SoC in 11x11 mm package. MBa93xxCA is a starterkit base board usable for TQMa91xxCA and TQMa91xxLA soldered on an adapter board to demonstrate use cases without display but more interfaces. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 52f08bc1f8ea..656f2596e1d5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1619,11 +1619,13 @@ properties: in the assembled SOC. MBa91xxCA mainboard can be used as starterkit for the SOM soldered on an adapter board or for the connector variant - MBa91xxLA mainboard is a single board computer using the solderable - SOM variant + to demonstrate parallel display and majority of interfaces while + MBa93xxCA starterkit mainboard is focused on communication + interfaces without display support. items: - enum: - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA + - tq,imx91-tqma9131-mba93xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa93xxCA - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM - const: fsl,imx91 From 4d0d3a3d1993a41b2bf8d28aa6c6071fa1a3bff7 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 13 Jul 2026 11:19:22 +0200 Subject: [PATCH 095/131] arm64: dts: add devicetree for TQMa91xx on MBa93xxCA This allows using TQMa91xxCA / TQMa91xxLA SoM on MBa93xxCA starter kit. While not having display all other interfaces of this mainboard can be used. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx91-tqma9131-mba93xxca.dts | 937 ++++++++++++++++++ 2 files changed, 938 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b60b43071936..d5c2dc720197 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -586,6 +586,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba93xxca.dtb imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts new file mode 100644 index 000000000000..3fb5bb71b622 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts @@ -0,0 +1,937 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include +#include +#include +#include + +#include "imx91-tqma9131.dtsi" + +/{ + model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa93xxCA starter kit"; + compatible = "tq,imx91-tqma9131-mba93xxca", + "tq,imx91-tqma9131", "fsl,imx91"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial5 = &lpuart6; + serial7 = &lpuart8; + }; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + status = "disabled"; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwmfan>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = ; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = ; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_12v0>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + cpu_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&cpu_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&cpu_active2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + /* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#", + /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = + /* 00 */ "SPI6_PCS0#", "", "", "", + /* 04 */ "", "", "", "SPI_CS#", + /* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC", + /* 12 */ "", "", "", "", + /* 16 */ "X1_11", "X1_21", "X1_17", "X1_13", + /* 20 */ "X1_15", "X1_9", "", "", + /* 24 */ "", "", "X1_7", "", + /* 28 */ "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* 00 */ "SD2_CD#", "", "", "", + /* 04 */ "", "", "", "SD2_RST#", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "DP_INT", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + mpcie-wake-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card's low-active power down pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card's low-active disable pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card's reset pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "DP_EN", + "MIPI_CSI_EN", "MIPI_CSI_RST#", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + toshiba,hpd-pin = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp_dsi_in: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + }; + }; +}; + +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&se97_som { + /* TEMP_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_temp_sensor_som>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; + +/* on LVDS connector, not usable */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000 + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000 + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000 + /* HYS | PD | FSEL_0 | DSE no drive */ + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400 + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = < + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000 + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000 + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000 + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000 + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000 + /* HYS | PD | FSEL_0 | DSE no drive */ + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400 + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = < + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + /* HYS | PU | FSEL_0 | DSE no drive */ + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200 + /* PU | FSEL_3 | DSE X4 */ + MX91_PAD_PDM_CLK__CAN1_TX 0x039e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + /* HYS | PU | FSEL_0 | DSE no drive */ + MX91_PAD_GPIO_IO27__CAN2_RX 0x1200 + /* PU | FSEL_3 | DSE X4 */ + MX91_PAD_GPIO_IO25__CAN2_TX 0x039e + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + /* HYS | PD | FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x151e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x151e + MX91_PAD_GPIO_IO18__GPIO2_IO18 0x151e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x151e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x151e + MX91_PAD_GPIO_IO21__GPIO2_IO21 0x151e + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x151e + >; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = < + MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e + MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200 + MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e + MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200 + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + /* SION | HYS | OD | FSEL_3 | DSE X4 */ + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + /* SION | HYS | OD | FSEL_3 | DSE X4 */ + MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e + MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e + >; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + /* HYS | PD | FSEL_0 | DSE no drive */ + MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x1400 + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e + MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x051e + >; + }; + + pinctrl_lpspi6_cs: lpspi6csgrp { + fsl,pins = < + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO00__GPIO2_IO0 0x011e + MX91_PAD_GPIO_IO07__GPIO2_IO7 0x011e + >; + }; + + pinctrl_mipi_csi: mipicsigrp { + fsl,pins = < + MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */ + MX91_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */ + MX91_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */ + >; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = < + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 + >; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000 + >; + }; + + pinctrl_pwmfan: pwmfangrp { + fsl,pins = < + /* HYS | PU | FSEL_0 | no DSE */ + MX91_PAD_GPIO_IO09__GPIO2_IO9 0x1200 + >; + }; + + pinctrl_tc9595: tc9595-grp { + fsl,pins = < + /* HYS | PD | FSEL_0 | no DSE */ + MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 + >; + }; + + pinctrl_temp_sensor_som: tempsensorsomgrp { + fsl,pins = < + /* HYS | FSEL_0 | no DSE */ + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 + >; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = < + MX91_PAD_GPIO_IO06__TPM5_CH0 0x57e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + MX91_PAD_GPIO_IO08__TPM6_CH0 0x57e + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x1000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_UART1_RXD__LPUART1_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_UART1_TXD__LPUART1_TX 0x011e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_UART2_RXD__LPUART2_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_UART2_TXD__LPUART2_TX 0x011e + /* FSEL_2 | DSE X4 */ + MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_GPIO_IO15__LPUART3_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO14__LPUART3_TX 0x011e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_GPIO_IO05__LPUART6_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO04__LPUART6_TX 0x011e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_GPIO_IO13__LPUART8_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO12__LPUART8_TX 0x011e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000 + >; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = < + /* PD | FSEL_3 | DSE X5 */ + MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be + /* HYS | PU | FSEL_3 | DSE X4 */ + MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + /* HYS | PU | FSEL_3 | DSE X3 */ + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + /* FSEL_2 | DSE X3 */ + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e + >; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = < + /* PD | FSEL_3 | DSE X6 */ + MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe + /* HYS | PU | FSEL_3 | DSE X4 */ + MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + /* FSEL_2 | DSE X3 */ + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e + >; + }; +}; From 8f62ead195283b8620070985ae642a5a1db88843 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:25 +0300 Subject: [PATCH 096/131] arm64: dts: lx2160a: explicitly enable serdes_1 node Explicitly enable the serdes_1 node in all board DT files. This is needed in order to be able to change the default status of the node to "disabled" from the SoC DT file. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 4bc151d721dd..1f946d3a4ec0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -135,6 +135,10 @@ &sata3 { status = "okay"; }; +&serdes_1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts index d16e27307275..954b9955b1b3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts @@ -805,6 +805,10 @@ &rgmii_phy1 { status = "disabled"; }; +&serdes_1 { + status = "okay"; +}; + &serdes_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 935f421475ac..39b2b04be532 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -325,6 +325,10 @@ &sata3 { status = "okay"; }; +&serdes_1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 99ee2b1c0f13..df2568ec7f1a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -367,6 +367,10 @@ &pcs_mdio18 { status = "okay"; }; +&serdes_1 { + status = "okay"; +}; + &serdes_2 { status = "okay"; }; From 12422fe9b3f4876f953bb1699e8c2c18084e58d9 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:26 +0300 Subject: [PATCH 097/131] arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsi One of the major differences between LX2160A Rev1 and Rev2 is the PCIe controller used. With the final goal of removing any usage of delete-node or delete-property from the current LX2160A related dts files, move the PCIe nodes found on the LX2160A Rev1 into a separate dtsi file. This will make it easier to include the appropriate dtsi file describing the PCIe controller depending on the SoC revision in a follow-up patch. No actual change in the DT nodes found in the final DTBs is intended. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi | 176 ++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 170 +---------------- 2 files changed, 178 insertions(+), 168 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi new file mode 100644 index 000000000000..871f5d5d8f75 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the PCIe Mobiveil's GPEX 4.0 IP +// found on LX2160A Rev1 +// +// Copyright 2026 NXP + +&soc { + pcie1: pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie2: pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie3: pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <256>; + ppio-wins = <24>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie4: pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie5: pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ + <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <256>; + ppio-wins = <24>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie6: pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ + <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 1d73abffa6b7..387cd677cdc7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1177,174 +1177,6 @@ sata3: sata@3230000 { status = "disabled"; }; - pcie1: pcie@3400000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ - <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ - <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <256>; - ppio-wins = <24>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie4: pcie@3700000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ - <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie5: pcie@3800000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ - <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <256>; - ppio-wins = <24>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie6: pcie@3900000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ - <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; @@ -2021,3 +1853,5 @@ optee: optee { }; }; }; + +#include "fsl-lx2160a-pcie-mbvl.dtsi" From 9f0f43baf1ed556e6b16ddd5403dc44c5f21eb6a Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:27 +0300 Subject: [PATCH 098/131] arm64: dts: lx2160a: extract the SerDes nodes into a separate dtsi In terms of its SerDes blocks, the LX2162A is not properly described since it just inherits the LX2160A SerDes nodes, which is not correct. In order to fix this but also avoid the usage of delete-node, extract the SerDes nodes currently found in fsl-lx2160a.dtsi into a separate dtsi. No any actual changes in the final dtb files, only a dt node move. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-serdes.dtsi | 21 +++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 14 +------------ 2 files changed, 22 insertions(+), 13 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi new file mode 100644 index 000000000000..307824eda6d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2160A +// Rev1 and Rev2 +// +// Copyright 2026 NXP + +&soc { + serdes_1: phy@1ea0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1ea0000 0x0 0x1e30>; + #phy-cells = <1>; + }; + + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 387cd677cdc7..da139e7fa30c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -621,19 +621,6 @@ soc: soc { ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - serdes_1: phy@1ea0000 { - compatible = "fsl,lynx-28g"; - reg = <0x0 0x1ea0000 0x0 0x1e30>; - #phy-cells = <1>; - }; - - serdes_2: phy@1eb0000 { - compatible = "fsl,lynx-28g"; - reg = <0x0 0x1eb0000 0x0 0x1e30>; - #phy-cells = <1>; - status = "disabled"; - }; - crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>; @@ -1855,3 +1842,4 @@ optee: optee { }; #include "fsl-lx2160a-pcie-mbvl.dtsi" +#include "fsl-lx2160a-serdes.dtsi" From 8f69555ef54c59aa0207cdd0e15939417730a4e4 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:28 +0300 Subject: [PATCH 099/131] arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate file The LX2160A Rev2 SoC changed the PCIe controllers used. This difference is reflected in the fsl-lx2160a-rev2.dtsi file which modifies the relevant dt nodes so that they match the actual HW. Extract these modifications into a separate dtsi file as a first step into a complete overhaul of the LX216xA related dts files with the intent to not use delete-node or delete-property. No final dtb changes are expected with this patch. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 185 +---------------- .../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 187 ++++++++++++++++++ 2 files changed, 188 insertions(+), 184 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi index 3d2637fee2d3..c2a18cfd8efc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -7,187 +7,4 @@ /dts-v1/; #include "fsl-lx2160a.dtsi" - -&pcie1 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie2 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie3 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - - -&pcie4 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie5 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie6 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&soc { - pcie_ep1: pcie-ep@3400000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x80 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; - - pcie_ep2: pcie-ep@3500000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x88 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; - - pcie_ep3: pcie-ep@3600000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x90 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <256>; - num-ib-windows = <24>; - status = "disabled"; - }; - - pcie_ep4: pcie-ep@3700000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03700000 0x0 0x00100000 - 0x98 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; - - - pcie_ep5: pcie-ep@3800000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03800000 0x0 0x00100000 - 0xa0 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <256>; - num-ib-windows = <24>; - status = "disabled"; - }; - - pcie_ep6: pcie-ep@3900000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03900000 0x0 0x00100000 - 0xa8 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; -}; +#include "fsl-lx216xa-pcie-gen3.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi new file mode 100644 index 000000000000..f405b21e68fc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the PCIe IPs found on the LX2160A Rev2 and LX2162A SoCs +// +// Copyright 2026 NXP + +&pcie1 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie2 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie3 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie4 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie5 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie6 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&soc { + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x90 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + num-ib-windows = <24>; + status = "disabled"; + }; + + pcie_ep4: pcie-ep@3700000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03700000 0x0 0x00100000 + 0x98 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep5: pcie-ep@3800000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03800000 0x0 0x00100000 + 0xa0 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + num-ib-windows = <24>; + status = "disabled"; + }; + + pcie_ep6: pcie-ep@3900000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03900000 0x0 0x00100000 + 0xa8 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; +}; From 285560f0d39dd6cd40c5c83470e4d3e43effd4b8 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:29 +0300 Subject: [PATCH 100/131] arm64: dts: lx2160a: split the dtsi to avoid delete-property Reorganize the LX216XA related dts/dtsi files with the intent to avoid any delete-property usage. Taken into consideration the differences between the LX2160A Rev1, LX2160A Rev2 and LX2162A SoCs, the following structure is created: fsl-lx216x.dtsi ---> fsl-lx2160a-rev1.dtsi (PCIe gen4, 3 SerDes blocks) (no PCIe, no SerDes) ---> fsl-lx2160a-rev2.dtsi (PCIe gen3, 3 SerDes blocks) ---> fsl-lx2162a.dtsi (PCIe gen3, 2 SerDes blocks) Each PCIe integration or SerDes block instantiation has its own dtsi file which gets to be included only by the necessary SoC level dtsi file. The dtsi file describing the PCIe controllers found on LX2160A Rev2 is also changed so that it does not work on a already defined node but rather it describes it entirely. In order to decouple the LX2162A from LX2160A, a new dtsi fsl-lx2162a-serdes.dtsi file is added which, for the moment, only duplicates the SerDes related nodes found already for LX2160A. Any dts which previously included fsl-lx2160a.dtsi now includes the -rev1 version and any dts which is clearly intended for LX2162A based board now includes the fsl-lx2162a.dtsi. No changes for the final dtbs. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-bluebox3.dts | 2 +- .../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 +- .../dts/freescale/fsl-lx2160a-honeycomb.dts | 2 +- .../boot/dts/freescale/fsl-lx2160a-rev1.dtsi | 9 + .../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 3 +- .../dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi | 2 +- .../dts/freescale/fsl-lx2162a-clearfog.dts | 2 +- .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +- .../dts/freescale/fsl-lx2162a-serdes.dtsi | 21 ++ .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 9 + .../{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} | 3 - .../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 310 +++++++++++------- 12 files changed, 237 insertions(+), 130 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi rename arch/arm64/boot/dts/freescale/{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} (99%) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts index 042c486bdda2..e035e4456867 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" / { model = "NXP Layerscape LX2160ABLUEBOX3"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts index 802d7611c647..4e47bb389af6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" #include "fsl-lx2160a-cex7.dtsi" #include "fsl-lx2160a-clearfog-itx.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts index 2b1e13053422..1a603decd034 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" #include "fsl-lx2160a-cex7.dtsi" #include "fsl-lx2160a-clearfog-itx.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi new file mode 100644 index 000000000000..7538dbdc8093 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree Include file for Layerscape-LX2160A Rev1 SoC. +// +// Copyright 2026 NXP + +#include "fsl-lx216x.dtsi" +#include "fsl-lx2160a-pcie-mbvl.dtsi" +#include "fsl-lx2160a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi index c2a18cfd8efc..47a42347c230 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -6,5 +6,6 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx216x.dtsi" #include "fsl-lx216xa-pcie-gen3.dtsi" +#include "fsl-lx2160a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi index 89a4765737b4..cc6b6427ec8a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi @@ -5,7 +5,7 @@ * Author: Gregor Herburger */ -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" / { reg_vcc3v3: regulator-vcc3v3 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index df2568ec7f1a..63f161610caa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -8,7 +8,7 @@ #include -#include "fsl-lx2160a-rev2.dtsi" +#include "fsl-lx2162a.dtsi" #include "fsl-lx2162a-sr-som.dtsi" / { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 7a595fddc027..0ba56b9819ac 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a-rev2.dtsi" +#include "fsl-lx2162a.dtsi" / { model = "NXP Layerscape LX2162AQDS"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi new file mode 100644 index 000000000000..23f05a138eac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A +// SoC +// +// Copyright 2026 NXP + +&soc { + serdes_1: phy@1ea0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1ea0000 0x0 0x1e30>; + #phy-cells = <1>; + }; + + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi new file mode 100644 index 000000000000..b710f6a8eb48 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162 SoC +// +// Copyright 2026 NXP + +#include "fsl-lx216x.dtsi" +#include "fsl-lx216xa-pcie-gen3.dtsi" +#include "fsl-lx2162a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi similarity index 99% rename from arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi rename to arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi index da139e7fa30c..ae6e37870c5e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi @@ -1840,6 +1840,3 @@ optee: optee { }; }; }; - -#include "fsl-lx2160a-pcie-mbvl.dtsi" -#include "fsl-lx2160a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi index f405b21e68fc..068fbf9bf04f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi @@ -4,127 +4,39 @@ // // Copyright 2026 NXP -&pcie1 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie2 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie3 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie4 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie5 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie6 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - &soc { + pcie1: pcie@3400000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep1: pcie-ep@3400000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000 @@ -135,6 +47,37 @@ pcie_ep1: pcie-ep@3400000 { status = "disabled"; }; + pcie2: pcie@3500000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep2: pcie-ep@3500000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000 @@ -145,6 +88,38 @@ pcie_ep2: pcie-ep@3500000 { status = "disabled"; }; + pcie3: pcie@3600000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep3: pcie-ep@3600000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000 @@ -155,6 +130,37 @@ pcie_ep3: pcie-ep@3600000 { status = "disabled"; }; + pcie4: pcie@3700000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep4: pcie-ep@3700000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03700000 0x0 0x00100000 @@ -165,6 +171,38 @@ pcie_ep4: pcie-ep@3700000 { status = "disabled"; }; + pcie5: pcie@3800000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep5: pcie-ep@3800000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03800000 0x0 0x00100000 @@ -175,6 +213,38 @@ pcie_ep5: pcie-ep@3800000 { status = "disabled"; }; + pcie6: pcie@3900000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep6: pcie-ep@3900000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03900000 0x0 0x00100000 From bc12e3ee01c82f2da45c6240b74f501b82732b27 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:30 +0300 Subject: [PATCH 101/131] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes instance is present in the compatible string, to allow reliable per-lane capability detection and per-lane customization of electrical properties. The modern bindings are backward-incompatible with old kernels, due to the consumer phandles being either in one form or in another, as explained here: https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/ Also mark the serdes_1 node as disabled by default since any dts using it enables it explicitly now. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-serdes.dtsi | 150 +++++++++++++++++- 1 file changed, 148 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi index 307824eda6d6..d482920f4d17 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi @@ -6,16 +6,162 @@ // Copyright 2026 NXP &soc { + /* Note on the interpretation of SerDes lane numbering from + * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]: + * The letters (A-H) correspond to logical lane numbers in the + * SerDes register map (lane A's registers start with LNAGCR0), + * while the numbers (0-7) correspond to physical lanes as + * routed to pins. SerDes block #1 is flipped in the LX2160A + * floorplan (logical lane A goes to physical lane 7's pins), + * while SerDes blocks #2 and #3 are not. The lanes below are + * listed right to left when looking at that table. + * Both the numbers and the letters are according to the logical + * numbering scheme, and do not account for the flipping. + */ serdes_1: phy@1ea0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g"; reg = <0x0 0x1ea0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; + status = "disabled"; + + serdes_1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; serdes_2: phy@1eb0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g"; reg = <0x0 0x1eb0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; status = "disabled"; + + serdes_2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_2_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_2_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_2_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_2_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + + serdes_3: phy@1ec0000 { + compatible = "fsl,lx2160a-serdes3"; + reg = <0x0 0x1ec0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes_3_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_3_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_3_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_3_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_3_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_3_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_3_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_3_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; }; From 21cb12ad026e91aca65329531554ec1e74a32e77 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:31 +0300 Subject: [PATCH 102/131] arm64: dts: lx2162a: transition to device-specific SerDes compatible strings Align to the modern fsl,lynx-28g.yaml binding for the LX2162A SoC, where the SoC and SerDes instance is present in the compatible string, to allow reliable per-lane capability detection and per-lane customization of electrical properties. Since one of the major differences between LX2162A and LX2160A is the SerDes, add the necessary nodes to its own fsl-lx2162a-serdes.dtsi file. Also mark the serdes_1 node as disabled by default since any dts using it enables it explicitly now. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2162a-serdes.dtsi | 69 ++++++++++++++++++- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi index 23f05a138eac..1ab18f0c67c2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi @@ -7,15 +7,80 @@ &soc { serdes_1: phy@1ea0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g"; reg = <0x0 0x1ea0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; + status = "disabled"; + + serdes_1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; serdes_2: phy@1eb0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g"; reg = <0x0 0x1eb0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; status = "disabled"; + + serdes_2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_2_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_2_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_2_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_2_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; }; From 2b64e802a7c8a577616289b023a98e009318123d Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:32 +0300 Subject: [PATCH 103/131] arm64: dts: ls1028a: describe the Lynx 10G SerDes Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the LS1028A SoC. The node is left disabled at the SoC level; board DTs will be expected to enable it once the consumer Ethernet nodes use it. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index f4ba3d16ab86..ef62968590fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c { }; }; + serdes: phy@1ea0000 { + compatible = "fsl,ls1028a-serdes"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + scfg: syscon@1fc0000 { compatible = "fsl,ls1028a-scfg", "syscon"; reg = <0x0 0x1fc0000 0x0 0x10000>; From 65121d706ecd9c7b1365f91cc9f4e3c01fd9f15b Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:33 +0300 Subject: [PATCH 104/131] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1046A SoC. The nodes are left disabled at the SoC level; board DTs will be expected to enable them once the consumer Ethernet nodes appear. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 6fefe837f434..270a97711a69 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -424,6 +424,66 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls1046a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls1046a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; From 9eb4d238348fb1b81cc25ec3c50c13b85b6055d1 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:34 +0300 Subject: [PATCH 105/131] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS208xA SoC. The nodes are left disabled at the SoC level; board DTs will enable them once there are consumers. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 6073e426774a..cc1a64e63ed5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -280,6 +280,104 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls2088a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls2088a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes2_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes2_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes2_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes2_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + isc: syscon@1f70000 { compatible = "fsl,ls2080a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; From c482d6c37187fe38662f278213301b7828cda662 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:35 +0300 Subject: [PATCH 106/131] arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1088A SoC. The nodes are left disabled at the SoC level; board DTs will enable them once there are consumers. Note that the SerDes block #2 is non-networking, meaning that it will not get probed by the Lynx10G SerDes PHY driver and it's only added for a complete hardware description. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 99016768b73f..e02f34329988 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -239,6 +239,64 @@ reset: syscon@1e60000 { reg = <0x0 0x1e60000 0x0 0x10000>; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls1088a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls1088a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; From 853d77cc0c06e686d0214a015fe88c1047ba6302 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 21 Jul 2026 09:12:41 -0700 Subject: [PATCH 107/131] arm64: dts: s32g: Add GPR syscon region Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter [jkangas@redhat.com: GPR syscon resized from 0x3000 to 0x100] Signed-off-by: Jared Kangas Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 8dc0c5d9f368..996494e34593 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -122,6 +122,11 @@ rtc0: rtc@40060000 { clock-names = "ipg", "source0"; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g2-gpr", "syscon"; + reg = <0x4007c000 0x100>; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -814,6 +819,7 @@ gmac0: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 24fa3057e929..31f7aad00b76 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -180,6 +180,11 @@ rtc0: rtc@40060000 { clock-names = "ipg", "source0"; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g3-gpr", "syscon"; + reg = <0x4007c000 0x100>; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -893,6 +898,7 @@ gmac0: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; From e1e3f7582bb87e849bd3e4101696992878529340 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:09 +0800 Subject: [PATCH 108/131] arm64: dts: imx8ulp: Add DMA channel properties and use eDMA flag macros Add DMA channel (dmas/dma-names) properties to peripheral nodes that were missing them: - LPI2C: lpi2c4, lpi2c5, lpi2c6, lpi2c7 - LPUART: lpuart4, lpuart5, lpuart6, lpuart7 - LPSPI: lpspi4, lpspi5 Also replace hardcoded numeric DMA direction flags with the proper FSL_EDMA_RX and FSL_EDMA_MULTI_FIFO macros for SAI (sai4, sai5, sai6, sai7) and SPDIF nodes. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++---- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c6d1bb9edf38..1ab4ab270dc2 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -370,6 +371,8 @@ lpi2c4: i2c@29370000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 46 0 0>, <&edma1 45 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -383,6 +386,8 @@ lpi2c5: i2c@29380000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 48 0 0>, <&edma1 47 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -392,6 +397,8 @@ lpuart4: serial@29390000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; clock-names = "ipg"; + dmas = <&edma1 55 0 FSL_EDMA_RX>, <&edma1 56 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -401,6 +408,8 @@ lpuart5: serial@293a0000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; + dmas = <&edma1 57 0 FSL_EDMA_RX>, <&edma1 58 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -416,6 +425,8 @@ lpspi4: spi@293b0000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 64 0 0>, <&edma1 63 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -431,6 +442,8 @@ lpspi5: spi@293c0000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 66 0 0>, <&edma1 65 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -474,6 +487,8 @@ lpi2c6: i2c@29840000 { assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 50 0 0>, <&edma1 49 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -487,6 +502,8 @@ lpi2c7: i2c@29850000 { assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 52 0 0>, <&edma1 51 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -496,6 +513,8 @@ lpuart6: serial@29860000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; clock-names = "ipg"; + dmas = <&edma1 59 0 FSL_EDMA_RX>, <&edma1 60 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -505,6 +524,8 @@ lpuart7: serial@29870000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; clock-names = "ipg"; + dmas = <&edma1 61 0 FSL_EDMA_RX>, <&edma1 62 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -516,7 +537,7 @@ sai4: sai@29880000 { <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; + dmas = <&edma1 67 0 FSL_EDMA_RX>, <&edma1 68 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x03 0x03>; @@ -531,7 +552,7 @@ sai5: sai@29890000 { <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; + dmas = <&edma1 69 0 FSL_EDMA_RX>, <&edma1 70 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x0f 0x0f>; @@ -814,7 +835,7 @@ sai6: sai@2da90000 { <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; + dmas = <&edma2 71 0 FSL_EDMA_RX>, <&edma2 72 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x0f 0x0f>; @@ -829,7 +850,7 @@ sai7: sai@2daa0000 { <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; + dmas = <&edma2 73 0 FSL_EDMA_RX>, <&edma2 74 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x0f 0x0f>; @@ -855,7 +876,8 @@ spdif: spdif@2dab0000 { "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba"; - dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; + dmas = <&edma2 75 0 (FSL_EDMA_RX | FSL_EDMA_MULTI_FIFO)>, + <&edma2 76 0 FSL_EDMA_MULTI_FIFO>; dma-names = "rx", "tx"; status = "disabled"; }; From 5f3301712f42c89df861d26518121d1deefca96c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:10 +0800 Subject: [PATCH 109/131] arm64: dts: imx8ulp: Add I3C2 controller node Add the I3C2 (i3c-master@29360000) node to the imx8ulp device tree using the Silvaco I3C master IP. Configure PCC3-gated clock with SOSC DIV2 as parent at 24 MHz for pclk and fast_clk. slow_clk uses a dummy clock. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 1ab4ab270dc2..cb0d73327d86 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -361,6 +361,22 @@ tpm5: tpm@29340000 { status = "disabled"; }; + i3c2: i3c@29360000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x29360000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&pcc3 IMX8ULP_CLK_I3C2>, + <&pcc3 IMX8ULP_CLK_I3C2>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + lpi2c4: i2c@29370000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29370000 0x10000>; From 92ccf83b8d58f9dca5752a824f0e81ac54665889 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:11 +0800 Subject: [PATCH 110/131] arm64: dts: imx8ulp: Correct SRAM node address and size to cover full SSRAM P2 The SSRAM P2 partition starts at 0x22010000 with a size of 64 KB. The previous node only mapped the last 4 KB (0x2201f000, 0x1000) which was used for the SCMI shared memory buffer. Update the base address and size to cover the full P2 region so it can also serve as a general purpose SRAM pool. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index cb0d73327d86..7d00fe836094 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -154,17 +154,17 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@2201f000 { + sram@22010000 { compatible = "mmio-sram"; - reg = <0x0 0x2201f000 0x0 0x1000>; + reg = <0x0 0x22010000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0x2201f000 0x1000>; + ranges = <0 0x0 0x22010000 0x10000>; - scmi_buf: scmi-sram-section@0 { + scmi_buf: scmi-sram-section@f000 { compatible = "arm,scmi-shmem"; - reg = <0x0 0x400>; + reg = <0xf000 0x400>; }; }; From c89839764bf17b76d6f53d5923a28bda140a46cc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:12 +0800 Subject: [PATCH 111/131] arm64: dts: imx8ulp: Add assigned clock properties for LPUART nodes Add assigned-clocks, assigned-clock-parents and assigned-clock-rates properties to lpuart4 through lpuart7, so the LPUART input clock is configured automatically by the clock framework during probe. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 7d00fe836094..777b89ed6849 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -413,6 +413,9 @@ lpuart4: serial@29390000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; dmas = <&edma1 55 0 FSL_EDMA_RX>, <&edma1 56 0 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -424,6 +427,9 @@ lpuart5: serial@293a0000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; dmas = <&edma1 57 0 FSL_EDMA_RX>, <&edma1 58 0 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -529,6 +535,9 @@ lpuart6: serial@29860000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; clock-names = "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; dmas = <&edma1 59 0 FSL_EDMA_RX>, <&edma1 60 0 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -540,6 +549,9 @@ lpuart7: serial@29870000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; clock-names = "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; dmas = <&edma1 61 0 FSL_EDMA_RX>, <&edma1 62 0 0>; dma-names = "rx", "tx"; status = "disabled"; From 011242de59d0eb69e7b8a4f42dc32cf1f5d53592 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:13 +0800 Subject: [PATCH 112/131] arm64: dts: imx8ulp-evk: Add gpio-keys node for power button Add a gpio-keys node for the power-on button, report it as KEY_POWER to user space. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 19 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index 5497e3d78136..af8f0d6087f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -10,6 +10,18 @@ / { model = "NXP i.MX8ULP EVK9"; compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-power-on { + label = "PowerOn"; + gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &btcpu { @@ -43,6 +55,12 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 >; }; +&pinctrl_gpio_keys { + fsl,pins = < + MX8ULP_PAD_PTF11__PTF11 0x3 + >; +}; + &pinctrl_usb1 { fsl,pins = < MX8ULP_PAD_PTE16__USB0_ID 0x10003 diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 5dea66c1e7aa..6a92c5ca9a41 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8ulp.dtsi" / { @@ -20,6 +21,18 @@ chosen { stdout-path = &lpuart5; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-power-on { + label = "PowerOn"; + gpios = <&gpiof 31 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; @@ -323,6 +336,12 @@ MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 >; }; + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8ULP_PAD_PTF31__PTF31 0x3 + >; + }; + pinctrl_lpuart5: lpuart5grp { fsl,pins = < MX8ULP_PAD_PTF14__LPUART5_TX 0x3 From fdcdcb8dd47e829f5bdb4e52ecce210e845ef4f7 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 20 Jul 2026 22:12:14 +0800 Subject: [PATCH 113/131] arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth Enable lpuart6 with RTS/CTS flow control on the i.MX 8ULP EVK board and add an NXP 88W8987 Bluetooth companion node to pair the UART transport with the wireless chip. i.MX8ULP 9X9 EVK use different lpuart6 pins which used for M.2 bluetooth, also use the sai6 instead of sai5 for PCM interface on M.2, so need to update the pin setting in dts. Signed-off-by: Sherry Sun Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 17 ++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 20 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index af8f0d6087f7..71c66c58edc4 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -75,6 +75,23 @@ MX8ULP_PAD_PTE20__USB1_OC 0x10003 >; }; +&pinctrl_lpuart6 { + fsl,pins = < + MX8ULP_PAD_PTF18__LPUART6_TX 0x3 + MX8ULP_PAD_PTF19__LPUART6_RX 0x3 + MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x3 + MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x3 + >; +}; + +&lpspi5 { /* conflict with lpuart6 PAD_PTF16-19 */ + status = "disabled"; +}; + +&sai5 { + status = "disabled"; +}; + &sai6 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_sai6>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 6a92c5ca9a41..84c61656f3f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -167,6 +167,17 @@ &lpuart5 { status = "okay"; }; +&lpuart6 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart6>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &lpi2c7 { #address-cells = <1>; #size-cells = <0>; @@ -349,6 +360,15 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3 >; }; + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + MX8ULP_PAD_PTE10__LPUART6_TX 0x3 + MX8ULP_PAD_PTE11__LPUART6_RX 0x3 + MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + >; + }; + pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 From 35bdffecf91b8f31a526116d488022fa0f5e09ad Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 20 Jul 2026 22:12:15 +0800 Subject: [PATCH 114/131] arm64: dts: imx8ulp-evk: Enable LPUART7 The i.MX 8ULP EVK proto1B revision routes LPUART7 TX/RX to the FT4232 PortD connector (J25/J26 pins 2-3). Enable the port by default so the additional serial console is available out of the box. Signed-off-by: Sherry Sun Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 84c61656f3f2..9da54291c753 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -178,6 +178,13 @@ bluetooth { }; }; +&lpuart7 { + /* FT4232 PortD: need to connect J25/J26 2-3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; + status = "okay"; +}; + &lpi2c7 { #address-cells = <1>; #size-cells = <0>; @@ -369,6 +376,13 @@ MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3 >; }; + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + MX8ULP_PAD_PTF22__LPUART7_TX 0x3 + MX8ULP_PAD_PTF23__LPUART7_RX 0x3 + >; + }; + pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 From 7108abc25f3b6f97e3098650924816ccdbc06367 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Mon, 20 Jul 2026 22:12:16 +0800 Subject: [PATCH 115/131] arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET Change to use standard drive strength and slow slew rate on PTE14-17, 22, 23, otherwise the overshoot of ENET is too high. Signed-off-by: Wei Fang Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 9da54291c753..22c1d542798d 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -323,15 +323,15 @@ &mu { &iomuxc1 { pinctrl_enet: enetgrp { fsl,pins = < - MX8ULP_PAD_PTE15__ENET0_MDC 0x43 - MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 - MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTE15__ENET0_MDC 0x7 + MX8ULP_PAD_PTE14__ENET0_MDIO 0x7 + MX8ULP_PAD_PTE17__ENET0_RXER 0x7 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 - MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 - MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 - MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x7 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x7 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x7 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 >; From c4e8b643c83d4abfbd92e7161b4975f670eff0a6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:17 +0800 Subject: [PATCH 116/131] arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size Rename the board model from "NXP i.MX8ULP EVK9" to "NXP i.MX8ULP 9x9 EVK" to follow the i.MX naming convention where the die size (9x9 mm) is used instead of an opaque board revision suffix. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index 71c66c58edc4..e6bc6e6555f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -8,7 +8,7 @@ #include "imx8ulp-evk.dts" / { - model = "NXP i.MX8ULP EVK9"; + model = "NXP i.MX8ULP 9x9 EVK"; compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; gpio-keys { From 3c45ac08d2897aeb95ceecde25a6d4935c4ab8be Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 22 Jul 2026 13:33:05 +0200 Subject: [PATCH 117/131] arm64: dts: imx8qm-var-som-symphony: enable expansion header UART Enable LPUART4 and configure its pin multiplexing to expose the UART interface on the Symphony expansion header. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts index c7d3073b4041..ec55b86c220d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts @@ -287,6 +287,13 @@ &lpuart2 { status = "okay"; }; +/* header */ +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + &pca9534 { usb3-signal-route-hog { gpio-hog; @@ -428,6 +435,13 @@ IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 >; }; + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX8QM_M40_GPIO0_01_DMA_UART4_TX 0x06000020 + IMX8QM_M40_GPIO0_00_DMA_UART4_RX 0x06000020 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021 From db8398bb31d740e621e3309e929a06adbc664f2f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 24 Jul 2026 14:17:55 +0800 Subject: [PATCH 118/131] arm64: dts: imx95-19x19-evk: Add CM7 node and related memory nodes Add remoteproc CM7 node and reserved memory regions to enable the Cortex-M7 remote processor. The reserved memory includes firmware memory, virtio device vring buffers, a resource table and a shared DMA pool for inter-processor communication via the MU7 mailbox. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx95-19x19-evk.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 340ab0253ec2..814da90243b2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -76,6 +76,42 @@ linux_cma: linux,cma { linux,cma-default; reusable; }; + + m7_reserved: memory@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; }; flexcan1_phy: can-phy0 { @@ -185,6 +221,16 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,name = "bt-sco-audio"; From 7d1f4e4f62a1b076fb91b708a2dc74432827c3d7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 24 Jul 2026 14:17:56 +0800 Subject: [PATCH 119/131] arm64: dts: imx952-evk: Add CM7 node and related memory nodes Add remoteproc CM7 node and reserved memory regions to enable the Cortex-M7 remote processor. The reserved memory includes firmware memory, virtio device vring buffers and a resource table for inter-processor communication via the MU7 mailbox. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 50 ++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 62d1c1c7c501..2224b90aafe9 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -82,6 +82,42 @@ linux_cma: linux,cma { linux,cma-default; reusable; }; + + m7_reserved: memory@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdev0buffer: vdev0buffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; }; flexcan1_phy: can-phy0 { @@ -151,6 +187,16 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,bitclock-inversion; @@ -451,6 +497,10 @@ &micfil { status = "okay"; }; +&mu7 { + status = "okay"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, From 89d93ad8afedfcbc8281d07f68b18829325d73ab Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 24 Jul 2026 14:17:57 +0800 Subject: [PATCH 120/131] arm64: dts: imx943-evk: Add CM7 and CM33S nodes Add remoteproc nodes for the two Cortex-M7 cores (CM7-0, CM7-1) and the Cortex-M33S core, along with their respective reserved memory regions for firmware, virtio device vrings, resource tables and shared DMA pools. Enable the MU11, MU13 and MU15 mailbox units used for inter-processor communication with each remote processor. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 135 +++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 49fb1744d992..64660f94f4e9 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -133,6 +133,36 @@ reg_audio_pwr: regulator-wm8962-pwr { enable-active-high; }; + remoteproc-cm70 { + compatible = "fsl,imx94-cm70"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu11 0 1 + &mu11 1 1 + &mu11 3 1>; + memory-region = <&cm70_vdev0buffer>, <&cm70_vdev0vring0>, <&cm70_vdev0vring1>, + <&cm70_vdev1vring0>, <&cm70_vdev1vring1>, <&cm70_rsc_table>; + }; + + remoteproc-cm71 { + compatible = "fsl,imx94-cm71"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu13 0 1 + &mu13 1 1 + &mu13 3 1>; + memory-region = <&cm71_vdev0buffer>, <&cm71_vdev0vring0>, <&cm71_vdev0vring1>, + <&cm71_vdev1vring0>, <&cm71_vdev1vring1>, <&cm71_rsc_table>; + }; + + remoteproc-cm33s { + compatible = "fsl,imx94-cm33s"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu15 0 1 + &mu15 1 1 + &mu15 3 1>; + memory-region = <&cm33s_vdev0buffer>, <&cm33s_vdev0vring0>, <&cm33s_vdev0vring1>, + <&cm33s_vdev1vring0>, <&cm33s_vdev1vring1>, <&cm33s_rsc_table>; + }; + reserved-memory { ranges; #address-cells = <2>; @@ -145,6 +175,99 @@ linux,cma { size = <0 0x10000000>; linux,cma-default; }; + + cm33s_vdev0vring0: vdev0vring0@20800000 { + reg = <0 0x20800000 0 0x8000>; + no-map; + }; + + cm33s_vdev0vring1: vdev0vring1@20808000 { + reg = <0 0x20808000 0 0x8000>; + no-map; + }; + + cm33s_vdev1vring0: vdev1vring0@20810000 { + reg = <0 0x20810000 0 0x8000>; + no-map; + }; + + cm33s_vdev1vring1: vdev1vring1@20818000 { + reg = <0 0x20818000 0 0x8000>; + no-map; + }; + + cm33s_rsc_table: rsc-table@208a0000 { + reg = <0 0x208a0000 0 0x1000>; + no-map; + }; + + cm33s_vdev0buffer: vdev0buffer@20820000 { + compatible = "shared-dma-pool"; + reg = <0 0x20820000 0 0x80000>; + no-map; + }; + + cm70_vdev0vring0: vdev0vring0@82000000 { + reg = <0 0x82000000 0 0x8000>; + no-map; + }; + + cm70_vdev0vring1: vdev0vring1@82008000 { + reg = <0 0x82008000 0 0x8000>; + no-map; + }; + + cm70_vdev1vring0: vdev1vring0@82010000 { + reg = <0 0x82010000 0 0x8000>; + no-map; + }; + + cm70_vdev1vring1: vdev1vring1@82018000 { + reg = <0 0x82018000 0 0x8000>; + no-map; + }; + + cm70_rsc_table: rsc-table@82220000 { + reg = <0 0x82220000 0 0x1000>; + no-map; + }; + + cm70_vdev0buffer: vdev0buffer@82020000 { + compatible = "shared-dma-pool"; + reg = <0 0x82020000 0 0x100000>; + no-map; + }; + + cm71_vdev0vring0: vdev0vring0@84000000 { + reg = <0 0x84000000 0 0x8000>; + no-map; + }; + + cm71_vdev0vring1: vdev0vring1@84008000 { + reg = <0 0x84008000 0 0x8000>; + no-map; + }; + + cm71_vdev1vring0: vdev1vring0@84010000 { + reg = <0 0x84010000 0 0x8000>; + no-map; + }; + + cm71_vdev1vring1: vdev1vring1@84018000 { + reg = <0 0x84018000 0 0x8000>; + no-map; + }; + + cm71_rsc_table: rsc-table@84220000 { + reg = <0 0x84220000 0 0x1000>; + no-map; + }; + + cm71_vdev0buffer: vdev0buffer@84020000 { + compatible = "shared-dma-pool"; + reg = <0 0x84020000 0 0x100000>; + no-map; + }; }; sound-bt-sco { @@ -592,6 +715,18 @@ &micfil { status = "okay"; }; +&mu11 { + status = "okay"; +}; + +&mu13 { + status = "okay"; +}; + +&mu15 { + status = "okay"; +}; + &netc_blk_ctrl { assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>, <&scmi_clk IMX94_CLK_MAC5>; From d93dce11f39aaf5c2b246e68f20d47b92e99d331 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 24 Jul 2026 14:17:58 +0800 Subject: [PATCH 121/131] arm64: dts: imx8ulp-evk: Update rpmsg resource table address The MCU firmware copies the rsc table to a fixed address (0x1FFF8000) at startup. However, this address is occupied by variables used in the MCU firmware, so copying the rsc table there corrupts those variables. Move the rsc-table reserved memory region from 0x1FFF8000 to 0x20000000 to avoid the conflict. The M33 firmware linker script has been updated accordingly to place the rpmsg resource table at 0x20000000 (DTCM m_rsc_tbl region). Signed-off-by: Biwen Li Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 22c1d542798d..4b925832bb66 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -55,8 +55,8 @@ m33_reserved: noncacheable-section@a8600000 { no-map; }; - rsc_table: rsc-table@1fff8000 { - reg = <0 0x1fff8000 0 0x1000>; + rsc_table: rsc-table@20000000 { + reg = <0 0x20000000 0 0x1000>; no-map; }; From 95870e5eb88c6efa252de89bd8dd360f1150b388 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 24 Jul 2026 21:30:04 +0200 Subject: [PATCH 122/131] arm64: dts: imx95-var-dart-sonata: enable in-band status for SFP The 10GBASE-R port is connected to an SFP cage and requires in-band status handling for link state reporting. Set managed to "in-band-status" so phylink can manage the SFP link through the PCS. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index ccf7e77016e4..3479abc25df2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -157,6 +157,7 @@ &enetc_port1 { }; &enetc_port2 { + managed = "in-band-status"; phy-mode = "10gbase-r"; sfp = <&sfp0>; status = "okay"; From 0a0ed37b68ff9e09025f9f5ed780e6b8b343302b Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:27 +0200 Subject: [PATCH 123/131] arm64: dts: freescale: imx8mm-verdin: Add NAU8822 Bridge Tied Load Add a device tree overlay for configuring the NAU8822 loudspeaker outputs as a Bridge Tied Load (BTL) output on the Verdin Development Board. The overlay adds the codec property for the BTL-capable output configuration, where the two loudspeaker outputs are combined for higher output power. Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ .../freescale/imx8mm-verdin-dev-nau8822-btl.dtso | 14 ++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d5c2dc720197..dcc0464b4e80 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -177,6 +177,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb @@ -184,12 +185,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb +imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo + imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso new file mode 100644 index 000000000000..e4b662519a6b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Enable Bridge Tied Load (BTL) speaker mode on the Verdin Development Board, + * combining the two loudspeaker outputs for higher output power. + */ + +/dts-v1/; +/plugin/; + +&nau8822_1a { + nuvoton,spk-btl; +}; From 70b923a721c9364e43967a9a0e7b37c52bc57ec7 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:28 +0200 Subject: [PATCH 124/131] arm64: dts: freescale: imx8mm-verdin: Add DSI to HDMI adapter overlay Add a device tree overlay for the Toradex DSI to HDMI Adapter, an accessory that connects to the Verdin DSI_1 interface and provides a full-size HDMI Type-A output. The adapter is based on the Lontium LT8912B DSI-to-HDMI bridge. The overlay is also combined with the Verdin iMX8M Mini carrier board device trees to provide ready-to-use DTBs for the Dahlia, Yavia and Development Board carriers, in both WiFi and non-WiFi SoM variants. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 13 +++ .../freescale/imx8mm-verdin-dsi-to-hdmi.dtso | 88 +++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dcc0464b4e80..f55c570cb3e3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -178,21 +178,34 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb +imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo +imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso new file mode 100644 index 000000000000..507d0bbb5935 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to HDMI Adapter on Verdin DSI_1. + * + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + reg_dsi_hdmi: regulator-dsi-hdmi { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "DSI_1_PWR_EN"; + }; +}; + +&hdmi_connector { + status = "okay"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&dsi_hdmi_bridge_out>; + }; + }; +}; + +&hdmi_lontium_lt8912 { + vdd-supply = <®_dsi_hdmi>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_hdmi_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi_hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_hdmi_bridge_in>; +}; + +/* Verdin PWM_3_DSI (SODIMM 19) repurposed as HDMI HPD GPIO */ +&pwm1 { + status = "disabled"; +}; From e23768eba9badb72bf335e77cdfdc4eb73174bbc Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:29 +0200 Subject: [PATCH 125/131] arm64: dts: freescale: imx8mm-verdin: Add Toradex DSI to LVDS adapter with 10.1" display Add a device tree overlay for the Toradex DSI to LVDS Adapter with the Toradex Capacitive Touch Display 10.1" LVDS. The adapter connects to the Verdin DSI_1 interface. It is based on the Texas Instruments SN65DSI84 DSI-to-LVDS bridge and drives a LogicTechno LT170410-2WHC 10.1" WXGA IPS LCD panel. Touch input is provided by an Atmel maXTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + ...in-dsi-to-lvds-panel-cap-touch-10inch.dtso | 104 ++++++++++++++++++ 2 files changed, 108 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f55c570cb3e3..91ae54931818 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -179,6 +179,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb @@ -191,6 +192,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb @@ -204,6 +206,8 @@ imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8 imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \ + imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso new file mode 100644 index 000000000000..2c253018893b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to LVDS Adapter on Verdin DSI_1 with Capacitive Touch Display + * 10.1". Used on Dahlia (X17) and Development Board (X48) that expose DSI_1 + * via a Samtec LSS-130 connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter + * https://www.toradex.com/accessories/verdin-dsi-to-lvds-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT (SODIMM 46) - DSI_1_BKL_EN_LVDS */ + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI (SODIMM 19) - PWM_3_DSI_LVDS */ + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-bridge { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight_pwm3>; + power-supply = <®_dsi_lvds>; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; + + reg_dsi_lvds: regulator-dsi-lvds { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "DSI_1_PWR_EN"; + }; +}; + +&atmel_mxt_ts { + vdd-supply = <®_dsi_lvds>; + + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&lvds_ti_sn65dsi84 { + vcc-supply = <®_dsi_lvds>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_lvds_bridge_in>; +}; From 16790c0bdb2b20f8ab0286f74a617839cfa81e29 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:30 +0200 Subject: [PATCH 126/131] arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 10.1" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" on the Verdin DSI_1 interface. The display features an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA IPS TFT LCD panel. The touch input is provided by an Ilitek ILI2132 capacitive touch controller. The overlay is also combined with the Verdin iMX8M Mini Dahlia carrier board device trees to provide ready-to-use DTBs in both WiFi and non-WiFi SoM variants. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 7 + ...8mm-verdin-panel-cap-touch-10inch-dsi.dtso | 129 ++++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 91ae54931818..00dc2893c754 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb @@ -189,7 +190,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb @@ -202,9 +205,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb \ + imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := imx8mm-verdin-wifi-dahlia.dtb \ + imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \ imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso new file mode 100644 index 000000000000..5626903d668a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" on Verdin DSI_1. + * On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a + * Samtec LSS-130 connector and requires the Toradex DSI Display Adapter + * to convert to FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + pwms = <&pwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt101hvlnwc00", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <71100000>; + de-active = <1>; + hactive = <1280>; + hback-porch = <64 64 64>; + hfront-porch = <36 36 36>; + hsync-active = <0>; + hsync-len = <24 24 24>; + pixelclk-active = <1>; + vactive = <800>; + vback-porch = <24 24 24>; + vfront-porch = <8 8 8>; + vsync-active = <0>; + vsync-len = <8 8 8>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_1p8v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + /* Rising edge avoids spurious interrupts from the noisy falling edge. */ + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_lvds_bridge_in>; +}; From 4bf5b8862fae3865069b34bdde2492e3e49f1810 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:31 +0200 Subject: [PATCH 127/131] arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 7" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 7" on the Verdin DSI_1 interface. The display features an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. The touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + ...x8mm-verdin-panel-cap-touch-7inch-dsi.dtso | 129 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 00dc2893c754..fe261d7bdab5 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -191,12 +191,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb @@ -216,6 +218,8 @@ imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-ver imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \ imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo +imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := imx8mm-verdin-wifi-dev.dtb \ + imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso new file mode 100644 index 000000000000..0e15b4b3f3ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 7" on Verdin DSI_1. + * On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a + * Samtec LSS-130 connector and requires the Toradex DSI Display Adapter + * to convert to FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-7-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + pwms = <&pwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt70hslnwca0", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <100 100 100>; + hfront-porch = <16 160 216>; + hsync-active = <0>; + hsync-len = <50 60 140>; + pixelclk-active = <1>; + vactive = <600>; + vback-porch = <23 23 23>; + vfront-porch = <1 12 126>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_1p8v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + /* Rising edge avoids spurious interrupts from the noisy falling edge. */ + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_lvds_bridge_in>; +}; From d4fc54ac184d036b51d1638a83f717269b86ddec Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:32 +0200 Subject: [PATCH 128/131] arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F remoteproc Describe the Cortex-M4F remote processor available on the Verdin iMX8M Mini SoM. Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 5fc177f589cb..ac450fc6cbfb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -52,6 +52,18 @@ hdmi_connector: hdmi-connector { status = "disabled"; }; + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, + <&rsc_table>; + syscon = <&src>; + }; + /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -164,6 +176,27 @@ reserved-memory { /* Use the kernel configuration settings instead */ /delete-node/ linux,cma; + + vdev0vring0: vdev0vring0@55000000 { + reg = <0 0x55000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@55008000 { + reg = <0 0x55008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@550ff000 { + reg = <0 0x550ff000 0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@55400000 { + compatible = "shared-dma-pool"; + reg = <0 0x55400000 0 0x100000>; + no-map; + }; }; }; From 0c4a972d869eff8070685c055b6a9366d6c63710 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:33 +0200 Subject: [PATCH 129/131] arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F UART_4 overlay Verdin UART_4 can be assigned to Cortex-M4F firmware. Add an overlay that marks the UART as reserved so Linux does not claim the port. The overlay is also combined with the Verdin iMX8M Mini Development Board device tree to provide a ready-to-use DTB for the WiFi SoM variant. Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 3 +++ .../dts/freescale/imx8mm-verdin-uart4-mcu.dtso | 14 ++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index fe261d7bdab5..95ae85ab4adf 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -192,6 +192,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-uart4-mcu.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb @@ -199,6 +200,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-uart4-mcu.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb @@ -220,6 +222,7 @@ imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin- imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := imx8mm-verdin-wifi-dev.dtb \ imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo +imx8mm-verdin-wifi-dev-uart4-mcu-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-uart4-mcu.dtbo imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso new file mode 100644 index 000000000000..8dbecffe9e7b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Verdin iMX8M Mini UART_4 for Cortex-M4F + */ + +/dts-v1/; +/plugin/; + +/* Verdin UART_4 */ +&uart4 { + status = "reserved"; +}; From 933bb140ffbd5015e940ea376a8c5c15b0fbf5d6 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 22 Jul 2026 17:00:44 -0500 Subject: [PATCH 130/131] arm64: dts: imx94-xspi: add the DMA channels Add the DMA channels for iMX94 XSPI controller. Signed-off-by: Han Xu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index dfbb73603cb2..34833e62bd79 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -827,6 +827,8 @@ xspi1: spi@42b90000 { #size-cells = <0>; clocks = <&scmi_clk IMX94_CLK_XSPI1>; clock-names = "per"; + dmas = <&edma2 27 0 0>, <&edma2 28 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -843,6 +845,8 @@ xspi2: spi@42be0000 { #size-cells = <0>; clocks = <&scmi_clk IMX94_CLK_XSPI2>; clock-names = "per"; + dmas = <&edma4 42 0 0>, <&edma4 43 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From eba4724641990bd9975ca10ababe726b6143f0b6 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 18 Jun 2026 17:20:59 +0800 Subject: [PATCH 131/131] arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe The current PCIe device tree configuration only defines the MSI interrupt, which is sufficient for basic PCIe operation but limits advanced functionality. Add the following interrupt lines to pcie0 and pcie1 nodes: - dma: DMA interrupt for PCIe DMA operations - intr: General controller events and link state changes - aer: Advanced Error Reporting interrupt - pme: Power Management Event interrupt This enables enhanced PCIe features and capabilities that were previously unavailable due to missing interrupt definitions. Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 305751046d66..38fc47024841 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1957,8 +1957,12 @@ pcie0: pcie@4c300000 { bus-range = <0x00 0xff>; num-lanes = <1>; num-viewport = <8>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + ; + interrupt-names = "msi", "dma", "intr", "aer", "pme"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, @@ -2044,8 +2048,12 @@ pcie1: pcie@4c380000 { bus-range = <0x00 0xff>; num-lanes = <1>; num-viewport = <8>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + ; + interrupt-names = "msi", "dma", "intr", "aer", "pme"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,