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dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property

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Add support for the optional rockchip,clk-lane-phase device tree property
to allow board-specific tuning of the clock lane sampling phase for
improved signal integrity across supported data rates.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Gerald Loacker 2026-07-25 18:56:04 +02:00 committed by Vinod Koul
parent 4fae43e33a
commit f82ff8609f
1 changed files with 10 additions and 0 deletions
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10
Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
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@ -56,6 +56,16 @@ properties:
description:
Some additional phy settings are access through GRF regs.
rockchip,clk-lane-phase:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
default: 3
description:
Clock lane sampling phase selection (hardware tap index 0–7). Each step
corresponds to an approximately 40 ps delay as described in the hardware
specification.
required:
- compatible
- reg