From f82ff8609f582ca5105e45f18dfc3e949dfeaef1 Mon Sep 17 00:00:00 2001 From: Gerald Loacker Date: Sat, 25 Jul 2026 18:56:04 +0200 Subject: [PATCH] dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property Add support for the optional rockchip,clk-lane-phase device tree property to allow board-specific tuning of the clock lane sampling phase for improved signal integrity across supported data rates. Acked-by: Rob Herring (Arm) Acked-by: Michael Riesch Signed-off-by: Gerald Loacker Link: https://patch.msgid.link/20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net Signed-off-by: Vinod Koul --- .../bindings/phy/rockchip-inno-csi-dphy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 03950b3cad08..913aa688c0ae 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -56,6 +56,16 @@ properties: description: Some additional phy settings are access through GRF regs. + rockchip,clk-lane-phase: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 3 + description: + Clock lane sampling phase selection (hardware tap index 0–7). Each step + corresponds to an approximately 40 ps delay as described in the hardware + specification. + required: - compatible - reg