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v7.3-rc1
12412 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
79b4f3baae |
MFD for v7.3
- New Support & Features
- MediaTek MT6397: Add mt6323 AUXADC support.
- MediaTek MT6397: Add mt6323 EFUSE support.
- Spreadtrum SC27xx: Add SC2730 regulator cell.
- Improvements & Fixes
- Apple SMC: Fix key count endianness annotation.
- Azoteq IQS62x: Reject zero-length firmware records.
- ChromeOS EC: Introduce cros_ec_read_features helper and read features during
probe to catch transfer errors.
- Cirrus Logic CS42L43: Fix regmap defaults ordering.
- Cirrus Logic CS42L43: Remove redundant NULL checks on SoundWire.
- Congatec Board Controller: Fix teardown ordering in cgbc_remove().
- HP iPAQ Micro: Fix out-of-bounds stack read in ipaq_micro_str.
- Marvell 88PM886: Initialize the battery page.
- QNAP MCU: Keep the reply buffer alive past a command timeout.
- RAVE SP: Validate received frame payload lengths.
- Silicon Labs Si476x: Drop duplicate NULL checks.
- Silicon Labs Si476x: Modernize GPIO handling.
- Silicon Motion SM501: Fix potential memory leaks during remove.
- UCB1x00: Convert Assabet gpio-keys to use software nodes and register software
node for GPIO controller.
- Viperboard: Fix native fields type in structures as little-endian.
- Viperboard: Remove redundant NULL check before kfree().
- X-Powers AXP20x: Preserve other control bits when powering off.
- Cleanups & Refactoring
- Core: Drop unused assignment of spi_device_id driver data.
- Core: Initialize spi_device_id arrays using member names.
- Core: Unify style of spi_device_id arrays.
- Maintainers: Add Intel LPSS section to follow the changes.
- Maintainers: Add a mailing list entry to MFD.
- Cirrus Logic CS42L43: Format sdw_device_id table.
- Cirrus Logic CS42L43: Use new SoundWire enumeration helper.
- ROHM PMIC: Factor out power button registration and convert gpio-keys to use
software nodes.
- ST-Ericsson DB8500: Fold dbx500 header into db8500.
- Device Tree Binding Updates
- Core: Add techvision vendor prefix.
- Marvell 88PM886: Allow vbus regulator.
- MediaTek MT8195 SCP: Add support for MT8189 SoC.
- Qualcomm SPMI PMIC: Document PMG1110.
- Qualcomm SPMI PMIC: Document haptics device.
- Qualcomm TCSR: Add compatible for Hawi and Maili SoCs.
- Qualcomm TCSR: Add compatible for Shikra.
- Qualcomm TCSR: Document the IPQ9650 TCSR block.
- STMicroelectronics STMPE: Fix typo st,stmpe601 (should be st,stmpe610).
- Syscon: Add ESWIN EIC7700 compatible.
- Syscon: Allow syscon compatible for Loongson-2K0300 chip id.
- Syscon: Disallow simple-bus with syscon.
- Syscon: Drop custom select for older dtschema.
- TI OMAP USBHS TLL: Convert to DT schema.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAmqPE0EACgkQUa+KL4f8
d2EwsA/6Ah511L+E+sH3PMz9/9ZR7F6b4xXx+YI0WuiWANNNEdxkkIiq6smdCQI9
oS//iJBdMigdKzjllIwnAHTcfatZE+3A6qCroM0pnxsQejDdAR0BP2VA4b7QMGg0
ey44e5CYZgRorh9oOTtsjE/jL4sNZK6AgyZab0gZ3Q/A5qubLRiSaphHfpfCej+q
RC3W2m3jbQSge5iNy8iIg41PH4fHcjpRNM/UxT6UVexxBWiJ6i9yiNYdfb4joCuG
Oh4Rr4TfnoN8yIuoA8WRngYejpV5ZGGnwXwTDl47WPvoJiMeWSnpQU0u/fSJARqm
YAMtZ+GLjSfj60SgCu6HR8AyH9q5U54pNdBiCSQ/7fGhYJwq9WS/XDjr+Xaj0+ku
g4veatMTMaNdwJr0RAViw1RAOA97cAqfgOADnlAJM/tzvGw0VjIxdrbciywUXB2A
At26ibT6WQX/I/fPSJqmwieEYiueikZfvuLFYAeSrLQ4GWGGgq3Aj4k1LtOVLEP3
y3Pt4rkxJQxW3EDKseaZYsyR7EbU3PnJFTsAY0/p1XiDSeiM4d0IIi7dZQiQygg4
3XwmqE8ODxetHna+dPXr0ooaU9UIaaT1X5AyOr6t6Tp/n0Yq50F1PpjBCS2nLAYk
JdkgfFBMWlkOZcCTgLYMKNSnmWZihUxb0zfDaOMCe4HUoqc1WLA=
=92XF
-----END PGP SIGNATURE-----
Merge tag 'mfd-next-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Support & Features:
- MediaTek MT6397: Add mt6323 AUXADC support
- MediaTek MT6397: Add mt6323 EFUSE support
- Spreadtrum SC27xx: Add SC2730 regulator cell
Improvements & Fixes:
- Apple SMC: Fix key count endianness annotation
- Azoteq IQS62x: Reject zero-length firmware records
- ChromeOS EC: Introduce cros_ec_read_features helper and read
features during probe to catch transfer errors
- Cirrus Logic CS42L43: Fix regmap defaults ordering
- Cirrus Logic CS42L43: Remove redundant NULL checks on SoundWire
- Congatec Board Controller: Fix teardown ordering in cgbc_remove()
- HP iPAQ Micro: Fix out-of-bounds stack read in ipaq_micro_str
- Marvell 88PM886: Initialize the battery page
- QNAP MCU: Keep the reply buffer alive past a command timeout
- RAVE SP: Validate received frame payload lengths
- Silicon Labs Si476x: Drop duplicate NULL checks
- Silicon Labs Si476x: Modernize GPIO handling
- Silicon Motion SM501: Fix potential memory leaks during remove
- UCB1x00: Convert Assabet gpio-keys to use software nodes and
register software node for GPIO controller
- Viperboard: Fix native fields type in structures as little-endian
- Viperboard: Remove redundant NULL check before kfree()
- X-Powers AXP20x: Preserve other control bits when powering off
Cleanups & Refactoring:
- Core: Drop unused assignment of spi_device_id driver data
- Core: Initialize spi_device_id arrays using member names
- Core: Unify style of spi_device_id arrays
- Maintainers: Add Intel LPSS section to follow the changes
- Maintainers: Add a mailing list entry to MFD
- Cirrus Logic CS42L43: Format sdw_device_id table
- Cirrus Logic CS42L43: Use new SoundWire enumeration helper
- ROHM PMIC: Factor out power button registration and convert
gpio-keys to use software nodes
- ST-Ericsson DB8500: Fold dbx500 header into db8500
Device Tree Binding Updates:
- Core: Add techvision vendor prefix
- Marvell 88PM886: Allow vbus regulator
- MediaTek MT8195 SCP: Add support for MT8189 SoC
- Qualcomm SPMI PMIC: Document PMG1110
- Qualcomm SPMI PMIC: Document haptics device
- Qualcomm TCSR: Add compatible for Hawi and Maili SoCs
- Qualcomm TCSR: Add compatible for Shikra
- Qualcomm TCSR: Document the IPQ9650 TCSR block
- STMicroelectronics STMPE: Fix typo st,stmpe601 (should be
st,stmpe610)
- Syscon: Add ESWIN EIC7700 compatible
- Syscon: Allow syscon compatible for Loongson-2K0300 chip id
- Syscon: Disallow simple-bus with syscon
- Syscon: Drop custom select for older dtschema
- TI OMAP USBHS TLL: Convert to DT schema"
* tag 'mfd-next-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits)
mfd: cs42l43: Fix regmap defaults ordering
dt-bindings: mfd: syscon: Allow syscon compatible for Loongson-2K0300 chip id
dt-bindings: mfd: syscon: Add ESWIN EIC7700 compatible
mfd: qnap-mcu: keep the reply buffer alive past a command timeout
dt-bindings: mfd: qcom,tcsr: Document the IPQ9650 TCSR block
mfd: macsmc: Fix key count endianness annotation
dt-bindings: mfd: qcom,spmi-pmic: Document haptics device
mfd: iqs62x: Reject zero-length firmware records
mfd: rave-sp: validate received frame payload lengths
mfd: sm501: Fix potential memory leaks during remove
mfd: viperboard: Fix native fields type in structures as little-endian
mfd: si476x-i2c: Get rid of duplicate NULL checks
dt-bindings: mfd: Convert OMAP USB TLL to DT schema
mfd: cgbc: Fix teardown ordering in cgbc_remove()
mfd: mt6397-core: Add mt6323 AUXADC support
dt-bindings: mfd: qcom,tcsr: Add compatible for Hawi and Maili SoCs
mfd: rohm: Factor out power button registration
mfd: ucb1x00: Convert Assabet gpio-keys to use software nodes
mfd: ucb1x00: Register software node for GPIO controller
mfd: cs42l43: Tidy up formatting on sdw_device_id table
...
|
||
|
Linus Torvalds
|
502d45774a |
Mostly the usual clk driver updates and new SoC additions plus non-critical
data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lead, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmqPGK4UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSXB+g/+O8McZyE7kqNPiz8nQNQq9YwzO9uB /5LkNUUvvxhzJ9YEcXx8HCkmUcAks+kMCHzrZ/gxAN6BQGv9qrTChZZD2ZmD8e50 nj3IxyvN51PwRk5ley1PEsUILrnOqRpY6g83arnFppTP2aU/NxFFGjc5u+5qlIT4 f0xj2sJ0H96Ykw+brSJgEj9MXJHMEKerEqBmaDd0boHavDV3YkT/HxRrjy3WH/sE FBAdq6sOAEX3qnNwsF9debrfg1nKJGH2U8ecb1JThlAufn8yHvC+mxr3P4USxdov xGhDkvKbS+9nkbxeL1LOhnoReOWqNBGQg9qmadQKTrPEu/BAOb8nG62xpucIgLSl 6X3AACRzEE8u8Thaboz+cvQluQfOo667xz5X+bpTsQjfQuq4Yh0F4pO6pLmLd+LT NdOzbQctglbpwHbXIxXQftg+Fnk1bgERILW64DU9mUqXzSJJG9uzv+Ne5R0TTXJp TMRTp/o8o4Fclr1WB73wES523xpf7VltPfUw5XL9UN2xCCY5TI2bpHQwgfmkz/6J nHmxNBBK19qlNFzDovN1gfgwn9XVDLmT7YVSw0El24kINHs7rYXuGc++OX+LmUb3 r19QxJXU8ESV89ZGJYhnaSOKrCj1d4W49AkVqovvJXXYxxlFTab1ox8xKnhUlxGH SGDC+kZah2zUl7A= =iYa8 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include <linux/mod_devicetable.h> clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... |
||
|
Stephen Boyd
|
dd8eb789f1
|
Merge branches 'clk-pile' and 'clk-microchip' into clk-next
* clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper |
||
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Stephen Boyd
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5d650f824d
|
Merge branches 'clk-imx', 'clk-rockchip', 'clk-samsung', 'clk-qcom' and 'clk-allwinner' into clk-next
* clk-imx: clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 clk: imx95-blk-ctl: Add func_out_en clock for i.MX9x PCIe clk: imx: imx8qxp: add missing MODULE_DEVICE_TABLE() clk: imx: imx8qxp-lpcg: add missing MODULE_DEVICE_TABLE() clk: imx: Add audio PLL debugfs for K-divider control * clk-rockchip: clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src * clk-samsung: clk: samsung: Don't include <linux/mod_devicetable.h> clk: samsung: pll: use kzalloc_flex clk: samsung: cpu: use kzalloc_flex clk: samsung: use kzalloc_flex clk: samsung: exynos990: Fix PERIS gate clock parents clk: samsung: exynos990: Add PERIS TMU_SUB_PCLK gate dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLK * clk-qcom: (94 commits) clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra clk: qcom: Return expected ENOMEM error on dynamic allocation failure clk: qcom: apss-ipq-pll: Add IPQ5210 support dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible clk: qcom: Add support for videocc driver on Qualcomm Maili SoC dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gpucc-qcm2290: Drop pm_clk handling clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs clk: qcom: dispcc-qcm2290: Enable runtime PM support clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC ... * clk-allwinner: clk: sunxi-ng: sun6i-rtc: add a733 support clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate clk: sunxi-ng: div: add read-only operation support clk: sunxi-ng: mux: fix determine helper rate propagation clk: sunxi-ng: mux: remove unneeded export clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration clk: sunxi-ng: sun6i-rtc: clean up DT usage clk: sunxi-ng: fix ccu probe clock unregister on error dt-bindings: rtc: sun6i: add sun60i-a733 support dt-bindings: rtc: sun6i: no clock-output-names on h616/r329 |
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Stephen Boyd
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a1476addb4
|
Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next
* clk-renesas: clk: renesas: Add R-Car X5H CPG driver dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator clk: r9a08g045: Add clocks and resets for CAN-FD dt-bindings: clock: renesas,versaclock7: Update maintainer clk: renesas: r9a09g047: Add LVDS clocks and resets clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations clk: renesas: r9a08g046: Add USB2.0 clock and reset entries clk: renesas: r9a09g077: Add RTC clocks clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC clk: renesas: r9a08g046: Add clock and reset entries for GE3D clk: renesas: r9a08g046: Add clock and reset entries for SDHI clk: renesas: r9a09g047: Add audio clock and reset support dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID * clk-thead: clk: thead: allow COMPILE_TEST builds * clk-mobileye: clk: eyeq: Add EyeQ7H compatibles clk: eyeq: Drop PLL, dividers, and fixed factors structs clk: eyeq: Convert clocks declaration to eqc_clock clk: eyeq: Introduce a generic clock type clk: eyeq: Prefix the PLL registers with the PLL type clk: fixed-factor: Export __clk_hw_register_fixed_factor() clk: fixed-factor: Rework initialization with parent clocks reset: eyeq: Add EyeQ7H compatibles dt-bindings: soc: mobileye: Add EyeQ7H OLB * clk-amlogic: clk: amlogic: Add A9 peripherals clock controller driver dt-bindings: clock: Add Amlogic A9 peripherals clock controller clk: amlogic: Add A9 AO clock controller driver dt-bindings: clock: Add Amlogic A9 AO clock controller clk: meson: align gxbb_32k_clk_sel number of parents with actual count * clk-spacemit: clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers clk: spacemit: k3: fix i2s clock topology dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs clk: spacemit: k3: Add UFS refclk clock dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk clk: spacemit: k3: fix parent clock of UFS aclk |
||
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Pedro Kopper
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fbfa013eea
|
clk: microchip: mpfs: fix regmap_update_bits() mask/val order
mpfs_cfg_clk_set_rate() passes the mask and value arguments to
regmap_update_bits() in the wrong order. The resulting write becomes
reg = orig_reg | val, causing bits to not be cleared if the clock
divider changes.
Pass the arguments in the correct order so the divider field is updated
as intended.
Fixes:
|
||
|
Geert Uytterhoeven
|
39c0e6c844
|
clk: visconti: Make sure clk_init_data is fully initialized
The clk_init_data structure contains several mutually-exclusive members
for different methods to specify the possible parents of a clock,
prompting drivers to initialize only the members they need. However,
not initializing all members may cause subtle issues, which are only
exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is
enabled.
visconti_clk_register_gate() fills in init.parent_data, and assumes that
init.parent_names is NULL. However, the latter in uninitialized, and
thus may cause a crash.
Make sure all members are fully initialized, to fix such bugs, and to
avoid future breakage when converting drivers to a different method for
specifying the parents.
Fixes:
|
||
|
Geert Uytterhoeven
|
3ae1674975
|
clk: ti: Make sure clk_init_data is fully initialized
The clk_init_data structure contains several mutually-exclusive members
for different methods to specify the possible parents of a clock,
prompting drivers to initialize only the members they need. However,
not initializing all members may cause subtle issues, which are only
exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is
enabled.
_register_mux() fills in init.parent_data, and assumes that
init.parent_names is NULL. However, the latter is uninitialized, and
thus may cause a crash.
Make sure all members are fully initialized, to fix such bugs, and to
avoid future breakage when converting drivers to a different method for
specifying the parents.
Fixes:
|
||
|
Linus Torvalds
|
ee1b6365f0 |
pmdomain providers:
- amlogic: Add support for A9 power domains
- bcm: Raise ASB poll timeout to 100us for bcm2835-power
- imx: Allow building power domain drivers as a modules
- mediatek: Add support for the MT6858 power domains
- mediatek: Add support for the MT8196 HFRP DirectCTL power domains
- qcom: Add support for RPMh power domains for Maili
- qcom: Skip retention by default for rpmhpd
- renesas: Add support for R-Car X5H Module Controller
- rockchip: Add a regulator to the RK3568 NPU power domain
- tegra: Add support for multi-socket platforms
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAmqC8RYQHHVsZmhAa2Vy
bmVsLm9yZwAKCRD+JoQlc1iMKYloEADS2kGT/z2l2NgivbXZFvz0RSNRG18nIpML
6HwJd0qKr5r+U9mpIkfwvHzI3BQGYWOAt0P8y9Wrf+b32lBoDeZqKAB7N7NSOOB7
FhNHeI+U1BIKoDxjuh/zWlHpwTAIbVDdiEJnBk1uGiG5ydco/CmwaQnDNnJywJfz
dsfiDM1q+okolagNxx+VzhvRaxgSqvGBiX52CAMJmcmiIXIlfNTMKK9rnQRhD3lh
kfhSnZYRQwtl7MQ7990vULYrINxAidU4KIoRnCPSJ+eA7Rl2udtsiEdQYdFba6C5
lzEhHzgDWN9YTExCHFhy/vLOWbehoW/z6Jfz3m/Lxmkv7Zd37t3SuMj/0KnPCrpM
Vtg8ZirqG1hvhihcoUpk20jR7LlUGcX1k5ipsP/ptj8uVkdHKVzen6bHy2FvpMle
bYNRWwd8TKqYxAGsxEMZ59GRpRdIRowFSUAOmcP09b5CI8wslkljpmZWZgBxk1f8
31CpmIDMIIxuYY3m0GR5CHlcAXxZO7N+5kk7AqBgDh1IXKf1/CcvgABetAMcJl07
jcUfBBaZDA64ulzqnAEclW+xjITX5+qONVjEy5D/JORo89ttbYaAKyL10BrAb2lm
WbkAP3R15ueHAKsE9Q6xMZ66V3qJxdF9wqmq3f/4TE+QRntDzvE/KMhCjxG5LOJ4
I1Bb9v3rYA==
=6EOE
-----END PGP SIGNATURE-----
Merge tag 'pmdomain-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
- amlogic: Add support for A9 power domains
- bcm: Raise ASB poll timeout to 100us for bcm2835-power
- imx: Allow building power domain drivers as a modules
- mediatek:
- Add support for the MT6858 power domains
- Add support for the MT8196 HFRP DirectCTL power domains
- qcom:
- Add support for RPMh power domains for Maili
- Skip retention by default for rpmhpd
- renesas: Add support for R-Car X5H Module Controller
- rockchip: Add a regulator to the RK3568 NPU power domain
- tegra: Add support for multi-socket platforms
* tag 'pmdomain-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (24 commits)
pmdomain: renesas: Add R-Car X5H MDLC driver
dt-bindings: power: Document Renesas R-Car X5H Module Controller
pmdomain: amlogic: Add support for A9 power domains controller
dt-bindings: power: Add Amlogic A9 power domains
clk: imx: imx8qxp: add soft dependency on SCU power domain driver
pmdomain: imx: scu-pd: allow building as a module
of: export of_stdout symbol
pmdomain: imx8m{p,}-blk-ctrl: Add MODULE_DESCRIPTION
pmdomain: mediatek: Add support for MT6858 SoC
pmdomain: mediatek: Add support for secure modem power domain control
dt-bindings: power: Add MediaTek MT6858 power domain controller
pmdomain: rockchip: Add a regulator to the RK3568 NPU power domain
pmdomain: imx: Make IMX8M/IMX9 BLK_CTRL tristate
dt-bindings: power: qcom,rpmpd: document RPMh power domain for Maili
pmdomain: tegra: Add support for multi-socket platforms
pmdomain: bcm: bcm2835-power: Raise ASB poll timeout to 100us
pmdomain: mediatek: Add support for MT8196 HFRP DirectCTL domains
pmdomain: mediatek: Add support for Direct CTL simple power sequence
pmdomain: mediatek: Respect PD relationships during error cleanup
dt-bindings: power: mediatek: Add support for MT8196 direct HFRP
...
|
||
|
Mathieu Dubois-Briand
|
fe3dd92ac5
|
clk: ti: composite: resolve parent clocks by DT index, not by name
Resolve parent clocks by their index into the device tree "clocks" property rather than matching names as strings. This makes it consistent with other parts of the same driver. Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Mathieu Dubois-Briand
|
667f420c09
|
clk: ti: mux: resolve parent clocks by DT index, not by name
Resolve parent clocks by their index into the device tree "clocks"
property rather than matching names as strings. Name-based matching is
fragile because a clock's "clock-output-names" value in its provider
node can differ from the name used to reference it in a consumer node,
and because names must be globally unique across all clock providers.
On AM335x, this caused broken clock trees where some clocks failed to
enable because their parents could not be found.
Replace of_clk_parent_fill() with a clk_parent_data array that sets
.index to the array position.
Fixes:
|
||
|
Onur Özkan
|
0d4d262c16
|
clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
devm_clk_get_optional_enabled_with_rate() registers its cleanup action
before setting the clock rate. If setting the rate fails, it attempts to
disable and unprepare a clock that was never enabled. This issue was
spotted while reviewing "rust: clk: add devres-managed clks" [1].
Register the cleanup action only after successfully preparing and enabling
the clock.
[1]: https://lore.kernel.org/rust-for-linux/20260706-clk-type-state-v5-3-67c5f326a16c@collabora.com
Fixes:
|
||
|
Babanpreet Singh
|
3cf908dd13
|
clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
Commit
|
||
|
Stephen Boyd
|
df822f2e36
|
Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile
Pull clk patches from Brian Masney: - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS), UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree bindings. Si549 support was added to the existing si544 driver. - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha EN7523 PCIe PERSTOUT reset lines. - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to the existing optional variant, and exports devm_clk_hw_register_composite_pdata() for modular drivers. - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1 support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL charge pump/lock parameter programming during dynamic reconfiguration. - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on registration failure, a prepare reference leak in the palmas driver, unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a clocking-wizard clock difference detection bug. - Various cleanups across tegra, st, and mvebu providers to stop misusing the consumer clock API, along with other minor fixes and improvements. Signed-off-by: Brian Masney <bmasney@redhat.com> * tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits) clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 clk: aspeed: add AST2700 PECI clock dt-bindings: clock: ast2700: add PECI clock clk: mediatek: Add mt8173-mfgtop driver dt-bindings: clock: mediatek: Add mt8173 mfgtop clk: tegra: clean-up simple provider misuse of the consumer API clk: st: clean-up simple provider misuse of the consumer API clk: mvebu: clean-up simple provider misuse of the consumer API clk: remove conditional return with no effect clk: Add devm_clk_bulk_get_enable() clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT arm64: dts: cix: sky1: add audss cru reset: cix: add sky1 audss auxiliary reset driver ... |
||
|
Stephen Boyd
|
804b10deb0 |
clk: various improvements and fixes
Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQSkbTJwWGWqPd7cKQS30t0nXX7AhwUCakLuwRYcbWFzbmV5YkBv bnN0YXRpb24ub3JnAAoJELfS3SddfsCH1qIA/3OYdBm1fIrd/PumuFj/6xnito0J nwY64dzlOm4kPVynAQDGDUxQMevRq8AFXh33kOh+cCFg7H9CXjF55ajB2TXaBg== =1BFM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmqDNnUUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSU1oxAAiKegvy9n27Avul9t7GX9SYpyM93E XXvr3kdI6ySTkAk/CXqSUKLS0FnqMepQE6b1FSiRQGOyPl0iYxXFKZ3iwd5ZHHIN AWWwXYhzAuwOXNnNzlz3SFJ40lt8zTLY4Y20sG3/+iuIiqotywONWqr1JlUwlgVI ahmGqWPj2qtuKCnxnOQnBNcaA/xd3NqdjHt0W1UgXP9Hn9j0l+EhL7f4TJVp4Wq5 LU+jlA7g6Btxy5JrJOpzdgd84bPNw4xxYOhzn3ek8ULB5H0QRj36cu2ZahNudZJF ObIr23OOgRJLZtKQ/WlM5fHXONuhnE9CSTiBEeXSr2yon0JKcJ8bjKUvTilJhZ34 TV5DSBxB70E0Vs4omJJ0NtKsJWW+zoa53yU2mT88VWQNTDLfTe4VHVbBCBN9cBnV aS8ssQF9uipsOKEGQ1aQG9neV2ML0OXd3nMx9f8VgMcfV5K8Wbtt5oRFtQtl5fS/ uCkTbII+IL29MMVJ6+X3sRilFY8SsKxaG1gDmk50LwcMUVx4hzNGOhQC/1TPRNG2 ZuSEeRX10syBwI5txupnxD1mJClw2ZxE9QmSTmKmWI1Y3aSdcSdtKnEobhLXJmmS 7PFtOe9Rf8lRbYKxZGaW63R/9fOmrf3wyG9kzepLKJl8loV7SRJ8by6psNBfBgVO kyANlk/27dpi1Zo= =QbCr -----END PGP SIGNATURE----- Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile Pull clk patches picked up by Brian Masney: Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> [sboyd@kernel.org: Fix allmodconfig modpost failure in scmi] * tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits) pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop() pmdomain: mediatek: airoha: use clk_determine_rate_noop() phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop() clk: sprd: use clk_determine_rate_noop() clk: scpi: use clk_determine_rate_noop() clk: samsung: acpm: use clk_determine_rate_noop() clk: rp1: use clk_determine_rate_noop() clk: renesas: rzg2l-cpg: use clk_determine_rate_noop() clk: qcom: smd-rpm: use clk_determine_rate_noop() clk: qcom: rpmh: use clk_determine_rate_noop() clk: qcom: rpm: use clk_determine_rate_noop() clk: imx: scu: use clk_determine_rate_noop() clk: hisilicon: hi3660-stub: use clk_determine_rate_noop() clk: add clk_determine_rate_noop() clk: imx: scu: drop redundant init.ops variable assignment clk: test: convert constants to use HZ_PER_MHZ docs: clk: include some identifiers to keep documentation up to date clk: add kernel docs for struct clk_core clk: add kernel docs for the core flags clk: hisilicon: allow COMPILE_TEST builds ... |
||
|
Uwe Kleine-König (The Capable Hub)
|
53cb675d72
|
clk: samsung: Don't include <linux/mod_devicetable.h>
All users of drivers/clk/samsung/clk.h live in drivers/clk/samsung (see
git grep samsung/clk.h
). All these are only using of_device_id from
the set of structures defined by this include (see
{ git grep -l clk\\.h drivers/clk/samsung/; echo drivers/clk/samsung/clk.h; } | xargs grep -oh -E "\<(acpi_device_id|amba_id|ap_device_id|apr_device_id|auxiliary_device_id|bcma_device_id|ccw_device_id|cdx_device_id|coreboot_device_id|css_device_id|dfl_device_id|dmi_(device|system)_id|eisa_device_id|fsl_mc_device_id|hda_device_id|hid_device_id|hv_vmbus_device_id|i2c_device_id|i3c_device_id|ieee1394_device_id|input_device_id|ipack_device_id|isapnp_device_id|ishtp_device_id|mcb_device_id|mdio_device_id|mei_cl_device_id|mhi_device_id|mips_cdmm_device_id|of_device_id|parisc_device_id|pci_device_id|pci_epf_device_id|pcmcia_device_id|platform_device_id|pnp_(card_)?device_id|rio_device_id|rpmsg_device_id|sdio_device_id|sdw_device_id|serio_device_id|slim_device_id|spi_device_id|spmi_device_id|ssam_device_id|ssb_device_id|tb_service_id|tee_client_device_id|typec_device_id|ulpi_device_id|usb_device_id|vchiq_device_id|vio_device_id|virtio_device_id|wmi_device_id|x86_(cpu|device)_id|zorro_device_id|cpu_feature)\>" | sort | uniq -c
).
So <linux/mod_devicetable.h> can be replaced by <linux/device-id/of.h>
to get rid of another user of the former header.
Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||
|
Stephen Boyd
|
fb96dea9cf |
Microchip clock updates for v7.3
This update includes: - use of_property_read_reg() instead of of_property_read_u8() to properly parse the reg DT property -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCanwNUQAKCRCejrg/N2X7 /c7UAP94EFEZVWabWmwTrZRFn0gYyM6hy44suT5q3i5L/Ga9GgEAxwkaIilVSmTk G7R4fS8e12222dtlkTQqRnHxiGxh4wY= =gD4j -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp+ecoUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSXLtg/+O55nxvbOWWGU9WkW2eH6wHwDc+kX YnWbXnRYOZjdZ3tcQvQxGbbboBgu5j0gt2UoBZeFTlu4wf2iJM4KaPQEanpeeSf9 Rr1BroJnRUVqNtaDIekXdagxOUeaH1ProTNPCc1RHbRIl53XDF3vBambKQe2Mm/N SvzW6pgcxyqMNq01o2GRHoj7RpIskzDqQFqzuMY9GpR8Dt9HEivwM1E/sFKl9riI xUWcReASsqNT6BstviSemlPXQ2CBEBxTTiDOsRx9QlbRr70ArTGWyRqWVnjVz/9/ JY6yaQ8X83nTWw6XkJk5qTuWNHYo4PpXXwGvu3SLeWmjCPc5HJh7u5zWz9Y2ckRL RYATzbm6tMfy+Ik79b1hBHdhNxoV7/uwnPPhweyW0DpLDmgoBpZqrcDvLlnAYsL8 S9XQOteeYAzeqfmoS25R3zmtjmTTovBqJURuUt3DKR+YXjRCRxui006olfSXcwj2 D0xLHx+MpTZXKa0pLOnh/2vztX9kfUGaaN1floAFz48RR/+07EdSBB0TTYaGDs97 zZWgN+n5dy7YnlHzAvVNkVgkAtXAQvgBNv3KvbNPCWU14TYYF9PJ9wJMNs/1XFev RIJChx+NEKyc/wD7loPXyRGZugxUbemQx/41UcfjO/uJFRCltg9Js/0olOKTT7Tt jqluJdZDoov3vmw= =HV0C -----END PGP SIGNATURE----- Merge tag 'clk-microchip-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: - use of_property_read_reg() instead of of_property_read_u8() to properly parse the reg DT property in the microchip driver * tag 'clk-microchip-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: Read "reg" with helper |
||
|
Stephen Boyd
|
d8a8d206a7 |
Allwinner clock changes for 7.3
Some cleanups to the Allwinner clock driver library and support for the Allwinner A733 RTC clocks added. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmp4YtEQHHdlbnNAa2Vy bmVsLm9yZwAKCRA4mlQhnA8kMOIFEADkvYPkegyGZWpVRlRuvV1mzE0Uc16Ueo4G jisA5FSjOOjR1v8JcG16gvX0uvllWBTyHRQUJ/4VRexedRcL/QQewID7kZ4Ebh+M BGuSbEHiPUqLTDO0j9mNE5Cu6fmIvrMSCyffxFqCbmhfvb5XiCIPeNtA9Q9V18dK UMSIh9NUU2JKINnJJnBpL/3akPxUDUEBRx2MfuW85hb/0irsWaYAGEToFLNBYBhf r5QUcXnrMgV7mvFPLHjG0TytPWRDTiNR/aXlXtPuLPx7TgTuKMSwt2b7mGv7+kz0 rPooPw48TfpFVoGmBx22FmD4BJuHyi8BUTQfWluSpw+MZpwmURYDhfQiyPjPASAC nSDWIFL5s0i/R2Gtql+sbqpY3zDADxta/jRsUG/0azEALjcVNNuWWr9f/h0QxiDB MRLrUFKRx6TwQBSgyMRkk43wA0pWKn9koZaB1FFu3if03heRk/Qt/YOcg7mp0xP7 EW0PZfKq3GXBWtcQ0UlC6jOzF+X0MFWlNCOSxkNR460H+K2jQdMaU+rUx0N1qXnA qN9uoMzukXd9x6GazWDA4tOfbc6fYSQ8R40EQNLsrjCaYq6gf/ED1V83D60/2TnM 8rpxDagwTLndtT+oO2DkCEk60XVpnRodkyzLXlQ+wHNF0FjddDA/I29QLAcN5bvl kjsWWCFtTw== =1HWO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8DggUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSXnBQ//fyZ0fFm5sAO5Dl4/d52hbv4i4SLa Wv/R+dEbrHrMlU5Vd1WSHImf0XqG97MZNlGlNor3fcM98Z9bQo3NZFOGTUkjJs6W yJGs/68mJpZvfqYHBXBk+PlYBDD7ULNOAgz8TSsrjuLS0ehpvmI40eYhcczqZLqe wupz/upveK81a9qDQfpfrIF7pb5Xf57YTQnkFRJkrL7Jyhu6+jSp0YhnqXpTOz+w RtPqHGSl+kquLPGgmzZmDS2lUZfRr/MrEbP2LsEhoqK2rBLQGnoYYtxlBBDKgtdc VEjpsp3dk8TnckgAZZF+Az13PoOYIXXP6EoSez+V5UANGCXjxB+Xh1JNdGmsYF5+ awI6fjlND8xKsGGz5tKMvZXuqf1a+cF8sqqI0cJ6roLN7DUQEc2lSPN5Ao6eaw+A ljV7hUe/7RyIS1rvJtMVy60g6+9hqGPtQqqM8xV+2brCguL/sj6aW16P9ZEy+wvv LLJev2Ojt0I2JCwyYkDqCX8EefNfZGFAVe3+fUUunNHahQjXlCv1IWe6vqbI78dR uTWP9n3ohTozg4PNDSxjOZxQaueGL6ZTfBwLTrXk6tVo4Q4pawMH0q+VIvr3Hzc7 ifOK5/NN6oq/dAfXIukRFBXdGSGRyMNt7sYfq9r2CxGP/9NqeF4g9H2Uxotu0q5C YyLtNcH2+pTsUUE= =3i3v -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Chen-Yu Tsai: Some cleanups to the Allwinner clock driver library and support for the Allwinner A733 RTC clocks added. * tag 'sunxi-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun6i-rtc: add a733 support clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate clk: sunxi-ng: div: add read-only operation support clk: sunxi-ng: mux: fix determine helper rate propagation clk: sunxi-ng: mux: remove unneeded export clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration clk: sunxi-ng: sun6i-rtc: clean up DT usage clk: sunxi-ng: fix ccu probe clock unregister on error dt-bindings: rtc: sun6i: add sun60i-a733 support dt-bindings: rtc: sun6i: no clock-output-names on h616/r329 |
||
|
Stephen Boyd
|
79b64c7476 |
Qualcomm clock updates for v7.3
Add global, TCSR, RPMh, and video clock controller support for Maili. Add global, RPM, GPU, display, and audio core clock controller support for Shikra. Add display and graphics clock controllers for Nord. Add Glymur camera and EVA clock controllers, the IPQ9650 REFGEN clocks, and Hawi video clock controller support. Extend the IPQ5210 APSS PLL and RPM clock support for Agatti. Enable runtime PM and regulator-backed reference clock handling where needed. Update QCM2290 clock and power-domain handling, critical clock definitions, and arm architecture Kconfig defaults. Correct MDM9607, MSM8916, MSM8939, SM6115, QCS8300, Kaanapali, and Glymur clock and power-domain handling. Improve GDSC error propagation and teardown. Update bindings for the added controllers and required power and OPP properties. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmp2AIsOHGJqb3JuQGty eW8uc2UACgkQCx85Pw2ZrcVp1Q/8DSFhshwLJ7BxaKUyYcoL0oCzRRMoH5U3UEw6 9iYM+bGbeNSguZW5d3fKQhOX4EHULk/nOHuP3nril1jeOUCMZlF6BaZcFaWxQN8I E26T3STNS1JYyQDGzUMAc9mL44nV/XfurA6w0BCkwGHZ4kFmgBJHWn8ns9jaxW6z jlTg9aUwm/omId3pkuB6LY0A7oTBOX8Vul/i+6CAh5JXr7JL2M+gU9rnqnNVJ2ug PX+m7phzZNaflVK6GsUP4TI/CPqgPWyeeccA/POQ4xkREwivZb8VpaV9LKPqqSmY 3SJ3bNaBd0nadsHoJiEbBflCWx88eMAXuXhMGHsxveA1KoTaxBJVDK3nzEqulobN xdLd9XXA+OJ9fMT3rVxmupldbkPlfxH1NIIxtSlAZlMb10SBo0O7S4EyzWisHSfP S5wFTprc3NLnqfHa+14inleIOqRGLRbHe2hb2dJRxv8Nxv0u82VGe0xEOk0oHgjS i60Sm8Hl81svH+sxICVBPDZ7JEH9FY3mHNav/DDcBbX9Bukg7xybgOonP5Y4K3E4 fAGU8T1SMRe3u+dsZmjR07ZFmEQgevefE8diDA8Z/bpND/HOWsjBILMUcz87aaYt YVu9BE+mOzIektehQcLsRkgmP15xLuCOEfpeL46I8mNEWPgfl1jfVyjEdFs2BFcn Rkj+acY= =1e93 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8Dc4UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSUQihAAwkz9Uc6w+wI4IuD1aGOcnj1/SQOe vFaylCwhUDb85ryx2TrwmXDAorxt1kPxVYGSNCmwTUP3KamDxtDIdqdxdB7AsKnq SNFe2JOx0pFDtGOKRqG3hCiml3GlIMzQQmbXCXKxPLK6NaVxNZwaJzrqhfMiJqji tGNWxllEMws82jWJ8N20+OLkpPcfV9CGxPwWFU6G+IrZpbmhCuzXqbaHOExQy2vz xMdcYRkVTZy4elI1ab6OTc3wQyu3zPL5dwBpTuWdbxLIvVbQChcgn9VGb9BITlBG +H8M9f5fzBkEkbI8m1l0wUm5mBfLiD+b4E72Y0UYMKsGp7oiJZCz/Tdm2eTdile7 IjhbOksiqJA824iN1AKtS1pqImmDkKJHHQcSHh7tANceFz+BkL4av4/pkrE3e6mu WZ7SoMQuWdXQuhnwzqnr0IOttKMmlBYvzdH+7tJ5IseM5kihXD/JugqqEA0lC7Rs 4BUbmV09Snrx/06EmIs7E4MNprPAiN//AjstmJOJli2eZYKBnccpXCWG/VQ7GkJ+ k5pkcGVjFMKtXUFwd4cgnTB8PQTdeF9f6nde6jjX42sD72qESLqqRpykj5UCg+D1 zfZMvBQMbgdjVVx0IbsgkFWtO6rDn6cbNjluAjPTIiXcnE2ckCv5wSpDlxIE3K28 dBIq1TQFxXKgLlk= =Ge5l -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: Add global, TCSR, RPMh, and video clock controller support for Maili. Add global, RPM, GPU, display, and audio core clock controller support for Shikra. Add display and graphics clock controllers for Nord. Add Glymur camera and EVA clock controllers, the IPQ9650 REFGEN clocks, and Hawi video clock controller support. Extend the IPQ5210 APSS PLL and RPM clock support for Agatti. Enable runtime PM and regulator-backed reference clock handling where needed. Update QCM2290 clock and power-domain handling, critical clock definitions, and arm architecture Kconfig defaults. Correct MDM9607, MSM8916, MSM8939, SM6115, QCS8300, Kaanapali, and Glymur clock and power-domain handling. Improve GDSC error propagation and teardown. Update bindings for the added controllers and required power and OPP properties. * tag 'qcom-clk-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (94 commits) clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra clk: qcom: Return expected ENOMEM error on dynamic allocation failure clk: qcom: apss-ipq-pll: Add IPQ5210 support dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible clk: qcom: Add support for videocc driver on Qualcomm Maili SoC dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gpucc-qcm2290: Drop pm_clk handling clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs clk: qcom: dispcc-qcm2290: Enable runtime PM support clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC ... |
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Stephen Boyd
|
e38dc76404 |
Samsung SoC clock drivers changes for v7.3
1. Exynos990: Add few missing clocks and correct the gate clock parents
in the PERIS clock controller.
2. Cleanup - Use kzalloc_flex for __counted_by checks.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmp0Q9oQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD15DYD/913hNrlwksCT1sCnY+yye76h8HTLrO7zqo
wFJdkbfhNlXDRpAw130sgGS2YZ0ed8AsIhD0cmjZQeXw8Wrdds7itymr26mqtot4
6QcZB0FEbuMSo4JM9S7Dx6jQIfyPmophDSbi4OzS9L1IY/r1cJb9B0TV3elD2rZ4
h5H/eW7V1y/VI3oQlsMYuvtI4YgKmOpz7G/hjHJUA7aBP1+fQYboXO6jM4BTsyWM
9xL9vHZuFcA0PbyqzsasRKRYNC7ueEHTgBzmITlz5aEvIzCjWmsEmNCyQhWsyHN7
UECOUVnRka8kEuKopfHgqKLlyjOS02e5mKh8NQX2IcjV7czPx44BF475P+v04ks1
cFQhOKMjEYBtV1AHF1fs+I5PTW84KuK5i30we6ERXxysdkEFA+4wsVmoIlgozG7Z
SBnaW0bDM0E0rACKtwHVGPTG4NScBQ1mv/ZPOIcE/eU1WUKEfd6KZk73lTUIroiL
yAWJVXom9pwPUL6lL3JH+qsIheOavTRTP1wH0F44j/r2QQegZqhlXVQHyrA1RWJV
OHX87i4RgZPw/9/b1pqk/Or6oUFZHpdbvXo2bT6oq781gWcBsfYa8RzWo+X+0Uc8
Q3CamvFl4HP14YAwwKejmnGj/holtzGG6jceNi/6W+f1YG21cUTRxpGrcLnvK41K
R6vCMvfBZg==
=vtnb
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8DVEUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSUxiBAAt0HOBg0gsM+MAEJZfwv1DUaquA8Y
Zb92F0N8aM2XSiWOK5LfzdDnTwTHoQ+5yI2Y18TMavpsGUR28FiK+vXeXRNgyo2J
d/RJUbleNk2mDK/Rkp07Cp+TK7mlY/mpbPOevuQKya2pYyu9ZyCPSvWHk85sCrJ7
kTsl0fY5ukDrFosCxRNDNKtfywgZw7dAm3JJkzfQo0pVo1wKxlogO9u0TPgn0PiK
TnE4pqziJaPPZTS/MYXWRqGof3eand4UbitNEp+HxL2JfbDlhZ5LW1rtNa7DvRPT
pj4Dy+IxGZyHlgFN6mxcu4NfGHxXNTFgQM2aqeyu9zXVh+y8+jqXGmtgCPdo06GC
DpEgRpHtG2nqxXdYVE7+8aEcRZVTNBKR0C9PyyNyBbYV8FeC4g5gfC6237pbSkAL
gsKa0Dom/MoN2RTkpci40vqyyQ13ooNQ3Z08mPa5xTyLUWqOXexd/bSZ4Cl8JxW4
Oe2G6cYhO5lRKcqNhzEMyeYQloxmI/uySMRSvY0bS9B6lOVgQQEYezQfVHNuJgBD
qHyQg6Gznk6TVpi0wxn40XnLzSBFeZ7Z8WUkEJyY5cW5dIiCFYnno0AHBrxqxeZm
22YbOLYbg9SO1OXKOe/Hd69iEoCfWxB4TbWDAFM3qBEx2TvoaOsAosQJfKzLktC8
ogPOBrGsxruqIb8=
=Yl9+
-----END PGP SIGNATURE-----
Merge tag 'samsung-clk-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:
- Exynos990: Add few missing clocks and correct the gate clock
parents in the PERIS clock controller.
- Cleanup - Use kzalloc_flex for __counted_by checks in Samsung
clk driver.
* tag 'samsung-clk-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: pll: use kzalloc_flex
clk: samsung: cpu: use kzalloc_flex
clk: samsung: use kzalloc_flex
clk: samsung: exynos990: Fix PERIS gate clock parents
clk: samsung: exynos990: Add PERIS TMU_SUB_PCLK gate
dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLK
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Stephen Boyd
|
1353d95e63 |
Clock driver for RV1106, fix for rk3576 spi source mux, better representing
fractional PLL coefficients and a fix for the dclk of the 3rd video-port to not affect other compoents when its rate gets changed. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmpzqVIQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgTYRB/9lSKLStQtLlreGs6zY5F2fVLN6qUgimFuz t7MFxUTJp/J8dArPK/PST78s+dbFcI2U2d+4K24zuDtNJm7Zsw3sEEcNjFRNqcnN FRyXdT1Yc1EhTFlwg8rSeVC/sCznm1b59BMBPRP2u11kDtPtS1HxpEPACFBg4rIg Bul89omf3Iyq//W5wweb69IK0GxAw3fldjgONOd9D1yd+GvO/HW/V03bXbX71T9Z RkSSyQ3E8bdxJzdEMUgaSSFVAxSCji0v8H30Kp5hlWm4JX3yhZzyTHcvv/QwxgNk F+irFyG5GfFzVg1wN+E55bdcL8o6OthIocVd9ae+OtKs5GFotzsi =6iqM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8DQIUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSV6Pw/9Fgw7gZRPS0KFJ/MXUgc/AZikVlpU r8GjmpcmpnjiZOIOKM2dvmBV7f1iB3xxNS0c9QDQ+HGa3G/+WWKsoHePumRVuJMf Mq7Zds7TP4DOSrxQGmrGA8B7YAthPV3iSUxjnxd5di0KXf0958HWVdNuYUNuS2x2 3qHGpqt24zGG1PV/59QKHK+fzrMt6dMOLOscYwhoaaQrnxXt0nQjslwew7W2QSlF 5F/2g8KHg3ezZU0S0AWsZ2+b2yhEojGxjjYwBjEgFysiOABAd2EfilgSG3EU7l5f 41uf3eJKfbocz7Lw0ZoHo1TBc9OAvA9mPLwoj/eFEc1oIH//2ODsvsd4spOSimJz RTWH2C9XJxlZKnBN/ZFRZtaghsdmF74iIumweekXXidsVP0+BsQyp6f6aKNOABiU 8RAEpL50vHFBt9RCNvV8dBghav6TWmR8oHkRlNoYzqZ9NX3L4wVQn8rhSNwwQcGw mvs7ginmTQX+uC9qgHuIV4kP4WasYCfTzFQlPlFMoAtpgtggtuXzxqeJJEfTpRiW 080t0XVS5kMIFPgbd51xdpBe+BJTLKUq+k8wZuP0XazfENP/fgAj1sw2DXdkD3NU IfknpUcBtywx5AIdXGWP7qNTWSJ+YAkSz/KTPd9f76UY1ToXgMMH2VAc42FD3rsf Qe1OM6jN7BB4CW8= =jLWg -----END PGP SIGNATURE----- Merge tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Clock driver for Rockchip RV1106 - Fix for Rockchip rk3576 spi source mux - Better representing fractional PLL coefficients in Rockchip clk driver - Fix for the Rockchip dclk of the 3rd video-port to not affect other compoents when its rate gets changed * tag 'v7.3-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src |
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Rob Herring (Arm)
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da3abd0445 |
clk: at91: Read "reg" with helper
The "reg" property is an address-sized DT cell property. The AT91 compat clock parser only uses a small bus id from it, but reading it with the u8 helper does not match the property encoding. Use of_property_read_reg() so the code goes through the helper for "reg" properties, then keep the existing range check before passing the bus id to the clock registration code. Assisted-by: Codex:gpt-5-5 Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20260612215251.1888345-1-robh@kernel.org Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> |
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Stephen Boyd
|
9af2b73822 |
i.MX clock changes for 7.3
- Add audio PLL debugfs support for K-divider control. - Add missing MODULE_DEVICE_TABLE() declarations for i.MX8QXP clock drivers. - Add PCIe FUNC_OUTPUT_EN clock gate support on i.MX95. - Configure the i.MX95 PCIe transmitter current reference to fix REFCLK rise-fall timing. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEETvPuEU56jyrKp9G4G19EyQCVFVYFAmpxz1YACgkQG19EyQCV FVYqmA/7BUS8H0KGRHeRs2VXP1tAydexeUgePx0eqzUzSij92rSicZodfhMeuVtt 9k3MH35QFRiiKcU9giOFg7XQk5KEAXwsLFuoaPv5EYwITChKeTCKhOu42GvQ5BMA sTvuENQt9rg3oW3wGfluiWK/ENxboB3TlbV/mCU2YuNdpwHnKRDu6lqWFn2milx1 j31izCzrXDndFD3Iw6KRnnAyzS6TBO55iXOSvWJe15XepHERXn73m/0IW+4ZsAMY dp9ggS4Qo68qczPxQQv2mudntSpz++ZUoAJbCuYHppgstUOpS/9lFm3w5EpRa7MR TTy6p1sKhddM0l463Lct6nDXFSXUzhk5cAmF3BSGdF3rJf3nkGRWTmyEXkW2TzPY Qedg9wU4hDEygMqd4Mk2Tpd1GNIUxAuwD6J0sa4janh2kCTfVo/B1NruW6rERSfL 6AmFVwSSdjo9z8OYXNn+nzpycvdC4EVZr4tUzm14mjou05LBSy0Q4kUJredQpuJt w7yjBa4j8Y3DtY80sQ6yBjFn06T9wmx0SdpNp01sYODzF4p5B4hSt/IJqG6RFiu5 /B2pNWRFsgys0KGky/IVcqfYhjnyuiV+yDJortnryVGHMa9XmeEwLkvJyhg8FTs4 FkU5INkvjL92jZohpgCjNjSbYFyn1HoSH6Bu5x1P1iGDCkdaYhs= =AFza -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8CGcUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSUNgBAAoJnoiA+XxAtdiqS0ESsjrzsGN8y3 2p2nGLioG8feIoGlSQ5G8rWBH3nCsDh7fjr7dqUwKnBOWXgaR858ypVnBOeYKXKI 4BMhI7GAkhN94fGUkRcM1OXmddQ/0o03Tus0c9YkaQeQ5oXoAWbGMTHprqXAWE9D 7fGzcv3JpvpbMI1hucqDDi7XXkNWnzD41sysPMfdUpcX5gqHANtPWE8A1Onq/9nK q6NKkiIeQ/rBlnNLhJsKJWNGrC7Bc9tSWiAsntNyEfxywtghRsTyzDQ3Eo1YIIzG UaD3tNeoGk7aanWYkQHjnL6RCWLKUElfBlhPAvW0Lm9T93K5CaoUOvT9oFJVVnO6 KbMEKdfKjhdhGmGrU+bujchGxsl90rpQEOS4xuZUNU3nUFw1h3GvkkPl+Nt+bJIz Io/qzbQrhcMLni7aP2POZa6hHKcOkCzDm/b5+OmYFXDGK+x6MvkhcgXVEov4gM1f bgFshkyi8JHS+wrEHf+gshvoF9aVMu/V7JsZm+zQBh7Z48neRPfkPkx3WLimv1K/ 2d1jkEgIKpY6+z5095/kS4H7/oAK94zaODuBc3VjOAw/3MbLU0j1y8s0o1NcS4Bc iHj5OIZ++V1EigGtp6aiPkUJud0Pl8U4nrdVxa/o/MeMq8bgyxub/9G8lm/BRDB+ idO7CpOqwJLKLko= =YBxi -----END PGP SIGNATURE----- Merge tag 'clk-imx-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Add audio PLL debugfs support for K-divider control. - Add missing MODULE_DEVICE_TABLE() declarations for i.MX8QXP clock drivers. - Add PCIe FUNC_OUTPUT_EN clock gate support on i.MX95. - Configure the i.MX95 PCIe transmitter current reference to fix REFCLK rise-fall timing. * tag 'clk-imx-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 clk: imx95-blk-ctl: Add func_out_en clock for i.MX9x PCIe clk: imx: imx8qxp: add missing MODULE_DEVICE_TABLE() clk: imx: imx8qxp-lpcg: add missing MODULE_DEVICE_TABLE() clk: imx: Add audio PLL debugfs for K-divider control |
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Stephen Boyd
|
166455473d |
RISC-V SpacemiT clock changes for 7.3
- Add clock for UFS controller - Add new I2S clock and fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmpunFUbFIAAAAAABAAO bWFudTIsMi41KzEuMTIsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtq1EQAJPWtqyQjQIcrF9ueZNm pj4sZ4v+bkLUas0YstOhHeEc8oeCHVB2OupJzd0m4NpzKviKJXf6f6AOs3P7Rnwi VwrWYdRVRCK4dk4BSJYaqEQ/gIhaKvy9WnfL+O+m95JeYwhPrZ8HyeU54Il5Cb3D aWdNAMyctR4kcRtAphB1J0+abuoGnTmWeGkYlMc6Y3j+sdMuvjSJcQ2dWidhVIse G+ztLGPm0tPBpHRYjAZDlny5vExzwyyUQ2vu4nmKCCAyAfMOxHmJRpW6iv+uRsQf bisMpaCm5wGBvTNiDZSzYlLDp1N3GBsucY0jxwm0ZBbNyHKmQ4UFHtqy2XmMEit6 XJQXT85LRDurbRhzHDaMrirunXrZi5O6YqfJq19/bV2ChdGeWKhEkAj8Uvg94Zxu RhAX845rBQRaT8v0Unqw5oYeH8TKj32X5eBJaZx/TVaBthJ245fcTVTrgUgQNB+1 EAApa3TOaqM9SVMWmDWAIZ5O7BppXCTJm+P6eaHzJRHJvIp25wfD/Cp1MKS1OLr6 vl76AVzUn4dXAksLwsJEgl4XiDhW+lT7Hd/+NlwSwcaqzzhLdhjzEceCPt2QVUSZ Ru+N7ED6j24Etpmi5Vvpa9JnC/upHkkO3kmmPvWSaD/d/RtELzL573Gbx3r9ofHT RDl64jRLxgQL8ydIMaAIN7Bu =JXgV -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8AwYUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSX+QRAArcNSD/jlIH0f2r2Y0eEaCXkCGsi3 cOToSvpVf8liHIuAIAsWpKRYcCVmsYyPNU7DQvtoc/cCDVIJ1P9hHVryPNF3qc22 ei8C/fhkUc+oxTkPhVqAdZl1pCaxleIUB4S96iy9V7C2sOXOLOKdx6P8sJlUIo6z 11dNAcZ7Ardkgj5BafENbMjqwmg449dHLb418Q2IKbn5xSBkXDUHKVvlkGzAjWFK M6K9m81mXN1uOgv1LsGLHDQK/mdddUotJrKCS94hCdKwymZpGKICGHsPHLSFW5Ar NAZXDfVKDvJj2N65L0t+Kh5fIBw8mmttcMD45mJXQ/AA7CPlgRax2x5OjC/x2kQh wKpxCMIS2PHIXaXWqZmoT+6TXIN5kJ0Y6hpwIOwwZ9l6hlVa3VPyy0PkEGH7WKh2 uNhnVF7Ik/KjHdDS8G+A+8vrOEWMN/Pn3iQbe1N1X0GxKLzr5vxrzcFcsneQw87W fR6zjjtbFu/kYp73rXhiLdO7eFy6JAF/dS4a7kH3xtoSo37cWYXWabZPSrQQFGJd Y0kY2XXkdNM+HJGXVVkEIQhvxCcE39qBImYHwEZrYmq6hruSeorncJ/wuVN3NJzY /zAj7BMSlOg8V81J0PbiHdpN+UyBGHFvkk+v2NQPh812E0/YN0x5D9Sex9mYMb/M MHnvm14YYXW2CVU= =x8ty -----END PGP SIGNATURE----- Merge tag 'spacemit-clk-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into clk-spacemit Pull RISC-V SpacemiT clk driver updates from Yixun Lan: - Add clock for SpacemiT UFS controller - Add SpacemiT I2S clock and fixes * tag 'spacemit-clk-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers clk: spacemit: k3: fix i2s clock topology dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs clk: spacemit: k3: Add UFS refclk clock dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk clk: spacemit: k3: fix parent clock of UFS aclk |
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Stephen Boyd
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3990334628 |
Amlogic clock changes for v7.3
* Fix the incorrect parent number of the 32k clock on GXBB * Add the AO and peripheral clock controllers for the new A9 chip -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmpspMEACgkQ5vwPHDfy 2oUc2BAAr4p6ygDoxRof6N/NjNlJebaYWviWhwaKDdM9a8UaKKtYeqQP1ye/1Nzv qIUcLCMDqQP1UU4xsErIDcuOLBEZ9l9WWUvL8aMJwNWyZ+l1BFdxROhnHTqfUj+i j636C+7/t9/c7PVu5C+v7i7cAMPCQQx48p1KQskmWiEJBfOt8fgIbfpdIpy9HM4V FprCnyMZdqx9DjUB1n9LWFwAN2skEwplZp3Vg0UZCtKLxdW6RGJ9ALYlknrWTkKL hqWMMQFofNBlBlMaXKrNKAlZfaegn/0pNrAeIpX3rSk8a/bdjQ7FVPtFfSfIHcw+ Z8uoxef3yuLI+c8x/SrRCPSLe83ZalOGtontmuWGT6prE7E89HqS1IqUbVoiMlDD EwbPUEGxLMMJUa3IP5WMGOCqTtnbiI/8gQVC4EgxPxWHiMr8qYHNRwVCfZhzZIic iinEU4UqehOoySapEZum/neBCbl9eJbr5bxxt2aKl60fQcXBJDEDUcju5JG56zuT m3OQAcAcKQoPcA4Fggdvyzc1eZMiEGjdYepT1WFNFq8aAA/qct0nse5GWyvZ9ZU8 tWDFKGwBfI1BfvGnFV7r1CN+wwF77I8d0Yf/6tx64iLYG+OVoGT1764fq+xOp/wu 33BNxGNfW6+tPrHrQp6QHPaC/lTAGVKimGe7usDSomLjDpyZBfU= =pzDk -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp7/0AUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSU0QhAAhtpaF2R3Dnp2+rNaCBEnqmdEqU8f LgK48CXz/a97wJi1QIXfVihajkEBrxi1+j01TJNzEQcFuW2UkXoRbn97ZaPathd+ GoOv+da5IU6e1FwctdHCWXff8Y6tkdkYTP7bAC6/n7m146muNt99MSO1Htkb3x5i 0klXsu+fHQQ+EYcUo31secuMJbC1R94JhF1Oz+MOsSygNbe64e6aJJS3XkZ1x1py 2TeP+/AF53AwYtUx1z0zdHP/xLsyIJnsPmt5Jfzbt3UtKTBOP/IAoyvDSjGRa9kb E7wWnJ7z5GRwZAk4L7kbtrs7nruNSQT8QbHERw87b1uFA2N+gl5k7M+j3pEXdQgo K63uzCoNPyoIsghgg0f5fXBz28eE2UsG9W4JkNfEGcjJK7cSAX7/68dsY4is/tJs Rjy+uLRcBCLtcHOgMZQNTSISAqWt1RBdU6AElKviFNR1nw05xCN9jDRB9xEwYNo/ ZEW9hwjAVfjeD/Yrzs8vqBRYZqyD6lgZkGcM5cNUGTClPbrK+QmVQZXhuDH1HT4o aw1mwFX6FFUrfYKm5nHUWIelh6hETFt2T6L8L3edxRAzC/NYVcrx7KFzTq5387eV HXy/Y4xSimaaCR32tgkeUyv6ZRd8M/m7G4BW6q4ObJq/mKFYsv5VcQYgpAXHRxa8 mW1136cLsgBTRpk= =Dxt8 -----END PGP SIGNATURE----- Merge tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Fix the incorrect parent number of the 32k clock on Amlogic GXBB - Add the AO and peripheral clock controllers for the new Amlogic A9 chip * tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson: clk: amlogic: Add A9 peripherals clock controller driver dt-bindings: clock: Add Amlogic A9 peripherals clock controller clk: amlogic: Add A9 AO clock controller driver dt-bindings: clock: Add Amlogic A9 AO clock controller clk: meson: align gxbb_32k_clk_sel number of parents with actual count |
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Stephen Boyd
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cd72dbb2a7 |
clk-eyeq: Add support for Mobileye EyeQ7H
This patchset brings the support of the Other Logic Blocks (OLB) found in the first Mobileye SoC based on the RISC-V architecture, the EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks provide similar clock and reset functions to the controllers of the chip. This series introduces the device tree bindings of the SoC and the necessary changes to the clock and reset eyeq drivers. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEy6c1E9KFcNpKUem2OLE8WZ9QiKgFAmpZ6HEbFIAAAAAABAAO bWFudTIsMi41KzEuMTIsMiwyAAoJEDixPFmfUIioZPEP/3m6axQcd5jsnpGnIsjf mR/5MbWEJFHjs4rxtWD9xeIqu2NEW1rz1lbw4wWr1Tp4KgrtOTFlkt7hRVzW7QV9 BHOMM85Ssaolk50iMSSDhINkBQtWBd4Xg+fVE18ZrZbMW781lnOsp5wlQK81KUy1 BST5QCIuEssJZkI2sDaI1DSf1hQkUPZmIgfA8i+QlQUq16u/e6mu9Y4eR4CWT0gr VBSiFACjPnucSSVu9vxYvcrrq5QqKsvtsfAUucmI23JmuA65OTUuJLwdHqQod+6n R99om1zc7z2CQITuTDrSQVO9yGmxpDaAu6jVl4SKTax+KJBVt05CWOle8kyO2Mew 2k+yGb2PgW87HwompCU6y1R7BcuStjxs11dWs9XP75rhzxD8/wluOr1Mah7w7Z/P mkBoB0KLwtPZsfeEQwFTOWK6ox+joGGAN/7VoGSgQvzbK4rJbfVh+AEa81aV6MxV J9kMZLC+Y7b/QqM1KG5p57IyVVeY7XWRQe/VPK/Uqvm1B8QwhGRPVI4ihnB+MLkp WDli4KVlaWmXmS1jT29nVqWxjvCS0AnWe6hNgVIIFg+jwRtMhoQZx8xxRIEVcFai YvjgX+0eG49f2MKtLssaQ6DyttqSGFMT6OTrMfWw/xM4Y0ehic+1oTz9APUow1WX 0RNW9PRZv9ylFpxAE8XfJ0FR =w3Sh -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp782EUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSVoWxAAmsUHIZEsHi+O+oKY5WIxBWzKk4d3 WarkDQcYYnL/YCK6N4luG35yVj52hAdrGT5sFERaNgq1dlfKrSvCOO3Tzwn8ZFzf LMawqnQ5hdPigHQTiU9rj+ET77s9w/dXZ5NRP28+oX3Zs8uNszgrJqDKVuYyC3zJ fzXJbhrL8W/JK1VSmX3IkEy9bAutX+Ct+CBF4dQfbwiEQZut6KZubPjWS78acu56 VL4hC0I4X/b3z4W8D3yAGPdH9asiUuKyghQTYjUF5xi68V+hTlMxMI2W8daLbdAQ 8chl96p5OARNzukNbM7rGf0SNywmHhWWaQYBNaVtj8gb1FjPv8lLyM1eEDaBrn8H U3eVobyLtPsy6oAioN+qWU4a8npKqQvHL9Dmn2XyRq3kcLxDy8/8z3tbeAiwVMa4 v51PsPNnogfnefgrTKsPmOsLr+5Cg/d5mnTkqxIQYYYxliCERXquS3IoWB5iPHVD uMfxpCaFRKqMEEtMmrBFPSPCwdhhHGHQDkKDcfEpCFCjC27BXWorcERruedrVMrZ NM6TrYEYu69FFpWfpiGYy/ruuS6lRoqpBylH8aczyqNTwuIsUgq3FHhz3qLKD2iY 8eN25pu4C2D3O9FRr1lDEVuwVaH9JRY3Eq7izEUCQWq8pQ4kUf+aJ/3W3RE82bIW BEdrCQp3pdv3EcU= =izC9 -----END PGP SIGNATURE----- Merge tag 'clk-eyeq7h-7.3' of ssh://github.com/benoitmonin/linux into clk-mobileye Pull Mobileye clk driver updates from Benoît Monin: - Add support for Mobileye EyeQ7H This patchset brings the support of the Other Logic Blocks (OLB) found in the first Mobileye SoC based on the RISC-V architecture, the EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks provide similar clock and reset functions to the controllers of the chip. This series introduces the device tree bindings of the SoC and the necessary changes to the clock and reset eyeq drivers. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> * tag 'clk-eyeq7h-7.3' of ssh://github.com/benoitmonin/linux: clk: eyeq: Add EyeQ7H compatibles clk: eyeq: Drop PLL, dividers, and fixed factors structs clk: eyeq: Convert clocks declaration to eqc_clock clk: eyeq: Introduce a generic clock type clk: eyeq: Prefix the PLL registers with the PLL type clk: fixed-factor: Export __clk_hw_register_fixed_factor() clk: fixed-factor: Rework initialization with parent clocks reset: eyeq: Add EyeQ7H compatibles dt-bindings: soc: mobileye: Add EyeQ7H OLB |
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Stephen Boyd
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aa7ebeb035 |
T-HEAD clock changes for v7.3
There is just one change for this cycle. It allows COMPILE_TEST to select the th1520 clk driver without having CONFIG_ARCH_THEAD enabled. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSy8G7QpEpV9aCf6Lbb7CzD2SixDAUCal/PFAAKCRDb7CzD2Six DEWNAQChPTMeMYPSOzrEmnFodEFynvQUTfGaUXJWUHFC8DViJAD+PUViDmeX2rCq mTcn6IONeO13d75VjZ8hFdDaZNoxZwI= =57RB -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp78vIUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSWBVhAAiM6LDFrutqtNaUF12epX8OZWB8J9 WS14AdTKBef25c4Ys2JN0FI62hXceD8kulh8mwpTjxBVtiRl686T4WbDrUWe7G4D V9qGP2Mt2w550TcxgSb3xZ94icK5/Ap6cPAozCoYtklQvdJ+rzKhYTBIAgjv4O1L FRK7hkscpHJZX2GRKUwCF2n1vDveLiTUh4fOilP+McEyHNrG4ByY8cQ0gosKhCAI rJA7m+JQWHHl+5kp+G3dpSP783TevNFc25/Oiltgt4uYmoc4lEXnmVkw1KTbzmFD IzvYzu3GQjzUNszyuQQCctwa96XN/xTLYZQhosO+6+e+Gt99kwhJuZw5CaE/MdmN jEJZXZZmR6w94ta9eaqkWGAG7MU1XNmxtFQ7TkLmZ7EPzRqH8BGgVxB1nTMymPuh qZHQVhAPOBm21ipehBy/37xF90QJcPMmyIlqQKjzFvMSiFCoEjIBMZQaA6eoFgs1 KxvXkoywHtHFIKEpFFIIa1ka4kNbzQB+wtb7v5Gex/kcdUf8QjfUAcMX0CSuod0r lohcjsQZTvD8RdZfVngYueN7JAb4E6k/JRE5vOcy9aJ5giq/3blrJpDokcjLQUVx EJQeL26tJp+FkLZFMR+N817dtxYGu5e6T0qm56KGXT2ohJGmyRhFWon5Q55fDH7G lXTsjBuVWBTgb9w= =rH/5 -----END PGP SIGNATURE----- Merge tag 'thead-clk-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead Pull one T-HEAD clk driver update from Drew Fustini: There is just one change for this cycle. It allows COMPILE_TEST to select the th1520 clk driver without having CONFIG_ARCH_THEAD enabled. * tag 'thead-clk-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: clk: thead: allow COMPILE_TEST builds |
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Stephen Boyd
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7ae8acad2d |
Qualcomm clock fixes for v7.2
Fix the Eliza display clock controller to avoid RCG stall. Revert the rework of the "PHY mux" clock, as this broke PCIe on several different targets. Drop (and correct one) bouncing maintainer email addresses in DeviceTree bindings. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmpnlToOHGJqb3JuQGty eW8uc2UACgkQCx85Pw2ZrcWNXg//RN1nAKFwKalihovDtpk6wlkxdUEJl53E1dcU t5BWTTPWqlSmlc/FWvIqe7EccWRkm/3/rzt1KKaTw6mqupm2pmvtHa/A1dIfzNuw EMwcFZQssb4m56rS+hO8fvGTxSE8MEd+gl4UXet+neXGvmM7mLu+LotMIH0EbELT QZetojCYtZQVezkiNy/BKiXLCER/FnuQU0S37cpOR6bEWiS0rzptPKAFX3qgoKZ/ I1ff7iCJ5DJSkIYgAZhFXvMk4V6GGP+HXBp5LnWyzxTt+J5+YER+L5Zmv0po8NFh NzFxfC9nH+kihD9716FouII64QbwbmKdTc0qS1tLhH9u5OQmhTZEQ283kadpZIdc nwIglsdmibgFixRDM6sI7CR3aYuFZVbaMCMKWRC9aE7Vxpf0KuRzJnmqxCOwqa1u 5E6+Ps5wb93+mDtYAdx+qRXzLh8ZGUZksoVOE2gC6aZGFkDHEAkQewww6nEQ5ikT 9dZlgnesgMux78Yn1H+PhTFtNXgJXFjWGgBm2YgVXOCvDyXaTF6LE3wlpSIeo9SV mGAExhPm0OrBmxyN15ynQhVXrn4cKv5sY3rBRKPWtVi3pzWmp1y7KVBf/AL6UONj c6VmCq1hFBPrV6IUPM8kHJK50Ju+yIrcqS2P6quEaEIT8RKCyunvurwHHjhUz7Ya uUM7ZxI= =yj29 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp6GioUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSW9bA//SYbI1Mj6q2gMJyFZEL0Fz8P5pfWI LAPPAFK+xhTQDl0POkv2/zzRYmXhuQFTD/v2asRmCyu/C9b+GMKVBTuAQWnybSy3 Mp6HjYRrAVpMbZE56lLGkgZXi6a3bZOh9K5m6wdd5frMQt131slBaiiK/U3ZyFKR TQEIpNsbNa5mx614yCqobEDlGBIO0o4r2Z4iQD05ni2MH+ZYhVUKo+8gisEJledR GK7ter1b04MCMaxLuW6GAj46DNUhXdXTaEunmgdimjhtSTCy09AulTZO477heQQj PGXXxjuh7bxY0z8xorbWeqgz1nhr1L/nSDXPxTOyydBJ4FESqEtx8H4SaYiqdqxI AGNMH7KQPPJTf9nB8lJWFW8tlUi71a/LlQHH8Gu55+N28nkTceQ02dR1eUSue43I o2g6PMDUayX5SQRyQyEmO4Geusm5yENNHSxL7myDOsw3XIJbt9fjCTdulA50azK2 3QsFkXHy+fBOHxLa2njELKpga/AkUmmmfdj8u3nSe7z60Rjo0ZqUgPd61zO6HTf+ ncDjKlWHnihb7TnEQWyYSLZr9t/BOALDQXS8UFoxaNYu1ReNrV9OqxZFKN/igX77 HzYEmYURM5XeS3I/W8ignbxAXk6VBGvd91tv3By8o7fhlPfPQNCCcOJ9VvhdBkFb Vrf6zvBdavldz3U= =RZDP -----END PGP SIGNATURE----- Merge tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull Qualcomm clock driver fixes from Bjorn Andersson: - Fix the Eliza display clock controller to avoid RCG stall. Revert the rework of the "PHY mux" clock, as this broke PCIe on several different targets - Drop (and correct one) bouncing maintainer email addresses in Qualcomm clk DeviceTree bindings * tag 'qcom-clk-fixes-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: dt-bindings: clock: Replace bouncing emails Revert "clk: qcom: regmap-phy-mux: Rework the implementation" clk: qcom: dispcc-eliza: Fix disp_cc_mdss_mdp_clk_src RCG stall on Eliza EVK |
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Stephen Boyd
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46438586fc |
Fix for the recently added i2s clocks, to make it backwards compatible
with the existing devicetrees. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmpikiMQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgTGDB/wOp7Uxd2tfl7yye9dRbB4iguPfMpglFv6W MEnEkScHs+eQ2suNsLowagiUK9by7lbN9DvF7QAqH9Y23H6OxvMQobU9EIYMvkwZ J2cfGHx/bi8n/K82Po9UPAxXPaB0OjFNxI08FXoEWrE1Li3PdtiaJ/tacCyDjnk1 y+zWXnYTA33vZXQTpNvmOVjmJ1qdkBVRzfdqfzwuX7Sz/VKtbueCxUiDrM2GxUr8 AGdDz5BsRbVmJVRJJcLnEzI+MpMKJIS7g1dyuJpvXGOY0gJN/+I4mlgGOmlqwJK/ C83ql8qJxXEDwohrQeaWK3SKeoAGqJRyCrC6nijwjbSSc3zsCma5 =CIkN -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp6ErIUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSUCiRAApJ/YXrVxpjHV04HzyMB0SyQu5v/l tjCWrgIPz3PcgjmkpK6ncAr3Hyhx4Ohhr8exM8Vdd2AavHwYgOipsJtmj0L83MtG Kq7GR2tYH2D3iheAafD1y5qInvF51cc+WGTAAWmVQSr9QIHikARCtYFuc6QqmYlP P67scZ7yIOFt6Co9t8qZ2suQ8tal9fmbcWv//zAo6416hh6IAz7MkImGgfeP4wFB acRnzfq1PnF3wMv9NIyAlFk1Z05kXyT4S+Rcsr+nYaZI40MdmXYoC/Tr8EEF0FXC LPYieoJcSQqn8EZqkOWyf9ReDVSl90s0ezMvAI/wi/l3c5MCWw4FOZBiEtpVGaJI a77Yp9JVQ/gOV7nJjwNjajekPI8hKMN7zFZyKzvtT4Euf93+YwWn4urvdh/Lt2EX Vw4nR37sG760s0A4VhRVWoXXxc+bjZzyy+3Sxp58dX5i+rTM8AeMkvnf+jVDlZYu mW1gVG3Oi3dhYTe0HzwQR6CesMTUW0wT6ZbeeksxrhKhUMDABhkWEOVyxAcvvgzJ F0fyfWKT/DK3MG4WUppPHqIGcEOL+BdZi+fyohT72+9EqNw79p3v7Kfs/LzM68p0 O/VexKV9PhIsGmt95qjGzn8ubHqulKadO//GPb98H0sZItPc1+4Ktp/KCmc2RUfp e81R02R7EbCB2a4= =T1ds -----END PGP SIGNATURE----- Merge tag 'v7.2-rockchip-clkfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull a Rockchip clk driver fix from Heiko Stuebner: - Fix for the recently added Rockchip rk3588 i2s clocks, to make it backwards compatible with the existing devicetrees * tag 'v7.2-rockchip-clkfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3588: don't disable unused I2S MCLK output gates |
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Stephen Boyd
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14460b40c0 |
RISC-V SpacemiT clock fixes for v7.2
- Fix USB2 bus clock - Fix HDMA clock -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmpMDHobFIAAAAAABAAO bWFudTIsMi41KzEuMTIsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvt28gQAIocejCpBZtHHi+vU3jf /q8mwXj0vuKyqeJmZaOBfyWrwsDTvR2rE9tJt/7fPptxFypwNoxkCuLDmIM0un1j FYWf+ARO4M6Syo0BbyQ6bg2s2Zhrdtp5Ow5whKEf72xvOT9Rn8JyrkGE4Y1dI/11 W/pJ+FsECWquIwDZCIgpusWYHnpmKlS4mi2U7mvdMKdbIMVEq5zn2wrgeWn1n8QT G8QYy0fL9S/4Ncj69ezbpOF+ormSdOWpAmvmVGxfarCUze9luLCcVoG31A40/2WO puxUtT9tnMk76guudYrIR3FHBiHk0ePEpjDtW8LaMsUejqT0Rkk4EXf3GbhqD6GN wtvfhvrNh7a4pOnakawug4XCCkWK6PQul+J9KFKbIR8Jm+3qkoR02HvSwStGpo32 OZRXstTpJBW0xYdapiPobmI5OCMUzn6g2vWkKQLfSDMWQav+wF49OejASDXDvldl 0giZsjTwdCAlagKOigzICVwqMVM4wQM51IsB/1K5quqL9lMZEld8hVI//udU1rVP LfUwyx2kwJq/FrG9YbWJWEWhLoNJx+2VeM7TzFv2Mdi3hXWZZ/k0cRocx6ecm1S0 xGIAfqcww12xyfkyZ96/uXfRJd3P1Krm8RCWIPEcoJ1i8hxlmGifengpqmqB5rVx MBQCaUMYX4NQvZRpkL452ZxC =o3hc -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp6Ei0UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSVjjA/8DDAzHYV3epyXNPKjvlEgOGj2iW/a pGJNWZvVqVECi6pNesDohF6OUaC/wWdNpyLOgMXUOlL9WSZz6wlgnyAQvc9vI4Vq Hy7t4/NTcEEGaz784xuqj0bhq5eKbpRBdJqjw7ftJXovKEbcPPUNOVDEGVhy+Foq 4Li2Z/2mpWCFNaq8cjlwy8YHiHb3ag5vntF5fFeXeg+wEyFH5Ib2f8QyE1u+zflo 8tTAaiVK6iEAVNimGsJL+D2FucxSZbnMWnyb6ZY485RDrPR7E+3cp3arXr+CKq/r DRcxjD8PLNbYd8xCXJIGoHzD46Bw7F1ojgCnToDDfbExtuHkKN5JupYwzzyQkauY zkaNpfksbEHyL/Q1HV6ZFIIQ0/UVSGdNIUeeM4t+Qp+EM5p9RUl7mkYBWJZHuUS2 s16t62APpiZBoXXQPrCvcIUBhwi+SMs039XWC6Dk1qbSK369UYkMG8nWwq8/XoaN jcHZrMwC048U7nbSOAT1aSvhwrK7xTvS6ceiSsozV6Q+hQ952rTixwnRj5wikHNH 5p3hrbM6/Juwby5+fYFpA4ltD0At68LnX0f8WLGlQRTnciKyDu2Q3o2eDdHFGrC8 1iK/lxH0GHfB5bkfpu+1PnQ7Ku3ttFYja5v2NkeeEbovfbH1Q8AiTb/mGAiwVaZq +ehKV+YXrNtsJDc= =qqs/ -----END PGP SIGNATURE----- Merge tag 'spacemit-clk-fixes-for-7.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into clk-fixes Pull RISC-V SpacemiT clock fixes for v7.2 from Yixun Lan: - Fix SpacemiT USB2 bus clock - Fix SpacemiT HDMA clock * tag 'spacemit-clk-fixes-for-7.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: clk: spacemit: k3: set hdma clock as critical clk: spacemit: k3: fix USB2 bus clock |
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Geert Uytterhoeven
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0fb9083a6e |
clk: renesas: Add R-Car X5H CPG driver
Add a minimal Clock Pulse Generator driver for the R-Car X5H (R8A78000) SoC. For now this supports just the few fixed-rate clocks that are needed by the current minimal DTS. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/3f981753722de1ba871667be63460e89d299d635.1785941595.git.geert+renesas@glider.be |
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Alexey Charkov
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586ff159ec |
clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
The TRM defines available source muxes for SPI0..SPI4 as
- b00: clk_gpll_div6_src
- b01: clk_gpll_div8_src
- b10: clk_cpll_div10_src
- b11: clk_xin_osc0_func
Which doesn't match what the current clock driver implements, making it
impossible to derive some SPI clock rates such as 37.125 MHz (which
requires clk_gpll_div8_src as the source mux).
Add a correct mux definition per TRM and point SPI0..SPI4 clocks at it.
Fixes:
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Simon Glass
|
b520d056f2 |
clk: rockchip: Add clock controller for the RV1106
Add the clock and reset controller driver for the Rockchip RV1106, based on the vendor kernel from the Luckfox Pico SDK [1] at commit 824b817f8 (a Linux 5.10.160 kernel tree), adapted to the upstream clock framework. The MMC drive and sample phase clocks have their control registers in the GRF region. The CRU provides these clocks itself, using the syscon referenced by the rockchip,grf property as an auxiliary regmap, in the same way as the RK3528. The RV1103 is a package variant of the RV1106 and uses the same CRU. [1] https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Simon Glass <sjg@chromium.org> Link: https://patch.msgid.link/20260729133609.3465563-3-sjg@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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Geert Uytterhoeven
|
889600e21e |
Renesas R-Car X5H CPG DT Binding Definitions
DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Clock Pulse Generator (CPG), shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCanNW6AAKCRCKwlD9ZEnx cPR4AQCNfYByL18jPy6CLnjVNqaM2G/agem8pPGNh/F/yr+8XwEAvGh8CNxBoeO0 S11jYOm2zTq0zGqhy+HNLK5mvMygyAY= =9Rmf -----END PGP SIGNATURE----- Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3 Renesas R-Car X5H CPG DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Clock Pulse Generator (CPG), shared by driver and DT source files. |
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Imran Shaik
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c7d44572a8 |
clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra
The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC hardware block, with minor differences. Hence add support for Shikra GPUCC by extending the QCM2290 GPUCC driver. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-15-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Vladimir Zapolskiy
|
22d9257f08 |
clk: qcom: Return expected ENOMEM error on dynamic allocation failure
If a dynamic memory allocation fails, the returned error code in clock
controller driver probe functions on a few legacy platforms should be
set to -ENOMEM instead of -EINVAL.
Fixes:
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Varadarajan Narayanan
|
546e0bc2aa |
clk: qcom: apss-ipq-pll: Add IPQ5210 support
The Application Processor Subsystem on the IPQ5210 platform sources its clock from the Huayra PLL. Add the configuration data necessary to set it up. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260703-apss-clk-v3-2-4785e89a9c58@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Jagadeesh Kona
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778149217d |
clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
Add support for Qualcomm Maili video clock controller driver for video clients to be able to request for videocc clocks. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260717-maili_videocc-v3-2-6656694b06a7@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Imran Shaik
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ab46b5fb66 |
clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable
The RCG's clk src has to be parked at XO while disabling as per hardware
team's recommendation, hence use clk_rcg2_shared_ops to achieve the same.
Fixes:
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Imran Shaik
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7274ea68d2 |
clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe
Drop modelling of gpu_cc_ahb_clk and keep it always enabled from probe
similar to other critical clocks, since marking it as CLK_IS_CRITICAL
causes the clock framework to invoke clk_pm_runtime_get() during prepare,
which prevents the associated power domains from collapsing.
Fixes:
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Imran Shaik
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1b4599bc20 |
clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
Update the QCM2290 GPUCC driver to use the qcom_cc_probe() model by moving the critical clocks handling and PLL configurations from probe to the driver_data to align with the latest convention. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-9-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Imran Shaik
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1b2e1f5a37 |
clk: qcom: gpucc-qcm2290: Drop pm_clk handling
Drop the pm_clk handling from QCM2290 GPUCC driver as the required GCC AHB clocks are kept always enabled by the GCC driver during probe. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-8-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Imran Shaik
|
08cfbfd81d |
clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values
Update the QCM2290 DISPCC and GPUCC GDSC wait_val fields to match the hardware default values. Incorrect settings can cause the GDSC FSM to stuck, leading to power on/off failures. Fixes: |
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Imran Shaik
|
899dfd9022 |
clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs on QCM2290 to retain the register context across GDSC power collapse. Fixes: |
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Imran Shaik
|
6b0044bc75 |
clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs
The Qualcomm QCM2290 SoC GDSCR status bit may not reflect the actual state of the GDSC, instead the power on/off bits in CFG_GDSCR must be polled to determine the GDSC state correctly. Set POLL_CFG_GDSCR flag for the QCM2290 MDSS GDSC and GPUCC GX GDSC to ensure the correct GDSC status. This is not applicable for GPUCC CX GDSC, which relies on gds_hw_ctrl status. Fixes: |
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Imran Shaik
|
11345cbf17 |
clk: qcom: dispcc-qcm2290: Enable runtime PM support
The QCM2290 DISPCC is now associated with a power domain (RPMPD_CX) to
propagate genpd performance state votes to the CX rail. Set use_rpm to
true so that a runtime PM reference is acquired and released around probe,
instead of leaving a permanent 'enable' vote on the power domain.
Fixes:
|
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Imran Shaik
|
b8b5b26aa1 |
clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model
Update the QCM2290 DISPCC driver to use the qcom_cc_probe() model by moving the critical clocks handling and PLL configurations from probe to the driver_data to align with the latest convention. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-3-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Imran Shaik
|
b4ae34a7e6 |
clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
Some GCC branch clocks are required to be kept always-on due to the hardware requirements. Drop the modelling of those always-on QCM2290 GCC clocks and use the latest .clk_cbcr convention to keep them enabled from probe. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-2-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Imran Shaik
|
3e7b008046 |
clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
Add support for Audio Core Clock Controller (AUDIOCORECC) and Audio Core CSR resets on Qualcomm Shikra SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724-shikra-audiocorecc-v4-2-0a89bb13d817@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Taniya Das
|
47f2e6e1ce |
clk: qcom: gpucc: Add Nord graphics clock controller support
Add support for the GPU clock controllers (GPUCC) on the Qualcomm Nord platform. The platform includes two GPU clock controller instances,GPUCC and GPU2CC. Register support for both controllers, which provide clocks required for the graphics subsystem. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-6-32b45232217f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |