github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-22 04:34:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

RISC-V SpacemiT clock changes for 7.3

Browse Source 
- Add clock for UFS controller
 - Add new I2S clock and fixes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmpunFUbFIAAAAAABAAO
 bWFudTIsMi41KzEuMTIsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z
 Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz
 REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtq1EQAJPWtqyQjQIcrF9ueZNm
 pj4sZ4v+bkLUas0YstOhHeEc8oeCHVB2OupJzd0m4NpzKviKJXf6f6AOs3P7Rnwi
 VwrWYdRVRCK4dk4BSJYaqEQ/gIhaKvy9WnfL+O+m95JeYwhPrZ8HyeU54Il5Cb3D
 aWdNAMyctR4kcRtAphB1J0+abuoGnTmWeGkYlMc6Y3j+sdMuvjSJcQ2dWidhVIse
 G+ztLGPm0tPBpHRYjAZDlny5vExzwyyUQ2vu4nmKCCAyAfMOxHmJRpW6iv+uRsQf
 bisMpaCm5wGBvTNiDZSzYlLDp1N3GBsucY0jxwm0ZBbNyHKmQ4UFHtqy2XmMEit6
 XJQXT85LRDurbRhzHDaMrirunXrZi5O6YqfJq19/bV2ChdGeWKhEkAj8Uvg94Zxu
 RhAX845rBQRaT8v0Unqw5oYeH8TKj32X5eBJaZx/TVaBthJ245fcTVTrgUgQNB+1
 EAApa3TOaqM9SVMWmDWAIZ5O7BppXCTJm+P6eaHzJRHJvIp25wfD/Cp1MKS1OLr6
 vl76AVzUn4dXAksLwsJEgl4XiDhW+lT7Hd/+NlwSwcaqzzhLdhjzEceCPt2QVUSZ
 Ru+N7ED6j24Etpmi5Vvpa9JnC/upHkkO3kmmPvWSaD/d/RtELzL573Gbx3r9ofHT
 RDl64jRLxgQL8ydIMaAIN7Bu
 =JXgV
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmp8AwYUHHN3Ym95ZEBj
 aHJvbWl1bS5vcmcACgkQrQKIl8bklSX+QRAArcNSD/jlIH0f2r2Y0eEaCXkCGsi3
 cOToSvpVf8liHIuAIAsWpKRYcCVmsYyPNU7DQvtoc/cCDVIJ1P9hHVryPNF3qc22
 ei8C/fhkUc+oxTkPhVqAdZl1pCaxleIUB4S96iy9V7C2sOXOLOKdx6P8sJlUIo6z
 11dNAcZ7Ardkgj5BafENbMjqwmg449dHLb418Q2IKbn5xSBkXDUHKVvlkGzAjWFK
 M6K9m81mXN1uOgv1LsGLHDQK/mdddUotJrKCS94hCdKwymZpGKICGHsPHLSFW5Ar
 NAZXDfVKDvJj2N65L0t+Kh5fIBw8mmttcMD45mJXQ/AA7CPlgRax2x5OjC/x2kQh
 wKpxCMIS2PHIXaXWqZmoT+6TXIN5kJ0Y6hpwIOwwZ9l6hlVa3VPyy0PkEGH7WKh2
 uNhnVF7Ik/KjHdDS8G+A+8vrOEWMN/Pn3iQbe1N1X0GxKLzr5vxrzcFcsneQw87W
 fR6zjjtbFu/kYp73rXhiLdO7eFy6JAF/dS4a7kH3xtoSo37cWYXWabZPSrQQFGJd
 Y0kY2XXkdNM+HJGXVVkEIQhvxCcE39qBImYHwEZrYmq6hruSeorncJ/wuVN3NJzY
 /zAj7BMSlOg8V81J0PbiHdpN+UyBGHFvkk+v2NQPh812E0/YN0x5D9Sex9mYMb/M
 MHnvm14YYXW2CVU=
 =x8ty
 -----END PGP SIGNATURE-----

Merge tag 'spacemit-clk-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into clk-spacemit

Pull RISC-V SpacemiT clk driver updates from Yixun Lan:

 - Add clock for SpacemiT UFS controller
 - Add SpacemiT I2S clock and fixes

* tag 'spacemit-clk-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux:
  clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers
  clk: spacemit: k3: fix i2s clock topology
  dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs
  clk: spacemit: k3: Add UFS refclk clock
  dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk
  clk: spacemit: k3: fix parent clock of UFS aclk
This commit is contained in:
Stephen Boyd 2026-08-11 22:21:40 -07:00
commit 166455473d
3 changed files with 33 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/clk/spacemit/ccu-k3.c
View File

@ -218,11 +218,19 @@ static const struct clk_parent_data i2s_sysclk_src_parents[] = {
CCU_PARENT_HW(pll1_d96_25p6),
CCU_PARENT_HW(i2s_153p6_base),
};
CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0);
CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR1, 30, 1, BIT(31), 0);
CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0);
CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR1, 0, 15, 15, 12, 1, 0);
CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0);
CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1);
/*
* Divider of i2s_bclk always implies a 1/2 factor, which is
* described by i2s_bclk_factor.
*/
CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR1, 27, 2, BIT(29), 0);
CCU_MUX_GATE_DEFINE(i2s1_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR0, 30, 1, BIT(31), 0);
CCU_DDN_DEFINE(i2s1_sysclk, i2s1_sysclk_src, MPMU_ISCCR0, 0, 15, 15, 12, 1, 0);
static const struct clk_parent_data i2s_sysclk_parents[] = {
CCU_PARENT_HW(pll1_d4_614p4),
@ -236,14 +244,14 @@ CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2,
CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0);
CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0);
CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 2, 0);
static const struct clk_parent_data i2s2_sysclk_parents[] = {
CCU_PARENT_HW(i2s1_sysclk),
CCU_PARENT_HW(i2s_sysclk),
CCU_PARENT_HW(i2s2_sysclk_div),
};
CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0);
@ -926,15 +934,16 @@ CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 1
20, 3, BIT(16), 0);
static const struct clk_parent_data ufs_aclk_parents[] = {
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll1_d8_307p2),
CCU_PARENT_HW(pll2_d4),
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll2_d6),
CCU_PARENT_HW(pll2_d5),
};
CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8),
2, 3, BIT(1), 0);
CCU_FACTOR_DEFINE(ufs_refclk, CCU_PARENT_HW(pll1_d64_38p4), 2, 1);
static const struct clk_parent_data edp0_pclk_parents[] = {
CCU_PARENT_HW(lcd_pxclk),
CCU_PARENT_NAME(external_clk),
@ -1161,8 +1170,11 @@ static struct clk_hw *k3_ccu_mpmu_hws[] = {
[CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw,
[CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw,
[CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw,
[CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw,
[CLK_MPMU_I2S_SYSCLK] = &i2s_sysclk.common.hw,
[CLK_MPMU_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw,
[CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw,
[CLK_MPMU_I2S1_SYSCLK_SRC] = &i2s1_sysclk_src.common.hw,
[CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw,
[CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw,
[CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw,
[CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw,
@ -1392,6 +1404,7 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw,
[CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw,
[CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw,
[CLK_APMU_UFS_REFCLK] = &ufs_refclk.common.hw,
[CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw,
[CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
[CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,

4
include/dt-bindings/clock/spacemit,k3-clocks.h
View File

@ -145,6 +145,9 @@
#define CLK_MPMU_I2S3_SYSCLK 48
#define CLK_MPMU_I2S4_SYSCLK 49
#define CLK_MPMU_I2S5_SYSCLK 50
#define CLK_MPMU_I2S_SYSCLK 51
#define CLK_MPMU_I2S_BCLK_FACTOR 52
#define CLK_MPMU_I2S1_SYSCLK_SRC 53
/* APBC clocks */
#define CLK_APBC_UART0 0
@ -385,6 +388,7 @@
#define CLK_APMU_PCIE_PORTC_DBI 91
#define CLK_APMU_PCIE_PORTD_DBI 92
#define CLK_APMU_PCIE_PORTE_DBI 93
#define CLK_APMU_UFS_REFCLK 94
/* DCIU clocks */
#define CLK_DCIU_HDMA 0

3
include/soc/spacemit/k3-syscon.h
View File

@ -45,7 +45,8 @@
#define POSR_PLL7_LOCK BIT(30)
#define POSR_PLL8_LOCK BIT(31)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_ISCCR0 0x0040
#define MPMU_ISCCR1 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024