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clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values

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Update the QCM2290 DISPCC and GPUCC GDSC wait_val fields to match the
hardware default values. Incorrect settings can cause the GDSC FSM to
stuck, leading to power on/off failures.

Fixes: cc517ea333 ("clk: qcom: Add display clock controller driver for QCM2290")
Fixes: 8cab033628 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-7-62703e05ef0f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Imran Shaik 2026-07-18 18:26:14 +05:30 committed by Bjorn Andersson
parent 899dfd9022
commit 08cfbfd81d
2 changed files with 9 additions and 0 deletions
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3
drivers/clk/qcom/dispcc-qcm2290.c
View File

@ -452,6 +452,9 @@ static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},

6
drivers/clk/qcom/gpucc-qcm2290.c
View File

@ -297,6 +297,9 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_cx_gdsc",
},
@ -309,6 +312,9 @@ static struct gdsc gpu_gx_gdsc = {
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_gx_gdsc",
},