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Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next

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* clk-renesas:
  clk: renesas: Add R-Car X5H CPG driver
  dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
  clk: r9a08g045: Add clocks and resets for CAN-FD
  dt-bindings: clock: renesas,versaclock7: Update maintainer
  clk: renesas: r9a09g047: Add LVDS clocks and resets
  clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline
  clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library
  clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations
  clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
  clk: renesas: r9a09g077: Add RTC clocks
  clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC
  clk: renesas: r9a08g046: Add clock and reset entries for GE3D
  clk: renesas: r9a08g046: Add clock and reset entries for SDHI
  clk: renesas: r9a09g047: Add audio clock and reset support
  dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
  dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID
  dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID

* clk-thead:
  clk: thead: allow COMPILE_TEST builds

* clk-mobileye:
  clk: eyeq: Add EyeQ7H compatibles
  clk: eyeq: Drop PLL, dividers, and fixed factors structs
  clk: eyeq: Convert clocks declaration to eqc_clock
  clk: eyeq: Introduce a generic clock type
  clk: eyeq: Prefix the PLL registers with the PLL type
  clk: fixed-factor: Export __clk_hw_register_fixed_factor()
  clk: fixed-factor: Rework initialization with parent clocks
  reset: eyeq: Add EyeQ7H compatibles
  dt-bindings: soc: mobileye: Add EyeQ7H OLB

* clk-amlogic:
  clk: amlogic: Add A9 peripherals clock controller driver
  dt-bindings: clock: Add Amlogic A9 peripherals clock controller
  clk: amlogic: Add A9 AO clock controller driver
  dt-bindings: clock: Add Amlogic A9 AO clock controller
  clk: meson: align gxbb_32k_clk_sel number of parents with actual count

* clk-spacemit:
  clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers
  clk: spacemit: k3: fix i2s clock topology
  dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs
  clk: spacemit: k3: Add UFS refclk clock
  dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk
  clk: spacemit: k3: fix parent clock of UFS aclk
This commit is contained in:
Stephen Boyd 2026-08-20 16:51:21 -07:00
commit a1476addb4
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GPG Key ID: AD028897C6E49525
19 changed files with 4796 additions and 514 deletions
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76
Documentation/devicetree/bindings/clock/amlogic,a9-aoclkc.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2026 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,a9-aoclkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic A9 Series Always-On Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
const: amlogic,a9-aoclkc
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 5
items:
- description: input oscillator
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input sys clk
- description: external fixed 32k (optional)
clock-names:
minItems: 5
items:
- const: xtal
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: sys
- const: ext_32k
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@0 {
compatible = "amlogic,a9-aoclkc";
reg = <0x0 0x0 0x0 0x58>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk 14>,
<&scmi_clk 16>,
<&scmi_clk 18>,
<&scmi_clk 21>;
clock-names = "xtal",
"fdiv3",
"fdiv4",
"fdiv5",
"sys";
};
};

164
Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml Normal file
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@ -0,0 +1,164 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2026 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic A9 Series Peripherals Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
const: amlogic,a9-peripherals-clkc
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 27
items:
- description: input oscillator
- description: input fclk div 2
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input fclk div 7
- description: input fclk div 2p5
- description: input sys clk
- description: input gp1 pll
- description: input gp2 pll
- description: input sys pll div 16
- description: input cpu clk div 16
- description: input a78 clk div 16
- description: input dsu clk div 16
- description: input rtc clk
- description: input gp0 pll
- description: input hifi0 pll
- description: input hifi1 pll
- description: input mclk0 pll
- description: input mclk1 pll
- description: input video1 pll
- description: input video2 pll
- description: input hdmi out2 clk
- description: input hdmi pixel clk
- description: input pixel0 pll
- description: input pixel1 pll
- description: input ddr pll test clk
- description: external input rmii oscillator (optional)
clock-names:
minItems: 27
items:
- const: xtal
- const: fdiv2
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: fdiv7
- const: fdiv2p5
- const: sys
- const: gp1
- const: gp2
- const: sysplldiv16
- const: cpudiv16
- const: a78div16
- const: dsudiv16
- const: rtc
- const: gp0
- const: hifi0
- const: hifi1
- const: mclk0
- const: mclk1
- const: vid1
- const: vid2
- const: hdmiout2
- const: hdmipix
- const: pix0
- const: pix1
- const: ddr_test
- const: ext_rmii
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@200 {
compatible = "amlogic,a9-peripherals-clkc";
reg = <0x0 0x200 0x0 0x2f8>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk 10>,
<&scmi_clk 12>,
<&scmi_clk 14>,
<&scmi_clk 16>,
<&scmi_clk 18>,
<&scmi_clk 20>,
<&scmi_clk 21>,
<&scmi_clk 33>,
<&scmi_clk 34>,
<&scmi_clk 35>,
<&scmi_clk 36>,
<&scmi_clk 37>,
<&scmi_clk 38>,
<&scmi_clk 40>,
<&gp0 3>,
<&hifi0 3>,
<&hifi1 3>,
<&mclk0 3>,
<&mclk1 3>,
<&vid1>,
<&vid2>,
<&hdmitx 10>,
<&hdmitx 11>,
<&pix0>,
<&pix1>,
<&ddr 3>;
clock-names = "xtal",
"fdiv2",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"fdiv2p5",
"sys",
"gp1",
"gp2",
"sysplldiv16",
"cpudiv16",
"a78div16",
"dsudiv16",
"rtc",
"gp0",
"hifi0",
"hifi1",
"mclk0",
"mclk1",
"vid1",
"vid2",
"hdmiout2",
"hdmipix",
"pix0",
"pix1",
"ddr_test";
};
};

192
Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml Normal file
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@ -0,0 +1,192 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq7h-olb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mobileye EyeQ7H SoC system controller
maintainers:
- Benoît Monin <benoit.monin@bootlin.com>
- Grégory Clement <gregory.clement@bootlin.com>
- Théo Lebrun <theo.lebrun@bootlin.com>
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
description:
OLB ("Other Logic Block") is a hardware system controller grouping
smaller blocks. Clocks and resets are generated by those blocks and
used by internal controllers of the SoC. The EyeQ7H SoC hosts 14
different OLB.
properties:
compatible:
items:
- enum:
- mobileye,eyeq7h-acc0-olb
- mobileye,eyeq7h-acc1-olb
- mobileye,eyeq7h-ddr0-olb
- mobileye,eyeq7h-ddr1-olb
- mobileye,eyeq7h-east-olb
- mobileye,eyeq7h-mips0-olb
- mobileye,eyeq7h-mips1-olb
- mobileye,eyeq7h-mips2-olb
- mobileye,eyeq7h-periph-east-olb
- mobileye,eyeq7h-periph-west-olb
- mobileye,eyeq7h-south-olb
- mobileye,eyeq7h-west-olb
- mobileye,eyeq7h-xnn0-olb
- mobileye,eyeq7h-xnn1-olb
- const: syscon
reg:
maxItems: 1
'#reset-cells':
description:
First cell is domain and optional if compatible has a single reset domain.
Second cell is reset index inside that domain.
enum: [ 1, 2 ]
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-ddr0-olb
- mobileye,eyeq7h-ddr1-olb
- mobileye,eyeq7h-mips0-olb
- mobileye,eyeq7h-mips1-olb
- mobileye,eyeq7h-mips2-olb
- mobileye,eyeq7h-periph-east-olb
- mobileye,eyeq7h-south-olb
then:
properties:
clocks:
items:
- description: Reference input clock.
clock-names:
items:
- const: ref
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-east-olb
- mobileye,eyeq7h-west-olb
then:
properties:
clocks:
items:
- description: Reference input clock from the main oscillator.
- description: 100MHz reference input clock.
clock-names:
items:
- const: ref
- const: ref_100p0
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-acc0-olb
- mobileye,eyeq7h-acc1-olb
- mobileye,eyeq7h-periph-west-olb
- mobileye,eyeq7h-xnn0-olb
- mobileye,eyeq7h-xnn1-olb
then:
properties:
clocks:
items:
- description: 100MHz reference input clock.
- description: 106.6MHz reference input clock.
clock-names:
items:
- const: ref_100p0
- const: ref_106p6
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-ddr0-olb
- mobileye,eyeq7h-ddr1-olb
- mobileye,eyeq7h-east-olb
- mobileye,eyeq7h-periph-east-olb
- mobileye,eyeq7h-periph-west-olb
- mobileye,eyeq7h-west-olb
then:
properties:
'#reset-cells':
const: 1
required:
- '#reset-cells'
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-acc0-olb
- mobileye,eyeq7h-acc1-olb
- mobileye,eyeq7h-south-olb
- mobileye,eyeq7h-xnn0-olb
- mobileye,eyeq7h-xnn1-olb
then:
properties:
'#reset-cells':
const: 2
required:
- '#reset-cells'
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-mips0-olb
- mobileye,eyeq7h-mips1-olb
- mobileye,eyeq7h-mips2-olb
then:
properties:
'#reset-cells': false
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
system-controller0@45000000 {
compatible = "mobileye,eyeq7h-acc0-olb", "syscon";
reg = <0x0 0x45000000 0x0 0x1000>;
#reset-cells = <2>;
#clock-cells = <1>;
clocks = <&olb_south 7>, <&olb_east 5>;
clock-names = "ref_100p0", "ref_106p6";
};
};

2
drivers/clk/Makefile
View File

@ -157,7 +157,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-y += sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += tenstorrent/
obj-$(CONFIG_ARCH_THEAD) += thead/
obj-y += thead/
obj-y += ti/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_U8500) += ux500/

1268
drivers/clk/clk-eyeq.c
View File

File diff suppressed because it is too large Load Diff

78
drivers/clk/clk-fixed-factor.c
View File

@ -36,10 +36,14 @@ static int clk_factor_determine_rate(struct clk_hw *hw,
struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
struct clk_hw *parent_hw = clk_hw_get_parent(hw);
unsigned long best_parent;
if (!parent_hw)
return -EINVAL;
best_parent = (req->rate / fix->mult) * fix->div;
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
req->best_parent_rate = clk_hw_round_rate(parent_hw, best_parent);
}
req->rate = (req->best_parent_rate / fix->div) * fix->mult;
@ -90,7 +94,7 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *
clk_hw_unregister(&fix->hw);
}
static struct clk_hw *
struct clk_hw *
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
const char *name, const char *parent_name,
const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
@ -124,13 +128,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
init.name = name;
init.ops = &clk_fixed_factor_ops;
init.flags = flags;
if (parent_name)
init.parent_names = &parent_name;
else if (parent_hw)
init.parent_hws = &parent_hw;
init.parent_names = parent_name ? &parent_name : NULL;
init.parent_hws = parent_hw ? &parent_hw : NULL;
init.parent_data = pdata;
if (parent_name || parent_hw || pdata)
init.num_parents = 1;
else
init.parent_data = pdata;
init.num_parents = 1;
init.num_parents = 0;
hw = &fix->hw;
if (dev)
@ -148,6 +152,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
return hw;
}
EXPORT_SYMBOL_GPL(__clk_hw_register_fixed_factor);
/**
* devm_clk_hw_register_fixed_factor_index - Register a fixed factor clock with
@ -173,52 +178,6 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
/**
* devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
* pointer to parent clock
* @dev: device that is registering this clock
* @name: name of this clock
* @parent_hw: pointer to parent clk
* @flags: fixed factor flags
* @mult: multiplier
* @div: divider
*
* Return: Pointer to fixed factor clk_hw structure that was registered or
* an error pointer.
*/
struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
const char *name, const struct clk_hw *parent_hw,
unsigned long flags, unsigned int mult, unsigned int div)
{
const struct clk_parent_data pdata = { .index = -1 };
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
&pdata, flags, mult, div, 0, 0, true);
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
const char *name, const struct clk_hw *parent_hw,
unsigned long flags, unsigned int mult, unsigned int div)
{
const struct clk_parent_data pdata = { .index = -1 };
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
&pdata, flags, mult, div, 0, 0, false);
}
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
const struct clk_parent_data pdata = { .index = -1 };
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
&pdata, flags, mult, div, 0, 0, false);
}
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div)
@ -292,17 +251,6 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
const struct clk_parent_data pdata = { .index = -1 };
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
&pdata, flags, mult, div, 0, 0, true);
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div)

27
drivers/clk/meson/Kconfig
View File

@ -132,6 +132,33 @@ config COMMON_CLK_A1_PERIPHERALS
device, A1 SoC Family. Say Y if you want A1 Peripherals clock
controller to work.
config COMMON_CLK_A9_PERIPHERALS
tristate "Amlogic A9 SoC peripherals clock controller support"
depends on ARM64 || COMPILE_TEST
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_VID_PLL_DIV
imply COMMON_CLK_SCMI
help
Support for the peripherals clock controller on Amlogic A311Y3 based
device, AKA A9. Peripherals are required by most peripheral to operate.
Say Y if you want A9 peripherals clock controller to work.
config COMMON_CLK_A9_AO
tristate "Amlogic A9 SoC AO clock controller support"
depends on ARM64 || COMPILE_TEST
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_DUALDIV
imply COMMON_CLK_SCMI
help
Support for the AO clock controller on Amlogic A311Y3 based
device, AKA A9.
Say Y if you want A9 AO clock controller to work.
config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64

2
drivers/clk/meson/Makefile
View File

@ -19,6 +19,8 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o
obj-$(CONFIG_COMMON_CLK_A9_AO) += a9-aoclk.o
obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o

489
drivers/clk/meson/a9-aoclk.c Normal file
View File

@ -0,0 +1,489 @@
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Copyright (C) 2026 Amlogic, Inc. All rights reserved
*/
#include <dt-bindings/clock/amlogic,a9-aoclkc.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-regmap.h"
#include "clk-dualdiv.h"
#include "meson-clkc-utils.h"
#define AO_OSCIN_CTRL 0x00
#define AO_SYS_CLK0 0x04
#define AO_PWM_CLK_A_CTRL 0x1c
#define AO_PWM_CLK_B_CTRL 0x20
#define AO_PWM_CLK_C_CTRL 0x24
#define AO_PWM_CLK_D_CTRL 0x28
#define AO_PWM_CLK_E_CTRL 0x2c
#define AO_PWM_CLK_F_CTRL 0x30
#define AO_PWM_CLK_G_CTRL 0x34
#define AO_CEC_CTRL0 0x38
#define AO_CEC_CTRL1 0x3c
#define AO_RTC_BY_OSCIN_CTRL0 0x50
#define AO_RTC_BY_OSCIN_CTRL1 0x54
#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
MESON_COMP_SEL(a9_ao_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
#define A9_COMP_DIV(_name, _reg, _shift, _width) \
MESON_COMP_DIV(a9_ao_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
#define A9_COMP_GATE(_name, _reg, _bit) \
MESON_COMP_GATE(a9_ao_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
static struct clk_regmap a9_ao_xtal_in = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_OSCIN_CTRL,
.bit_idx = 3,
},
.hw.init = &(struct clk_init_data) {
.name = "ao_xtal_in",
.ops = &clk_regmap_gate_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1,
},
};
static struct clk_regmap a9_ao_xtal = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_OSCIN_CTRL,
.mask = 0x1,
.shift = 0,
},
.hw.init = &(struct clk_init_data){
.name = "ao_xtal",
.ops = &clk_regmap_mux_ops,
/* ext_32k is from external PAD, do not automatically reparent */
.parent_data = (const struct clk_parent_data []) {
{ .hw = &a9_ao_xtal_in.hw },
{ .fw_name = "ext_32k", },
},
.num_parents = 2,
.flags = CLK_SET_RATE_NO_REPARENT,
},
};
static struct clk_regmap a9_ao_sys = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_OSCIN_CTRL,
.mask = 0x1,
.shift = 1,
},
.hw.init = &(struct clk_init_data){
.name = "ao_sys",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .hw = &a9_ao_xtal.hw },
{ .fw_name = "sys", },
},
.num_parents = 2,
},
};
static const struct clk_parent_data a9_ao_pclk_parents = { .hw = &a9_ao_sys.hw };
#define A9_AO_PCLK(_name, _bit, _flags) \
MESON_PCLK(a9_ao_sys_##_name, AO_SYS_CLK0, _bit, \
&a9_ao_pclk_parents, _flags)
/*
* A9 integrates a low-power microprocessor (Always-on CPU: AOCPU). Some AO sys
* clocks control the AOCPU modules. Mark the AOCPU-related clocks with
* CLK_IS_CRITICAL to avoid them being disabled and impacting AOCPU functionality.
* AOCPU-related clocks list:
* - clktree
* - rst_ctrl
* - pad
* - irq
* - pwrctrl
* - aocpu
* - sram
*/
static A9_AO_PCLK(i3c, 0, 0);
static A9_AO_PCLK(rtc_reg, 1, 0);
static A9_AO_PCLK(clktree, 2, CLK_IS_CRITICAL);
static A9_AO_PCLK(rst_ctrl, 3, CLK_IS_CRITICAL);
static A9_AO_PCLK(pad, 4, CLK_IS_CRITICAL);
static A9_AO_PCLK(rtc_dig, 5, 0);
static A9_AO_PCLK(irq, 6, CLK_IS_CRITICAL);
static A9_AO_PCLK(pwrctrl, 7, CLK_IS_CRITICAL);
static A9_AO_PCLK(pwm_a, 8, 0);
static A9_AO_PCLK(pwm_b, 9, 0);
static A9_AO_PCLK(pwm_c, 10, 0);
static A9_AO_PCLK(pwm_d, 11, 0);
static A9_AO_PCLK(pwm_e, 12, 0);
static A9_AO_PCLK(pwm_f, 13, 0);
static A9_AO_PCLK(pwm_g, 14, 0);
static A9_AO_PCLK(i2c_a, 15, 0);
static A9_AO_PCLK(i2c_b, 16, 0);
static A9_AO_PCLK(i2c_c, 17, 0);
static A9_AO_PCLK(i2c_d, 18, 0);
static A9_AO_PCLK(sed, 19, 0);
static A9_AO_PCLK(ir_ctrl, 20, 0);
static A9_AO_PCLK(uart_b, 21, 0);
static A9_AO_PCLK(uart_c, 22, 0);
static A9_AO_PCLK(uart_d, 23, 0);
static A9_AO_PCLK(uart_e, 24, 0);
static A9_AO_PCLK(spisg_0, 25, 0);
static A9_AO_PCLK(rtc_secure, 26, 0);
static A9_AO_PCLK(cec, 27, 0);
static A9_AO_PCLK(aocpu, 28, CLK_IS_CRITICAL);
static A9_AO_PCLK(sram, 29, CLK_IS_CRITICAL);
static A9_AO_PCLK(spisg_1, 30, 0);
static A9_AO_PCLK(spisg_2, 31, 0);
static const struct clk_parent_data a9_ao_pwm_parents[] = {
{ .hw = &a9_ao_xtal.hw },
{ .fw_name = "fdiv5", },
{ .fw_name = "fdiv4", },
{ .fw_name = "fdiv3", }
};
static A9_COMP_SEL(pwm_a, AO_PWM_CLK_A_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_a, AO_PWM_CLK_A_CTRL, 0, 8);
static A9_COMP_GATE(pwm_a, AO_PWM_CLK_A_CTRL, 8);
static A9_COMP_SEL(pwm_b, AO_PWM_CLK_B_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_b, AO_PWM_CLK_B_CTRL, 0, 8);
static A9_COMP_GATE(pwm_b, AO_PWM_CLK_B_CTRL, 8);
static A9_COMP_SEL(pwm_c, AO_PWM_CLK_C_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_c, AO_PWM_CLK_C_CTRL, 0, 8);
static A9_COMP_GATE(pwm_c, AO_PWM_CLK_C_CTRL, 8);
static A9_COMP_SEL(pwm_d, AO_PWM_CLK_D_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_d, AO_PWM_CLK_D_CTRL, 0, 8);
static A9_COMP_GATE(pwm_d, AO_PWM_CLK_D_CTRL, 8);
static A9_COMP_SEL(pwm_e, AO_PWM_CLK_E_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_e, AO_PWM_CLK_E_CTRL, 0, 8);
static A9_COMP_GATE(pwm_e, AO_PWM_CLK_E_CTRL, 8);
static A9_COMP_SEL(pwm_f, AO_PWM_CLK_F_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_f, AO_PWM_CLK_F_CTRL, 0, 8);
static A9_COMP_GATE(pwm_f, AO_PWM_CLK_F_CTRL, 8);
static A9_COMP_SEL(pwm_g, AO_PWM_CLK_G_CTRL, 9, 0x7, a9_ao_pwm_parents);
static A9_COMP_DIV(pwm_g, AO_PWM_CLK_G_CTRL, 0, 8);
static A9_COMP_GATE(pwm_g, AO_PWM_CLK_G_CTRL, 8);
static struct clk_regmap a9_ao_rtc_dualdiv_in = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_BY_OSCIN_CTRL0,
.bit_idx = 31,
},
.hw.init = &(struct clk_init_data) {
.name = "ao_rtc_dualdiv_in",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_xtal.hw
},
.num_parents = 1,
},
};
static const struct meson_clk_dualdiv_param a9_ao_dualdiv_table[] = {
{ 733, 732, 8, 11, 1 },
{ /* sentinel */ }
};
static struct clk_regmap a9_ao_rtc_dualdiv_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_RTC_BY_OSCIN_CTRL0,
.shift = 0,
.width = 12,
},
.n2 = {
.reg_off = AO_RTC_BY_OSCIN_CTRL0,
.shift = 12,
.width = 12,
},
.m1 = {
.reg_off = AO_RTC_BY_OSCIN_CTRL1,
.shift = 0,
.width = 12,
},
.m2 = {
.reg_off = AO_RTC_BY_OSCIN_CTRL1,
.shift = 12,
.width = 12,
},
.dual = {
.reg_off = AO_RTC_BY_OSCIN_CTRL0,
.shift = 28,
.width = 1,
},
.table = a9_ao_dualdiv_table,
},
.hw.init = &(struct clk_init_data){
.name = "a9_ao_rtc_dualdiv_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_rtc_dualdiv_in.hw
},
.num_parents = 1,
},
};
static struct clk_regmap a9_ao_rtc_dualdiv_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTC_BY_OSCIN_CTRL1,
.mask = 0x1,
.shift = 24,
},
.hw.init = &(struct clk_init_data){
.name = "ao_rtc_dualdiv_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_rtc_dualdiv_div.hw,
&a9_ao_rtc_dualdiv_in.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap a9_ao_rtc_dualdiv = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_BY_OSCIN_CTRL0,
.bit_idx = 30,
},
.hw.init = &(struct clk_init_data) {
.name = "ao_rtc_dualdiv",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_rtc_dualdiv_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap a9_ao_rtc = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTC_BY_OSCIN_CTRL1,
.mask = 0x1,
.shift = 30,
},
.hw.init = &(struct clk_init_data){
.name = "ao_rtc",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_xtal.hw,
&a9_ao_rtc_dualdiv.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap a9_ao_cec_dualdiv_in = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_CEC_CTRL0,
.bit_idx = 31,
},
.hw.init = &(struct clk_init_data) {
.name = "ao_cec_dualdiv_in",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_xtal.hw
},
.num_parents = 1,
},
};
static struct clk_regmap a9_ao_cec_dualdiv_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_CEC_CTRL0,
.shift = 0,
.width = 12,
},
.n2 = {
.reg_off = AO_CEC_CTRL0,
.shift = 12,
.width = 12,
},
.m1 = {
.reg_off = AO_CEC_CTRL1,
.shift = 0,
.width = 12,
},
.m2 = {
.reg_off = AO_CEC_CTRL1,
.shift = 12,
.width = 12,
},
.dual = {
.reg_off = AO_CEC_CTRL0,
.shift = 28,
.width = 1,
},
.table = a9_ao_dualdiv_table,
},
.hw.init = &(struct clk_init_data){
.name = "ao_cec_dualdiv_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_cec_dualdiv_in.hw
},
.num_parents = 1,
},
};
static struct clk_regmap a9_ao_cec_dualdiv_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_CEC_CTRL1,
.mask = 0x1,
.shift = 24,
},
.hw.init = &(struct clk_init_data){
.name = "ao_cec_dualdiv_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_cec_dualdiv_div.hw,
&a9_ao_cec_dualdiv_in.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap a9_ao_cec_dualdiv = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_CEC_CTRL0,
.bit_idx = 30,
},
.hw.init = &(struct clk_init_data){
.name = "ao_cec_dualdiv",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_cec_dualdiv_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap a9_ao_cec = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_CEC_CTRL1,
.mask = 0x1,
.shift = 30,
},
.hw.init = &(struct clk_init_data){
.name = "ao_cec",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&a9_ao_cec_dualdiv.hw,
&a9_ao_rtc.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_hw *a9_ao_hw_clks[] = {
[CLKID_AO_XTAL_IN] = &a9_ao_xtal_in.hw,
[CLKID_AO_XTAL] = &a9_ao_xtal.hw,
[CLKID_AO_SYS] = &a9_ao_sys.hw,
[CLKID_AO_SYS_I3C] = &a9_ao_sys_i3c.hw,
[CLKID_AO_SYS_RTC_REG] = &a9_ao_sys_rtc_reg.hw,
[CLKID_AO_SYS_CLKTREE] = &a9_ao_sys_clktree.hw,
[CLKID_AO_SYS_RST_CTRL] = &a9_ao_sys_rst_ctrl.hw,
[CLKID_AO_SYS_PAD] = &a9_ao_sys_pad.hw,
[CLKID_AO_SYS_RTC_DIG] = &a9_ao_sys_rtc_dig.hw,
[CLKID_AO_SYS_IRQ] = &a9_ao_sys_irq.hw,
[CLKID_AO_SYS_PWRCTRL] = &a9_ao_sys_pwrctrl.hw,
[CLKID_AO_SYS_PWM_A] = &a9_ao_sys_pwm_a.hw,
[CLKID_AO_SYS_PWM_B] = &a9_ao_sys_pwm_b.hw,
[CLKID_AO_SYS_PWM_C] = &a9_ao_sys_pwm_c.hw,
[CLKID_AO_SYS_PWM_D] = &a9_ao_sys_pwm_d.hw,
[CLKID_AO_SYS_PWM_E] = &a9_ao_sys_pwm_e.hw,
[CLKID_AO_SYS_PWM_F] = &a9_ao_sys_pwm_f.hw,
[CLKID_AO_SYS_PWM_G] = &a9_ao_sys_pwm_g.hw,
[CLKID_AO_SYS_I2C_A] = &a9_ao_sys_i2c_a.hw,
[CLKID_AO_SYS_I2C_B] = &a9_ao_sys_i2c_b.hw,
[CLKID_AO_SYS_I2C_C] = &a9_ao_sys_i2c_c.hw,
[CLKID_AO_SYS_I2C_D] = &a9_ao_sys_i2c_d.hw,
[CLKID_AO_SYS_SED] = &a9_ao_sys_sed.hw,
[CLKID_AO_SYS_IR_CTRL] = &a9_ao_sys_ir_ctrl.hw,
[CLKID_AO_SYS_UART_B] = &a9_ao_sys_uart_b.hw,
[CLKID_AO_SYS_UART_C] = &a9_ao_sys_uart_c.hw,
[CLKID_AO_SYS_UART_D] = &a9_ao_sys_uart_d.hw,
[CLKID_AO_SYS_UART_E] = &a9_ao_sys_uart_e.hw,
[CLKID_AO_SYS_SPISG_0] = &a9_ao_sys_spisg_0.hw,
[CLKID_AO_SYS_RTC_SECURE] = &a9_ao_sys_rtc_secure.hw,
[CLKID_AO_SYS_CEC] = &a9_ao_sys_cec.hw,
[CLKID_AO_SYS_AOCPU] = &a9_ao_sys_aocpu.hw,
[CLKID_AO_SYS_SRAM] = &a9_ao_sys_sram.hw,
[CLKID_AO_SYS_SPISG_1] = &a9_ao_sys_spisg_1.hw,
[CLKID_AO_SYS_SPISG_2] = &a9_ao_sys_spisg_2.hw,
[CLKID_AO_PWM_A_SEL] = &a9_ao_pwm_a_sel.hw,
[CLKID_AO_PWM_A_DIV] = &a9_ao_pwm_a_div.hw,
[CLKID_AO_PWM_A] = &a9_ao_pwm_a.hw,
[CLKID_AO_PWM_B_SEL] = &a9_ao_pwm_b_sel.hw,
[CLKID_AO_PWM_B_DIV] = &a9_ao_pwm_b_div.hw,
[CLKID_AO_PWM_B] = &a9_ao_pwm_b.hw,
[CLKID_AO_PWM_C_SEL] = &a9_ao_pwm_c_sel.hw,
[CLKID_AO_PWM_C_DIV] = &a9_ao_pwm_c_div.hw,
[CLKID_AO_PWM_C] = &a9_ao_pwm_c.hw,
[CLKID_AO_PWM_D_SEL] = &a9_ao_pwm_d_sel.hw,
[CLKID_AO_PWM_D_DIV] = &a9_ao_pwm_d_div.hw,
[CLKID_AO_PWM_D] = &a9_ao_pwm_d.hw,
[CLKID_AO_PWM_E_SEL] = &a9_ao_pwm_e_sel.hw,
[CLKID_AO_PWM_E_DIV] = &a9_ao_pwm_e_div.hw,
[CLKID_AO_PWM_E] = &a9_ao_pwm_e.hw,
[CLKID_AO_PWM_F_SEL] = &a9_ao_pwm_f_sel.hw,
[CLKID_AO_PWM_F_DIV] = &a9_ao_pwm_f_div.hw,
[CLKID_AO_PWM_F] = &a9_ao_pwm_f.hw,
[CLKID_AO_PWM_G_SEL] = &a9_ao_pwm_g_sel.hw,
[CLKID_AO_PWM_G_DIV] = &a9_ao_pwm_g_div.hw,
[CLKID_AO_PWM_G] = &a9_ao_pwm_g.hw,
[CLKID_AO_RTC_DUALDIV_IN] = &a9_ao_rtc_dualdiv_in.hw,
[CLKID_AO_RTC_DUALDIV_DIV] = &a9_ao_rtc_dualdiv_div.hw,
[CLKID_AO_RTC_DUALDIV_SEL] = &a9_ao_rtc_dualdiv_sel.hw,
[CLKID_AO_RTC_DUALDIV] = &a9_ao_rtc_dualdiv.hw,
[CLKID_AO_RTC] = &a9_ao_rtc.hw,
[CLKID_AO_CEC_DUALDIV_IN] = &a9_ao_cec_dualdiv_in.hw,
[CLKID_AO_CEC_DUALDIV_DIV] = &a9_ao_cec_dualdiv_div.hw,
[CLKID_AO_CEC_DUALDIV_SEL] = &a9_ao_cec_dualdiv_sel.hw,
[CLKID_AO_CEC_DUALDIV] = &a9_ao_cec_dualdiv.hw,
[CLKID_AO_CEC] = &a9_ao_cec.hw,
};
static const struct meson_clkc_data a9_ao_clkc_data = {
.hw_clks = {
.hws = a9_ao_hw_clks,
.num = ARRAY_SIZE(a9_ao_hw_clks),
},
};
static const struct of_device_id a9_ao_clkc_match_table[] = {
{
.compatible = "amlogic,a9-aoclkc",
.data = &a9_ao_clkc_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, a9_ao_clkc_match_table);
static struct platform_driver a9_ao_clkc_driver = {
.probe = meson_clkc_mmio_probe,
.driver = {
.name = "a9-aoclkc",
.of_match_table = a9_ao_clkc_match_table,
},
};
module_platform_driver(a9_ao_clkc_driver);
MODULE_DESCRIPTION("Amlogic A9 Always-ON Clock Controller driver");
MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS("CLK_MESON");

2089
drivers/clk/meson/a9-peripherals.c Normal file
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File diff suppressed because it is too large Load Diff

2
drivers/clk/meson/gxbb.c
View File

@ -1393,7 +1393,7 @@ static struct clk_regmap gxbb_32k_clk_sel = {
.name = "32k_clk_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = gxbb_32k_clk_parents,
.num_parents = 4,
.num_parents = ARRAY_SIZE(gxbb_32k_clk_parents),
.flags = CLK_SET_RATE_PARENT,
},
};

41
drivers/clk/spacemit/ccu-k3.c
View File

@ -218,11 +218,19 @@ static const struct clk_parent_data i2s_sysclk_src_parents[] = {
CCU_PARENT_HW(pll1_d96_25p6),
CCU_PARENT_HW(i2s_153p6_base),
};
CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0);
CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR1, 30, 1, BIT(31), 0);
CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0);
CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR1, 0, 15, 15, 12, 1, 0);
CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0);
CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1);
/*
* Divider of i2s_bclk always implies a 1/2 factor, which is
* described by i2s_bclk_factor.
*/
CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR1, 27, 2, BIT(29), 0);
CCU_MUX_GATE_DEFINE(i2s1_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR0, 30, 1, BIT(31), 0);
CCU_DDN_DEFINE(i2s1_sysclk, i2s1_sysclk_src, MPMU_ISCCR0, 0, 15, 15, 12, 1, 0);
static const struct clk_parent_data i2s_sysclk_parents[] = {
CCU_PARENT_HW(pll1_d4_614p4),
@ -236,14 +244,14 @@ CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2,
CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0);
CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0);
CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0);
CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 2, 0);
CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 2, 0);
static const struct clk_parent_data i2s2_sysclk_parents[] = {
CCU_PARENT_HW(i2s1_sysclk),
CCU_PARENT_HW(i2s_sysclk),
CCU_PARENT_HW(i2s2_sysclk_div),
};
CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0);
@ -926,15 +934,16 @@ CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 1
20, 3, BIT(16), 0);
static const struct clk_parent_data ufs_aclk_parents[] = {
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll1_d8_307p2),
CCU_PARENT_HW(pll2_d4),
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll2_d6),
CCU_PARENT_HW(pll2_d5),
};
CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8),
2, 3, BIT(1), 0);
CCU_FACTOR_DEFINE(ufs_refclk, CCU_PARENT_HW(pll1_d64_38p4), 2, 1);
static const struct clk_parent_data edp0_pclk_parents[] = {
CCU_PARENT_HW(lcd_pxclk),
CCU_PARENT_NAME(external_clk),
@ -1161,8 +1170,11 @@ static struct clk_hw *k3_ccu_mpmu_hws[] = {
[CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw,
[CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw,
[CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw,
[CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw,
[CLK_MPMU_I2S_SYSCLK] = &i2s_sysclk.common.hw,
[CLK_MPMU_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw,
[CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw,
[CLK_MPMU_I2S1_SYSCLK_SRC] = &i2s1_sysclk_src.common.hw,
[CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw,
[CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw,
[CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw,
[CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw,
@ -1392,6 +1404,7 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw,
[CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw,
[CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw,
[CLK_APMU_UFS_REFCLK] = &ufs_refclk.common.hw,
[CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw,
[CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
[CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,

271
drivers/reset/reset-eyeq.c
View File

@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
* Reset driver for the Mobileye EyeQ5, EyeQ6L, EyeQ6H and EyeQ7H platforms.
*
* Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
* have a single OLB instance for a single reset controller. EyeQ6H has seven
* OLB instances; three host reset controllers.
* OLB instances; three host reset controllers. EyeQ7H has fourteen OLB instances;
* eleven host reset controllers.
*
* Each reset controller has one or more domain. Domains are of a given type
* (see enum eqr_domain_type), with a valid offset mask (up to 32 resets per
@ -73,6 +74,43 @@
* 9. PMA0 10. PMA1 11. MPC0 12. MPC1
* 13. MPC2 14. MPC3 15. PERIPH
*
* Known resets in EyeQ7H acc domain 0 (type EQR_EYEQ7H_ACRP)
* 0. VMP0 1. XVMP1 2. VMP2 3. VMP3
* 4. MPC0 5. MPC1 6. PMA0 7. PMA1
*
* Known resets in EyeQ7H acc domain 1 (type EQR_EYEQ7H_ACC)
* 0. NCORE0 1. NCORE1 2. NCORE0_M 3. NCORE1_M
* 4. NCORE_NOC 5. VMP_NOC 6. MPC_NOC 7. PMA_NOC
*
* Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG)
* 0. APB 1. DMI 2. DFI 3. PHY_SMS
* 4. CTL_SMS
*
* Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG)
* 0. ISP 1. VEU 2. LBIST
*
* Known resets in EyeQ7H periph (type EQR_EYEQ6H_SARCR)
* 0. gpio 1.EXT TIMER 2.UART 3. SPI
* 4. I2C0 5. I2C1 6.I2C2 7. I2S
*
* Known resets in EyeQ7H south domain 0 (type EQR_EYEQ7H_CFG)
* 0. PCI_PHY 1. PCI_CTL 2. S_NOC 3. GBE_PHY
* 4. GBE_CTL
*
* Known resets in EyeQ7H south domain 1 (type EQR_EYEQ7H_CFG)
* 0. XSPI 1. UFS 2. VDIO
*
* Known resets in EyeQ7H west (type EQR_EYEQ7H_CFG)
* 0. GPU 1. CAU 2. LBIST 3. GPU_LBIST
*
* Known resets in EyeQ7H xnn domain 0 (type EQR_EYEQ7H_ACRP)
* 0. XNN0 1. XNN1 2.XNN2
*
* Known resets in EyeQ7H xnn domain 1 (type EQR_EYEQ7H_ACC)
* 0. XNN0 1. XNN1 2. XNN2 3. XNN3
* 4. NCORE 5. L2_0 6. L2_1 7. SMS_0
* 8. SMS_1
*
* Abbreviations:
* - PMA: Programmable Macro Array
* - MPC: Multi-threaded Processing Clusters
@ -113,6 +151,11 @@ enum eqr_domain_type {
EQR_EYEQ5_ACRP,
EQR_EYEQ5_PCIE,
EQR_EYEQ6H_SARCR,
EQR_EYEQ7H_ACC,
EQR_EYEQ7H_ACRP,
EQR_EYEQ7H_CFG,
EQR_NB_DOM_TYPES /* number of domain types, keep at the end */
};
/*
@ -137,16 +180,34 @@ enum eqr_domain_type {
#define EQR_EYEQ6H_SARCR_RST_STATUS (0x008)
#define EQR_EYEQ6H_SARCR_CLK_REQUEST (0x00C)
/*
* Domain type EQR_EYEQ7H_ACC register offsets.
*/
#define EQR_EYEQ7H_ACC_CLK_EN (0x000)
#define EQR_EYEQ7H_ACC_RST_EN (0x004)
/*
* Domain type EQR_EYEQ7H_ACRP register masks.
* Registers are: base + 4 * offset.
*/
#define EQR_EYEQ7H_ACRP_PD_REQ BIT(0)
#define EQR_EYEQ7H_ACRP_MBIST_CFG GENMASK(3, 1)
#define EQR_EYEQ7H_ACRP_ST_POWER_DOWN BIT(13)
#define EQR_EYEQ7H_ACRP_ST_ACTIVE BIT(14)
struct eqr_busy_wait_timings {
unsigned long sleep_us;
unsigned long timeout_us;
};
static const struct eqr_busy_wait_timings eqr_timings[] = {
static const struct eqr_busy_wait_timings eqr_timings[EQR_NB_DOM_TYPES] = {
[EQR_EYEQ5_SARCR] = {1, 10},
[EQR_EYEQ5_ACRP] = {1, 40 * USEC_PER_MSEC}, /* LBIST implies long timeout. */
/* EQR_EYEQ5_PCIE does no busy waiting. */
[EQR_EYEQ6H_SARCR] = {1, 400},
/* EQR_EYEQ7H_ACC does no busy waiting. */
[EQR_EYEQ7H_ACRP] = {1, 40 * USEC_PER_MSEC},
/* EQR_EYEQ7H_CFG does no busy waiting. */
};
#define EQR_MAX_DOMAIN_COUNT 3
@ -220,10 +281,6 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
sleep_us, timeout_us);
break;
case EQR_EYEQ5_PCIE:
ret = 0; /* No busy waiting. */
break;
case EQR_EYEQ6H_SARCR:
/*
* Wait until both bits change:
@ -240,6 +297,23 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
&rst_status, &clk_status);
break;
case EQR_EYEQ7H_ACRP:
reg = base + 4 * offset;
if (assert)
mask = EQR_EYEQ7H_ACRP_ST_POWER_DOWN;
else
mask = EQR_EYEQ7H_ACRP_ST_ACTIVE;
ret = readl_poll_timeout(reg, val, !!(val & mask),
sleep_us, timeout_us);
break;
case EQR_EYEQ5_PCIE:
case EQR_EYEQ7H_ACC:
case EQR_EYEQ7H_CFG:
ret = 0; /* No busy waiting. */
break;
default:
WARN_ON(1);
ret = -EINVAL;
@ -284,6 +358,28 @@ static void eqr_assert_locked(struct eqr_private *priv, u32 domain, u32 offset)
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
break;
case EQR_EYEQ7H_ACC:
/* RST_REQUEST and CLK_REQUEST must be kept in sync. */
val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
val &= ~BIT(offset);
writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
break;
case EQR_EYEQ7H_ACRP:
/* set powerdown and leave MBIST bits at zero */
reg = base + 4 * offset;
val = readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG;
writel(val | EQR_EYEQ7H_ACRP_PD_REQ, reg);
break;
case EQR_EYEQ7H_CFG:
/* clear clock enable and NRESET bits */
val = readl(base);
val &= ~GENMASK(2 * offset + 1, 2 * offset);
writel(val, base);
break;
default:
WARN_ON(1);
break;
@ -338,6 +434,28 @@ static void eqr_deassert_locked(struct eqr_private *priv, u32 domain,
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
break;
case EQR_EYEQ7H_ACC:
/* RST_REQUEST and CLK_REQUEST must be kept in sync. */
val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
val |= BIT(offset);
writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
break;
case EQR_EYEQ7H_ACRP:
/* clear powerdown and leave MBIST bits at zero */
reg = base + 4 * offset;
val = readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG;
writel(val & ~EQR_EYEQ7H_ACRP_PD_REQ, reg);
break;
case EQR_EYEQ7H_CFG:
/* set clock enable and NRESET bits */
val = readl(base);
val |= GENMASK(2 * offset + 1, 2 * offset);
writel(val, base);
break;
default:
WARN_ON(1);
break;
@ -384,6 +502,14 @@ static int eqr_status(struct reset_controller_dev *rcdev, unsigned long id)
case EQR_EYEQ6H_SARCR:
reg = base + EQR_EYEQ6H_SARCR_RST_STATUS;
return !(readl(reg) & BIT(offset));
case EQR_EYEQ7H_ACC:
reg = base + EQR_EYEQ7H_ACC_RST_EN;
return !(readl(reg) & BIT(offset));
case EQR_EYEQ7H_ACRP:
reg = base + 4 * offset;
return !(readl(reg) & EQR_EYEQ7H_ACRP_ST_ACTIVE);
case EQR_EYEQ7H_CFG:
return !(readl(base) & BIT(2 * offset));
default:
return -EINVAL;
}
@ -557,6 +683,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = {
.domains = eqr_eyeq6h_acc_domains,
};
static const struct eqr_domain_descriptor eqr_eyeq7h_acc_domains[] = {
{
.type = EQR_EYEQ7H_ACRP,
.valid_mask = 0xFF,
.offset = 0x000,
},
{
.type = EQR_EYEQ7H_ACC,
.valid_mask = 0xFF,
.offset = 0x060,
},
};
static const struct eqr_match_data eqr_eyeq7h_acc_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_acc_domains),
.domains = eqr_eyeq7h_acc_domains,
};
static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] = {
{
.type = EQR_EYEQ7H_CFG,
.valid_mask = 0x1F,
.offset = 0x008,
},
};
static const struct eqr_match_data eqr_eyeq7h_ddr_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_ddr_domains),
.domains = eqr_eyeq7h_ddr_domains,
};
static const struct eqr_domain_descriptor eqr_eyeq7h_east_domains[] = {
{
.type = EQR_EYEQ7H_CFG,
.valid_mask = 0x7,
.offset = 0x060,
},
};
static const struct eqr_match_data eqr_eyeq7h_east_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_east_domains),
.domains = eqr_eyeq7h_east_domains,
};
/* Periph OLBs each have an instance. */
static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] = {
{
.type = EQR_EYEQ6H_SARCR,
.valid_mask = 0xFF,
.offset = 0x030,
},
};
static const struct eqr_match_data eqr_eyeq7h_per_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_per_domains),
.domains = eqr_eyeq7h_per_domains,
};
static const struct eqr_domain_descriptor eqr_eyeq7h_south_domains[] = {
{
.type = EQR_EYEQ7H_CFG,
.valid_mask = 0x1F,
.offset = 0x070,
},
{
.type = EQR_EYEQ7H_CFG,
.valid_mask = 0x7,
.offset = 0x074,
},
};
static const struct eqr_match_data eqr_eyeq7h_south_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_south_domains),
.domains = eqr_eyeq7h_south_domains,
};
static const struct eqr_domain_descriptor eqr_eyeq7h_west_domains[] = {
{
.type = EQR_EYEQ7H_CFG,
.valid_mask = 0xf,
.offset = 0x068,
},
};
static const struct eqr_match_data eqr_eyeq7h_west_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_west_domains),
.domains = eqr_eyeq7h_west_domains,
};
static const struct eqr_domain_descriptor eqr_eyeq7h_xnn_domains[] = {
{
.type = EQR_EYEQ7H_ACRP,
.valid_mask = 0x7,
.offset = 0x000,
},
{
.type = EQR_EYEQ7H_ACC,
.valid_mask = 0x1FF,
.offset = 0x060,
},
};
static const struct eqr_match_data eqr_eyeq7h_xnn_data = {
.domain_count = ARRAY_SIZE(eqr_eyeq7h_xnn_domains),
.domains = eqr_eyeq7h_xnn_domains,
};
/*
* Table describes OLB system-controller compatibles.
* It does not get used to match against devicetree node.
@ -568,15 +801,35 @@ static const struct of_device_id eqr_match_table[] = {
{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },
{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },
{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },
{ .compatible = "mobileye,eyeq7h-acc0-olb", .data = &eqr_eyeq7h_acc_data },
{ .compatible = "mobileye,eyeq7h-acc1-olb", .data = &eqr_eyeq7h_acc_data },
{ .compatible = "mobileye,eyeq7h-ddr0-olb", .data = &eqr_eyeq7h_ddr_data },
{ .compatible = "mobileye,eyeq7h-ddr1-olb", .data = &eqr_eyeq7h_ddr_data },
{ .compatible = "mobileye,eyeq7h-east-olb", .data = &eqr_eyeq7h_east_data },
{ .compatible = "mobileye,eyeq7h-periph-east-olb", .data = &eqr_eyeq7h_per_data },
{ .compatible = "mobileye,eyeq7h-periph-west-olb", .data = &eqr_eyeq7h_per_data },
{ .compatible = "mobileye,eyeq7h-south-olb", .data = &eqr_eyeq7h_south_data },
{ .compatible = "mobileye,eyeq7h-west-olb", .data = &eqr_eyeq7h_west_data },
{ .compatible = "mobileye,eyeq7h-xnn0-olb", .data = &eqr_eyeq7h_xnn_data },
{ .compatible = "mobileye,eyeq7h-xnn1-olb", .data = &eqr_eyeq7h_xnn_data },
{}
};
MODULE_DEVICE_TABLE(of, eqr_match_table);
static const struct auxiliary_device_id eqr_id_table[] = {
{ .name = "clk_eyeq.reset" },
{ .name = "clk_eyeq.reset_west" },
{ .name = "clk_eyeq.reset_east" },
{ .name = "clk_eyeq.reset_acc" },
{ .name = "clk_eyeq.reset_acc0" },
{ .name = "clk_eyeq.reset_acc1" },
{ .name = "clk_eyeq.reset_ddr0" },
{ .name = "clk_eyeq.reset_ddr1" },
{ .name = "clk_eyeq.reset_east" },
{ .name = "clk_eyeq.reset_periph_east" },
{ .name = "clk_eyeq.reset_periph_west" },
{ .name = "clk_eyeq.reset_south" },
{ .name = "clk_eyeq.reset_west" },
{ .name = "clk_eyeq.reset_xnn0" },
{ .name = "clk_eyeq.reset_xnn1" },
{}
};
MODULE_DEVICE_TABLE(auxiliary, eqr_id_table);

76
include/dt-bindings/clock/amlogic,a9-aoclkc.h Normal file
View File

@ -0,0 +1,76 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2026 Amlogic, Inc. All rights reserved.
*/
#ifndef __AMLOGIC_A9_AO_CLKC_H
#define __AMLOGIC_A9_AO_CLKC_H
#define CLKID_AO_XTAL_IN 0
#define CLKID_AO_XTAL 1
#define CLKID_AO_SYS 2
#define CLKID_AO_SYS_I3C 3
#define CLKID_AO_SYS_RTC_REG 4
#define CLKID_AO_SYS_CLKTREE 5
#define CLKID_AO_SYS_RST_CTRL 6
#define CLKID_AO_SYS_PAD 7
#define CLKID_AO_SYS_RTC_DIG 8
#define CLKID_AO_SYS_IRQ 9
#define CLKID_AO_SYS_PWRCTRL 10
#define CLKID_AO_SYS_PWM_A 11
#define CLKID_AO_SYS_PWM_B 12
#define CLKID_AO_SYS_PWM_C 13
#define CLKID_AO_SYS_PWM_D 14
#define CLKID_AO_SYS_PWM_E 15
#define CLKID_AO_SYS_PWM_F 16
#define CLKID_AO_SYS_PWM_G 17
#define CLKID_AO_SYS_I2C_A 18
#define CLKID_AO_SYS_I2C_B 19
#define CLKID_AO_SYS_I2C_C 20
#define CLKID_AO_SYS_I2C_D 21
#define CLKID_AO_SYS_SED 22
#define CLKID_AO_SYS_IR_CTRL 23
#define CLKID_AO_SYS_UART_B 24
#define CLKID_AO_SYS_UART_C 25
#define CLKID_AO_SYS_UART_D 26
#define CLKID_AO_SYS_UART_E 27
#define CLKID_AO_SYS_SPISG_0 28
#define CLKID_AO_SYS_RTC_SECURE 29
#define CLKID_AO_SYS_CEC 30
#define CLKID_AO_SYS_AOCPU 31
#define CLKID_AO_SYS_SRAM 32
#define CLKID_AO_SYS_SPISG_1 33
#define CLKID_AO_SYS_SPISG_2 34
#define CLKID_AO_PWM_A_SEL 35
#define CLKID_AO_PWM_A_DIV 36
#define CLKID_AO_PWM_A 37
#define CLKID_AO_PWM_B_SEL 38
#define CLKID_AO_PWM_B_DIV 39
#define CLKID_AO_PWM_B 40
#define CLKID_AO_PWM_C_SEL 41
#define CLKID_AO_PWM_C_DIV 42
#define CLKID_AO_PWM_C 43
#define CLKID_AO_PWM_D_SEL 44
#define CLKID_AO_PWM_D_DIV 45
#define CLKID_AO_PWM_D 46
#define CLKID_AO_PWM_E_SEL 47
#define CLKID_AO_PWM_E_DIV 48
#define CLKID_AO_PWM_E 49
#define CLKID_AO_PWM_F_SEL 50
#define CLKID_AO_PWM_F_DIV 51
#define CLKID_AO_PWM_F 52
#define CLKID_AO_PWM_G_SEL 53
#define CLKID_AO_PWM_G_DIV 54
#define CLKID_AO_PWM_G 55
#define CLKID_AO_RTC_DUALDIV_IN 56
#define CLKID_AO_RTC_DUALDIV_DIV 57
#define CLKID_AO_RTC_DUALDIV_SEL 58
#define CLKID_AO_RTC_DUALDIV 59
#define CLKID_AO_RTC 60
#define CLKID_AO_CEC_DUALDIV_IN 61
#define CLKID_AO_CEC_DUALDIV_DIV 62
#define CLKID_AO_CEC_DUALDIV_SEL 63
#define CLKID_AO_CEC_DUALDIV 64
#define CLKID_AO_CEC 65
#endif /* __AMLOGIC_A9_AO_CLKC_H */

351
include/dt-bindings/clock/amlogic,a9-peripherals-clkc.h Normal file
View File

@ -0,0 +1,351 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2026 Amlogic, Inc. All rights reserved.
*/
#ifndef __AMLOGIC_A9_PERIPHERALS_CLKC_H
#define __AMLOGIC_A9_PERIPHERALS_CLKC_H
#define CLKID_SYS_AM_AXI 0
#define CLKID_SYS_DOS 1
#define CLKID_SYS_MIPI_DSI0 2
#define CLKID_SYS_ETH_PHY 3
#define CLKID_SYS_AMFC 4
#define CLKID_SYS_MALI 5
#define CLKID_SYS_NNA 6
#define CLKID_SYS_ETH_AXI 7
#define CLKID_SYS_DP_APB 8
#define CLKID_SYS_EDPTX_APB 9
#define CLKID_SYS_U3HSG 10
#define CLKID_SYS_AUCPU 11
#define CLKID_SYS_GLB 12
#define CLKID_SYS_COMBO_DPHY_APB 13
#define CLKID_SYS_HDMIRX_APB 14
#define CLKID_SYS_HDMIRX_PCLK 15
#define CLKID_SYS_MIPI_DSI0_PHY 16
#define CLKID_SYS_CAN0 17
#define CLKID_SYS_CAN1 18
#define CLKID_SYS_SD_EMMC_A 19
#define CLKID_SYS_SD_EMMC_B 20
#define CLKID_SYS_SD_EMMC_C 21
#define CLKID_SYS_SC 22
#define CLKID_SYS_ACODEC 23
#define CLKID_SYS_MIPI_ISP 24
#define CLKID_SYS_MSR 25
#define CLKID_SYS_AUDIO 26
#define CLKID_SYS_MIPI_DSI1 27
#define CLKID_SYS_MIPI_DSI1_PHY 28
#define CLKID_SYS_ETH 29
#define CLKID_SYS_ETH_1G_MAC 30
#define CLKID_SYS_UART_A 31
#define CLKID_SYS_UART_F 32
#define CLKID_SYS_TS_A55 33
#define CLKID_SYS_ETH_1G_AXI 34
#define CLKID_SYS_TS_DOS 35
#define CLKID_SYS_U3DRD_B 36
#define CLKID_SYS_TS_CORE 37
#define CLKID_SYS_TS_PLL 38
#define CLKID_SYS_CSI_DIG_CLKIN 39
#define CLKID_SYS_CVE 40
#define CLKID_SYS_GE2D 41
#define CLKID_SYS_SPISG 42
#define CLKID_SYS_U2H 43
#define CLKID_SYS_PCIE_MAC_A 44
#define CLKID_SYS_U3DRD_A 45
#define CLKID_SYS_U2DRD 46
#define CLKID_SYS_PCIE_PHY 47
#define CLKID_SYS_PCIE_MAC_B 48
#define CLKID_SYS_PERIPH 49
#define CLKID_SYS_PIO 50
#define CLKID_SYS_I3C 51
#define CLKID_SYS_I2C_M_E 52
#define CLKID_SYS_I2C_M_F 53
#define CLKID_SYS_HDMITX_APB 54
#define CLKID_SYS_I2C_M_I 55
#define CLKID_SYS_I2C_M_G 56
#define CLKID_SYS_I2C_M_H 57
#define CLKID_SYS_HDMI20_AES 58
#define CLKID_SYS_CSI2_HOST 59
#define CLKID_SYS_CSI2_ADAPT 60
#define CLKID_SYS_DSPA 61
#define CLKID_SYS_PP_DMA 62
#define CLKID_SYS_PP_WRAPPER 63
#define CLKID_SYS_VPU_INTR 64
#define CLKID_SYS_CSI2_PHY 65
#define CLKID_SYS_SARADC 66
#define CLKID_SYS_PWM_J 67
#define CLKID_SYS_PWM_I 68
#define CLKID_SYS_PWM_H 69
#define CLKID_SYS_PWM_N 70
#define CLKID_SYS_PWM_M 71
#define CLKID_SYS_PWM_L 72
#define CLKID_SYS_PWM_K 73
#define CLKID_SD_EMMC_A_SEL 74
#define CLKID_SD_EMMC_A_DIV 75
#define CLKID_SD_EMMC_A 76
#define CLKID_SD_EMMC_B_SEL 77
#define CLKID_SD_EMMC_B_DIV 78
#define CLKID_SD_EMMC_B 79
#define CLKID_SD_EMMC_C_SEL 80
#define CLKID_SD_EMMC_C_DIV 81
#define CLKID_SD_EMMC_C 82
#define CLKID_PWM_H_SEL 83
#define CLKID_PWM_H_DIV 84
#define CLKID_PWM_H 85
#define CLKID_PWM_I_SEL 86
#define CLKID_PWM_I_DIV 87
#define CLKID_PWM_I 88
#define CLKID_PWM_J_SEL 89
#define CLKID_PWM_J_DIV 90
#define CLKID_PWM_J 91
#define CLKID_PWM_K_SEL 92
#define CLKID_PWM_K_DIV 93
#define CLKID_PWM_K 94
#define CLKID_PWM_L_SEL 95
#define CLKID_PWM_L_DIV 96
#define CLKID_PWM_L 97
#define CLKID_PWM_M_SEL 98
#define CLKID_PWM_M_DIV 99
#define CLKID_PWM_M 100
#define CLKID_PWM_N_SEL 101
#define CLKID_PWM_N_DIV 102
#define CLKID_PWM_N 103
#define CLKID_SPISG0_SEL 104
#define CLKID_SPISG0_DIV 105
#define CLKID_SPISG0 106
#define CLKID_SPISG1_SEL 107
#define CLKID_SPISG1_DIV 108
#define CLKID_SPISG1 109
#define CLKID_SPISG2_SEL 110
#define CLKID_SPISG2_DIV 111
#define CLKID_SPISG2 112
#define CLKID_SARADC_SEL 113
#define CLKID_SARADC_DIV 114
#define CLKID_SARADC 115
#define CLKID_AMFC_SEL 116
#define CLKID_AMFC_DIV 117
#define CLKID_AMFC 118
#define CLKID_NNA_SEL 119
#define CLKID_NNA_DIV 120
#define CLKID_NNA 121
#define CLKID_USB_250M_SEL 122
#define CLKID_USB_250M_DIV 123
#define CLKID_USB_250M 124
#define CLKID_USB_48M_PRE_SEL 125
#define CLKID_USB_48M_PRE_DIV 126
#define CLKID_USB_48M_PRE 127
#define CLKID_PCIE0_TL_SEL 128
#define CLKID_PCIE0_TL_DIV 129
#define CLKID_PCIE0_TL 130
#define CLKID_PCIE1_TL_SEL 131
#define CLKID_PCIE1_TL_DIV 132
#define CLKID_PCIE1_TL 133
#define CLKID_CMPR_SEL 134
#define CLKID_CMPR_DIV 135
#define CLKID_CMPR 136
#define CLKID_DEWARPA_SEL 137
#define CLKID_DEWARPA_DIV 138
#define CLKID_DEWARPA 139
#define CLKID_SC_PRE_SEL 140
#define CLKID_SC_PRE_DIV 141
#define CLKID_SC_PRE 142
#define CLKID_SC 143
#define CLKID_DPTX_APB2_SEL 144
#define CLKID_DPTX_APB2_DIV 145
#define CLKID_DPTX_APB2 146
#define CLKID_DPTX_AUD_SEL 147
#define CLKID_DPTX_AUD_DIV 148
#define CLKID_DPTX_AUD 149
#define CLKID_ISP_SEL 150
#define CLKID_ISP_DIV 151
#define CLKID_ISP 152
#define CLKID_CVE_SEL 153
#define CLKID_CVE_DIV 154
#define CLKID_CVE 155
#define CLKID_VGE_SEL 156
#define CLKID_VGE_DIV 157
#define CLKID_VGE 158
#define CLKID_PP_SEL 159
#define CLKID_PP_DIV 160
#define CLKID_PP 161
#define CLKID_GLB_SEL 162
#define CLKID_GLB_DIV 163
#define CLKID_GLB 164
#define CLKID_USB_48M_DUALDIV_IN 165
#define CLKID_USB_48M_DUALDIV_DIV 166
#define CLKID_USB_48M_DUALDIV_SEL 167
#define CLKID_USB_48M_DUALDIV 168
#define CLKID_USB_48M 169
#define CLKID_CAN0_PE_SEL 170
#define CLKID_CAN0_PE_DIV 171
#define CLKID_CAN0_PE 172
#define CLKID_CAN1_PE_SEL 173
#define CLKID_CAN1_PE_DIV 174
#define CLKID_CAN1_PE 175
#define CLKID_CAN0_FILTER_SEL 176
#define CLKID_CAN0_FILTER_DIV 177
#define CLKID_CAN0_FILTER 178
#define CLKID_CAN1_FILTER_SEL 179
#define CLKID_CAN1_FILTER_DIV 180
#define CLKID_CAN1_FILTER 181
#define CLKID_I3C_SEL 182
#define CLKID_I3C_DIV 183
#define CLKID_I3C 184
#define CLKID_TS_DIV 185
#define CLKID_TS 186
#define CLKID_ETH_125M_DIV 187
#define CLKID_ETH_125M 188
#define CLKID_ETH_RMII_SEL 189
#define CLKID_ETH_RMII_DIV 190
#define CLKID_ETH_RMII 191
#define CLKID_GEN_SEL 192
#define CLKID_GEN_DIV 193
#define CLKID_GEN 194
#define CLKID_CLK24M_IN 195
#define CLKID_CLK12_24M 196
#define CLKID_MALI_0_SEL 197
#define CLKID_MALI_0_DIV 198
#define CLKID_MALI_0 199
#define CLKID_MALI_1_SEL 200
#define CLKID_MALI_1_DIV 201
#define CLKID_MALI_1 202
#define CLKID_MALI 203
#define CLKID_MALI_STACK_0_SEL 204
#define CLKID_MALI_STACK_0_DIV 205
#define CLKID_MALI_STACK_0 206
#define CLKID_MALI_STACK_1_SEL 207
#define CLKID_MALI_STACK_1_DIV 208
#define CLKID_MALI_STACK_1 209
#define CLKID_MALI_STACK 210
#define CLKID_DSPA_0_SEL 211
#define CLKID_DSPA_0_DIV 212
#define CLKID_DSPA_0 213
#define CLKID_DSPA_1_SEL 214
#define CLKID_DSPA_1_DIV 215
#define CLKID_DSPA_1 216
#define CLKID_DSPA 217
#define CLKID_HEVCF_0_SEL 218
#define CLKID_HEVCF_0_DIV 219
#define CLKID_HEVCF_0 220
#define CLKID_HEVCF_1_SEL 221
#define CLKID_HEVCF_1_DIV 222
#define CLKID_HEVCF_1 223
#define CLKID_HEVCF 224
#define CLKID_HCODEC_0_SEL 225
#define CLKID_HCODEC_0_DIV 226
#define CLKID_HCODEC_0 227
#define CLKID_HCODEC_1_SEL 228
#define CLKID_HCODEC_1_DIV 229
#define CLKID_HCODEC_1 230
#define CLKID_HCODEC 231
#define CLKID_VPU_0_SEL 232
#define CLKID_VPU_0_DIV 233
#define CLKID_VPU_0 234
#define CLKID_VPU_1_SEL 235
#define CLKID_VPU_1_DIV 236
#define CLKID_VPU_1 237
#define CLKID_VPU 238
#define CLKID_VAPB_0_SEL 239
#define CLKID_VAPB_0_DIV 240
#define CLKID_VAPB_0 241
#define CLKID_VAPB_1_SEL 242
#define CLKID_VAPB_1_DIV 243
#define CLKID_VAPB_1 244
#define CLKID_VAPB 245
#define CLKID_GE2D 246
#define CLKID_VPU_CLKB_TMP_SEL 247
#define CLKID_VPU_CLKB_TMP_DIV 248
#define CLKID_VPU_CLKB_TMP 249
#define CLKID_VPU_CLKB_DIV 250
#define CLKID_VPU_CLKB 251
#define CLKID_HDMITX_SYS_SEL 252
#define CLKID_HDMITX_SYS_DIV 253
#define CLKID_HDMITX_SYS 254
#define CLKID_HDMITX_PRIF_SEL 255
#define CLKID_HDMITX_PRIF_DIV 256
#define CLKID_HDMITX_PRIF 257
#define CLKID_HDMITX_200M_SEL 258
#define CLKID_HDMITX_200M_DIV 259
#define CLKID_HDMITX_200M 260
#define CLKID_HDMITX_AUD_SEL 261
#define CLKID_HDMITX_AUD_DIV 262
#define CLKID_HDMITX_AUD 263
#define CLKID_HDMIRX_5M_SEL 264
#define CLKID_HDMIRX_5M_DIV 265
#define CLKID_HDMIRX_5M 266
#define CLKID_HDMIRX_2M_SEL 267
#define CLKID_HDMIRX_2M_DIV 268
#define CLKID_HDMIRX_2M 269
#define CLKID_HDMIRX_CFG_SEL 270
#define CLKID_HDMIRX_CFG_DIV 271
#define CLKID_HDMIRX_CFG 272
#define CLKID_HDMIRX_HDCP2X_SEL 273
#define CLKID_HDMIRX_HDCP2X_DIV 274
#define CLKID_HDMIRX_HDCP2X 275
#define CLKID_HDMIRX_ACR_REF_SEL 276
#define CLKID_HDMIRX_ACR_REF_DIV 277
#define CLKID_HDMIRX_ACR_REF 278
#define CLKID_HDMIRX_METER_SEL 279
#define CLKID_HDMIRX_METER_DIV 280
#define CLKID_HDMIRX_METER 281
#define CLKID_VID_LOCK_SEL 282
#define CLKID_VID_LOCK_DIV 283
#define CLKID_VID_LOCK 284
#define CLKID_VDIN_MEAS_SEL 285
#define CLKID_VDIN_MEAS_DIV 286
#define CLKID_VDIN_MEAS 287
#define CLKID_VID_PLL_DIV 288
#define CLKID_VID_PLL_SEL 289
#define CLKID_VID_PLL 290
#define CLKID_VID_PLL_VCLK 291
#define CLKID_VCLK0_SEL 292
#define CLKID_VCLK0_IN 293
#define CLKID_VCLK0_DIV 294
#define CLKID_VCLK0 295
#define CLKID_VCLK0_DIV1_EN 296
#define CLKID_VCLK0_DIV2_EN 297
#define CLKID_VCLK0_DIV2 298
#define CLKID_VCLK0_DIV4_EN 299
#define CLKID_VCLK0_DIV4 300
#define CLKID_VCLK0_DIV6_EN 301
#define CLKID_VCLK0_DIV6 302
#define CLKID_VCLK0_DIV12_EN 303
#define CLKID_VCLK0_DIV12 304
#define CLKID_VCLK1_SEL 305
#define CLKID_VCLK1_IN 306
#define CLKID_VCLK1_DIV 307
#define CLKID_VCLK1 308
#define CLKID_VCLK1_DIV1_EN 309
#define CLKID_VCLK1_DIV2_EN 310
#define CLKID_VCLK1_DIV2 311
#define CLKID_VCLK1_DIV4_EN 312
#define CLKID_VCLK1_DIV4 313
#define CLKID_VCLK1_DIV6_EN 314
#define CLKID_VCLK1_DIV6 315
#define CLKID_VCLK1_DIV12_EN 316
#define CLKID_VCLK1_DIV12 317
#define CLKID_VDAC_SEL 318
#define CLKID_VDAC 319
#define CLKID_ENCODER0_SEL 320
#define CLKID_ENCODER0 321
#define CLKID_ENCODER1_SEL 322
#define CLKID_ENCODER1 323
#define CLKID_HDMITX0_PIXEL_SEL 324
#define CLKID_HDMITX0_PIXEL 325
#define CLKID_HDMITX0_FE_SEL 326
#define CLKID_HDMITX0_FE 327
#define CLKID_HDMITX1_PIXEL_SEL 328
#define CLKID_HDMITX1_PIXEL 329
#define CLKID_HDMITX1_FE_SEL 330
#define CLKID_HDMITX1_FE 331
#define CLKID_CSI_PHY_SEL 332
#define CLKID_CSI_PHY_DIV 333
#define CLKID_CSI_PHY 334
#define CLKID_DSI0_MEAS_SEL 335
#define CLKID_DSI0_MEAS_DIV 336
#define CLKID_DSI0_MEAS 337
#define CLKID_DSI1_MEAS_SEL 338
#define CLKID_DSI1_MEAS_DIV 339
#define CLKID_DSI1_MEAS 340
#endif /* __AMLOGIC_A9_PERIPHERALS_CLKC_H */

119
include/dt-bindings/clock/mobileye,eyeq7h-clk.h Normal file
View File

@ -0,0 +1,119 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2025 Mobileye Vision Technologies Ltd.
*/
#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
/* ACC0 and ACC1 OLBs PLL and dividers */
#define EQ7HC_ACC_PLL_VMP 0
#define EQ7HC_ACC_PLL_MPC 1
#define EQ7HC_ACC_PLL_PMA 2
#define EQ7HC_ACC_PLL_NOC 3
#define EQ7HC_ACC_DIV_PMA 4
#define EQ7HC_ACC_DIV_NCORE 5
#define EQ7HC_ACC_DIV_CFG 6
/* DDR0 and DDR1 OLBs PLL and dividers */
#define EQ7HC_DDR_PLL 0
#define EQ7HC_DDR_DIV_APB 1
#define EQ7HC_DDR_DIV_PLLREF 2
#define EQ7HC_DDR_DIV_DFI 3
/* east OLB PLL and dividers */
#define EQ7HC_EAST_PLL_106P6 0
#define EQ7HC_EAST_DIV_REF_106P6 1
#define EQ7HC_EAST_PLL_NOC 2
#define EQ7HC_EAST_PLL_ISP 3
#define EQ7HC_EAST_PLL_VEU 4
#define EQ7HC_EAST_DIV_REF_DDR_PHY 5
#define EQ7HC_EAST_DIV_CORE 6
#define EQ7HC_EAST_DIV_CORE_MBIST 7
#define EQ7HC_EAST_DIV_ISRAM_MBIST 8
#define EQ7HC_EAST_DIV_CFG 9
#define EQ7HC_EAST_DIV_VEU_CORE 10
#define EQ7HC_EAST_DIV_VEU_MBIST 11
#define EQ7HC_EAST_DIV_VEU_OCP 12
#define EQ7HC_EAST_DIV_LBITS 13
#define EQ7HC_EAST_DIV_ISP0_CORE 14
/* MIPS0, MIPS1 and MIPS2 OLBs PLL and dividers */
#define EQ7HC_MIPS_PLL_CPU 0
#define EQ7HC_MIPS_DIV_CM 1
/* periph east OLB PLL and dividers */
#define EQ7HC_PERIPH_EAST_PLL_PER 0
#define EQ7HC_PERIPH_EAST_DIV_PER 1
/* periph west OLB PLL and dividers */
#define EQ7HC_PERIPH_WEST_PLL_PER 0
#define EQ7HC_PERIPH_WEST_PLL_I2S 1
#define EQ7HC_PERIPH_WEST_DIV_PER 2
#define EQ7HC_PERIPH_WEST_DIV_I2S 3
/* south OLB PLL and dividers */
#define EQ7HC_SOUTH_PLL_100P0 0
#define EQ7HC_SOUTH_DIV_REF_100P0 1
#define EQ7HC_SOUTH_PLL_XSPI 2
#define EQ7HC_SOUTH_PLL_VDIO 3
#define EQ7HC_SOUTH_PLL_PER 4
#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS 5
#define EQ7HC_SOUTH_DIV_PMA_CMN_REF 6
#define EQ7HC_SOUTH_DIV_REF_UFS 7
#define EQ7HC_SOUTH_DIV_XSPI_SYS 8
#define EQ7HC_SOUTH_DIV_XSPI_MBIST 9
#define EQ7HC_SOUTH_DIV_NOC_S 10
#define EQ7HC_SOUTH_DIV_PCIE_SYS 11
#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBIST 12
#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY 13
#define EQ7HC_SOUTH_DIV_UFS_CORE 14
#define EQ7HC_SOUTH_DIV_UFS_SMS 15
#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS 16
#define EQ7HC_SOUTH_DIV_ETH_SYS 17
#define EQ7HC_SOUTH_DIV_ETH_MBIST 18
#define EQ7HC_SOUTH_DIV_CFG_S 19
#define EQ7HC_SOUTH_DIV_TSU 20
#define EQ7HC_SOUTH_DIV_VDIO 21
#define EQ7HC_SOUTH_DIV_VDIO_CORE 22
#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIST 23
#define EQ7HC_SOUTH_DIV_VDO_CORE_MBIST 24
#define EQ7HC_SOUTH_DIV_VDO_P 25
#define EQ7HC_SOUTH_DIV_VDIO_CFG 26
#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC 27
/* west OLB PLL and dividers */
#define EQ7HC_WEST_PLL_106P6 0
#define EQ7HC_WEST_DIV_REF_106P6 1
#define EQ7HC_WEST_PLL_NOC 2
#define EQ7HC_WEST_PLL_GPU 3
#define EQ7HC_WEST_PLL_SSI 4
#define EQ7HC_WEST_DIV_GPU 5
#define EQ7HC_WEST_DIV_GPU_MBIST 6
#define EQ7HC_WEST_DIV_LBITS 7
#define EQ7HC_WEST_DIV_MIPS_TIMER 8
#define EQ7HC_WEST_DIV_SSI_CORE 9
#define EQ7HC_WEST_DIV_SSI_CORE_MBIST 10
#define EQ7HC_WEST_DIV_SSI_ROM 11
#define EQ7HC_WEST_DIV_SSI_ROM_MBIST 12
#define EQ7HC_WEST_DIV_REF_DDR_PHY 13
#define EQ7HC_WEST_DIV_CORE 14
#define EQ7HC_WEST_DIV_CORE_MBIST 15
#define EQ7HC_WEST_DIV_CFG 16
#define EQ7HC_WEST_DIV_CAU 17
#define EQ7HC_WEST_DIV_CAU_MBIST 18
/* XNN0 and XNN1 OLBs PLL and dividers */
#define EQ7HC_XNN_PLL_XNN0 0
#define EQ7HC_XNN_PLL_XNN1 1
#define EQ7HC_XNN_PLL_XNN2 2
#define EQ7HC_XNN_PLL_CLSTR 3
#define EQ7HC_XNN_DIV_XNN0 4
#define EQ7HC_XNN_DIV_XNN1 5
#define EQ7HC_XNN_DIV_XNN2 6
#define EQ7HC_XNN_DIV_CLSTR 7
#define EQ7HC_XNN_DIV_I2 8
#define EQ7HC_XNN_DIV_I2_SMS 9
#define EQ7HC_XNN_DIV_CFG 10
#endif

4
include/dt-bindings/clock/spacemit,k3-clocks.h
View File

@ -145,6 +145,9 @@
#define CLK_MPMU_I2S3_SYSCLK 48
#define CLK_MPMU_I2S4_SYSCLK 49
#define CLK_MPMU_I2S5_SYSCLK 50
#define CLK_MPMU_I2S_SYSCLK 51
#define CLK_MPMU_I2S_BCLK_FACTOR 52
#define CLK_MPMU_I2S1_SYSCLK_SRC 53
/* APBC clocks */
#define CLK_APBC_UART0 0
@ -385,6 +388,7 @@
#define CLK_APMU_PCIE_PORTC_DBI 91
#define CLK_APMU_PCIE_PORTD_DBI 92
#define CLK_APMU_PCIE_PORTE_DBI 93
#define CLK_APMU_UFS_REFCLK 94
/* DCIU clocks */
#define CLK_DCIU_HDMA 0

56
include/linux/clk-provider.h
View File

@ -1152,13 +1152,16 @@ struct clk_fixed_factor {
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
extern const struct clk_ops clk_fixed_factor_ops;
struct clk_hw *
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
const char *name, const char *parent_name,
const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
unsigned long flags, unsigned int mult, unsigned int div,
unsigned long acc, unsigned int fixflags, bool devm);
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
void clk_unregister_fixed_factor(struct clk *clk);
struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div);
@ -1170,9 +1173,6 @@ struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
const char *name, unsigned int index, unsigned long flags,
unsigned int mult, unsigned int div);
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
struct device_node *np, const char *name, const char *fw_name,
unsigned long flags, unsigned int mult, unsigned int div);
@ -1184,13 +1184,45 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
const char *name, unsigned int index, unsigned long flags,
unsigned int mult, unsigned int div);
struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
const char *name, const struct clk_hw *parent_hw,
unsigned long flags, unsigned int mult, unsigned int div);
#define clk_hw_register_fixed_factor(dev, name, parent_name, \
flags, mult, div) \
__clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
NULL, NULL, (flags), (mult), (div), \
0, 0, false)
#define clk_hw_register_fixed_factor_pdata(dev, np, name, pdata, \
flags, mult, div, acc, fixflags) \
__clk_hw_register_fixed_factor((dev), (np), (name), NULL, NULL, \
(pdata), (flags), (mult), (div), \
(acc), (fixflags), false)
#define devm_clk_hw_register_fixed_factor(dev, name, parent_name, flags, \
mult, div) \
__clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
NULL, NULL, (flags), (mult), (div), 0, \
0, true)
/**
* devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
* pointer to parent clock
* @dev: device that is registering this clock
* @name: name of this clock
* @parent_hw: pointer to parent clk
* @flags: fixed factor flags
* @mult: multiplier
* @div: divider
*
* Return: Pointer to fixed factor clk_hw structure that was registered or
* an error pointer.
*/
#define devm_clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, \
flags, mult, div) \
__clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
(parent_hw), NULL, (flags), (mult), \
(div), 0, 0, true)
struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
const char *name, const struct clk_hw *parent_hw,
unsigned long flags, unsigned int mult, unsigned int div);
#define clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, flags, \
mult, div) \
__clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
(parent_hw), NULL, (flags), (mult), \
(div), 0, 0, false)
/**
* struct clk_fractional_divider - adjustable fractional divider clock
*

3
include/soc/spacemit/k3-syscon.h
View File

@ -45,7 +45,8 @@
#define POSR_PLL7_LOCK BIT(30)
#define POSR_PLL8_LOCK BIT(31)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_ISCCR0 0x0040
#define MPMU_ISCCR1 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024