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clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model

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Update the QCM2290 DISPCC driver to use the qcom_cc_probe() model by moving
the critical clocks handling and PLL configurations from probe to the
driver_data to align with the latest convention.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-3-62703e05ef0f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Imran Shaik 2026-07-18 18:26:10 +05:30 committed by Bjorn Andersson
parent b4ae34a7e6
commit b8b5b26aa1
1 changed files with 19 additions and 19 deletions
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38
drivers/clk/qcom/dispcc-qcm2290.c
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@ -2,6 +2,7 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
@ -49,6 +50,7 @@ static const struct alpha_pll_config disp_cc_pll0_config = {
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.config = &disp_cc_pll0_config,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@ -483,6 +485,14 @@ static struct clk_regmap *disp_cc_qcm2290_clocks[] = {
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
};
static struct clk_alpha_pll *disp_cc_qcm2290_plls[] = {
&disp_cc_pll0,
};
static const u32 disp_cc_qcm2290_critical_cbcrs[] = {
0x604c, /* DISP_CC_XO_CLK */
};
static const struct regmap_config disp_cc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -491,6 +501,13 @@ static const struct regmap_config disp_cc_qcm2290_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_driver_data disp_cc_qcm2290_driver_data = {
.alpha_plls = disp_cc_qcm2290_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_qcm2290_plls),
.clk_cbcrs = disp_cc_qcm2290_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(disp_cc_qcm2290_critical_cbcrs),
};
static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.config = &disp_cc_qcm2290_regmap_config,
.clks = disp_cc_qcm2290_clocks,
@ -499,6 +516,7 @@ static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
.resets = disp_cc_qcm2290_resets,
.num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets),
.driver_data = &disp_cc_qcm2290_driver_data,
};
static const struct of_device_id disp_cc_qcm2290_match_table[] = {
@ -509,25 +527,7 @@ MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table);
static int disp_cc_qcm2290_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
}
return ret;
return qcom_cc_probe(pdev, &disp_cc_qcm2290_desc);
}
static struct platform_driver disp_cc_qcm2290_driver = {