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clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model

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Update the QCM2290 GPUCC driver to use the qcom_cc_probe() model by moving
the critical clocks handling and PLL configurations from probe to the
driver_data to align with the latest convention.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-9-62703e05ef0f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Imran Shaik 2026-07-18 18:26:16 +05:30 committed by Bjorn Andersson
parent 1b2e1f5a37
commit 1b4599bc20
1 changed files with 20 additions and 30 deletions
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50
drivers/clk/qcom/gpucc-qcm2290.c
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@ -2,13 +2,13 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2024, Linaro Limited
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
@ -20,6 +20,7 @@
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
@ -56,6 +57,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = {
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.config = &gpu_cc_pll0_config,
.vco_table = huayra_vco,
.num_vco = ARRAY_SIZE(huayra_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
@ -347,6 +349,14 @@ static struct gdsc *gpu_cc_qcm2290_gdscs[] = {
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] = {
&gpu_cc_pll0,
};
static const u32 gpu_cc_qcm2290_critical_cbcrs[] = {
0x1060, /* GPU_CC_GX_CXO_CLK */
};
static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -355,6 +365,12 @@ static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data = {
.alpha_plls = gpu_cc_qcm2290_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_qcm2290_plls),
.clk_cbcrs = gpu_cc_qcm2290_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs),
};
static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
.config = &gpu_cc_qcm2290_regmap_config,
@ -364,6 +380,8 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
.num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
.gdscs = gpu_cc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
.use_rpm = true,
.driver_data = &gpu_cc_qcm2290_driver_data,
};
static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
@ -374,35 +392,7 @@ MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
}
out_pm_runtime_put:
pm_runtime_put_sync(&pdev->dev);
return 0;
return qcom_cc_probe(pdev, &gpu_cc_qcm2290_desc);
}
static struct platform_driver gpu_cc_qcm2290_driver = {