According to brcm,bcm4329-fmac.yaml, "brcm,bcm43455-fmac" needs the
"brcm,bcm4329-fmac" fallback.
Change it accordingly to fix the following dt-schema warning:
['brcm,bcm43455-fmac'] is too short
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://patch.msgid.link/20260721133421.44258-1-festevam@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Marvell WLAN host wake interrupt is wired to GPIO0 8 and is not
one of the PCI INTx interrupts. The PCI device schema therefore
interprets the two-cell GPIO interrupt specifier as an invalid PCI
interrupt and reports dtbs_check warnings:
pcie@0,0: wifi@0,0:interrupts:0:0: 8 is not one of [1, 2, 3, 4]
pcie@0,0: wifi@0,0:interrupts:0: [8, 8] is too long
Describe the sideband interrupt with interrupts-extended, which
explicitly carries the interrupt controller and removes the ambiguity.
Fixes: 48f4d9796d ("arm64: dts: rockchip: add Gru/Kevin DTS")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Link: https://patch.msgid.link/20260721133445.44283-1-festevam@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add device tree for the Vicharak Vaaman2, a single-board computer
based on the Rockchip RK3588 SoC.
The board features:
- RK3588 SoC with 4x Cortex-A76 (big) + 4x Cortex-A55 (little)
- eMMC storage via SDHCI (HS400)
- microSD card via SDMMC
- RK806 PMIC on SPI2 providing all required power domains
- Two RK8602/RK8603 CPU regulators on I2C0 (big clusters)
- RK8602 NPU regulator on I2C1
- HYM8563 RTC on I2C0
- Status LED on GPIO2_C5 (active-low, heartbeat trigger)
- UART2 as serial console at 1500000 baud
- SARADC with 1.8V reference
Signed-off-by: Hrushiraj Gandhi <hrushirajg23@gmail.com>
Link: https://patch.msgid.link/20260714054653.266842-3-hrushirajg23@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add device tree binding documentation for the Vicharak Vaaman2,
a single-board computer based on the Rockchip RK3588 SoC.
Signed-off-by: Hrushiraj Gandhi <hrushirajg23@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260714054653.266842-2-hrushirajg23@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the device tree binding for the Vicharak Axon single-board
computer based on the Rockchip RK3588 SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Hrushiraj Gandhi <hrushirajg23@gmail.com>
Link: https://patch.msgid.link/20260608060940.52549-2-hrushirajg23@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the device tree for LCKFB Taishan Pi 3M, a board based on the
Rockchip RK3576 SoC.
The board schematics are available at:
https://oshwhub.com/li-chuang-kai-fa-ban/project_gzzvrwqn
Describe the RK806 supplies, eMMC, recovery key, RTC, SD card,
Gigabit Ethernet, USB Type-A hosts, source-only USB Type-C host,
mSATA, HDMI video and audio, AP6256 Wi-Fi and Bluetooth, status LED,
thermal sensors, and debug UART.
The MAE0621A PHY CLKOUT supplies the GMAC reference-clock input, so
request its validated 125 MHz setting.
The following interfaces were tested on the hardware: eMMC, RTC
register access, recovery key, SD card, 1GbE, USB 2.0 Type-A storage,
USB 3.0 Type-A 5 Gbit/s enumeration and 64 MiB storage I/O, USB-C
source/host enumeration in both orientations, mSATA, HDMI video and
audio, AP6256 2.4/5 GHz Wi-Fi scan, WPA2 association, ping and
bidirectional throughput, Bluetooth firmware load and HCI bring-up,
and UART0. Bluetooth active discovery was additionally exercised
during bring-up.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Link: https://patch.msgid.link/MN0PR19MB6091D3101FD2D8F940F0CE4DACF92@MN0PR19MB6091.namprd19.prod.outlook.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add device tree for the Xunlong Orange Pi 5 Pro (RK3588S).
- eMMC module, you can optionally solder a SPI NOR in place and turn
off the eMMC
- PCIe-attached NIC (pcie2x1l2)
- PCIe NVMe slot (pcie2x1l1)
- AP6256 WiFi (BCM43456) via SDIO with mmc-pwrseq
- BCM4345C5 Bluetooth
- es8388 audio
- USB 2.0 and USB 3.0
- HDMI output is enabled
- the second HDMI port connected to the DP bridge is left out for a
followup set
Vendors schematics are available at:
https://drive.google.com/file/d/1qs1DratHuh7C6J6MEtQIwUsiSrg8qgTi/view
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260511025352.106126-5-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Orange Pi 5 Pro uses the same SoC and base as the Orange Pi 5 and
Orange Pi 5B but has had sound, USB, and leds wired up differently. The
5 and 5B boards use gmac for ethernet where the Pro has a PCIe attached
NIC.
Move the 5/5B-specific bits (analog-sound/es8388, FUSB302 Type-C,
gmac1, pwm-leds, i2s1_8ch routing, USB role-switch plumbing) out of
rk3588s-orangepi-5.dtsi into a new rk3588s-orangepi-5-5b.dtsi that is
included by both 5 and 5B.
The RK806 PLDO1 and PLDO2 outputs are wired differently between the
5/5B and the Pro (PLDO1/PLDO2 are swapped), so label the PMIC node
rk806 in the base dtsi, drop pldo-reg1/pldo-reg2 from it, and define
them via a &rk806 regulators augmentation in rk3588s-orangepi-5-5b.dtsi.
The Pro will supply its own mapping.
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260511025352.106126-4-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Orange Pi 5, 5B and 5 Pro schematics label the RK806 PLDO outputs
using the pattern VCC_*_S0 / VCCA_*_S0 / VDDA_*_S0. Rename the base
dtsi regulator labels (and the es8388 supply references) to match:
pldo-reg1: avcc_1v8_s0 -> vcc_1v8_s0
pldo-reg2: vcc_1v8_s0 -> vcca_1v8_s0
pldo-reg3: avdd_1v2_s0 -> vdda_1v2_s0
pldo-reg4: vcc_3v3_s0 -> vcca_3v3_s0
Also update the saradc vref-supply reference to track the pldo-reg1
rename. No functional change.
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Link: https://patch.msgid.link/20260511025352.106126-3-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add compatible string for the Orange Pi 5 Pro.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Link: https://patch.msgid.link/20260511025352.106126-2-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This reverts commit 096bd8c679.
Just as with the Pinebook Pro, there are multiple chipset variants for
the Pinephone Pro, and multiple firmware binaries for different
distributions. The change causes issues with some of these combinations,
and reverting it resolves the issues. See the Closes below for the full
report.
Similarly with the Pinebook Pro adjustment, the original commit only
indicates "further description" and not indicative of fixing any
existing issues, so reverting should not kick any back up.
Fixes: 096bd8c679 ("arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro")
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Thorsten Leemhuis <regressions@leemhuis.info>
Cc: stable@vger.kernel.org
Closes: https://lore.kernel.org/r/20260607225901.64019-1-oklopfer37@gmail.com/
Signed-off-by: Oren Klopfer <oklopfer37@gmail.com>
Link: https://patch.msgid.link/20260703201010.67311-1-oklopfer37@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The YY3588 declares the HDMI-RX signal detect on GPIO1_C6, but the
receiver never sees an attached source there and cannot capture any
input.
That value was copied from the vendor device tree and is wrong. The
core-board schematics are not available and the SoM documentation does
not clearly show where this signal is routed, so the correct pin was
read from the device tree in the board's Android image: GPIO1_D5. With
GPIO1_D5 the receiver detects a connected source and locks, and v4l2
reports the input timing (1920x1080p60).
Fixes: 19847bde695f ("arm64: dts: rockchip: Add Youyeetoo YY3588")
Signed-off-by: Daniele Briguglio <hello@superkali.me>
Link: https://patch.msgid.link/20260709-yy3588-hdmirx-d5-fix-v1-1-900a6790386c@superkali.me
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The USB3 OTG controller on the ROC-PC can be used in device mode,
but the board description only enabled the DWC3 controller and USB2 PHY.
The USBDP PHY remained disabled and the controller had no role-switch
default, so DWC3 did not register a UDC and USB gadget drivers such
as g_mass_storage failed to bind.
Enable the USBDP PHY and describe the controller as a USB role switch
with peripheral as the default role. This lets the controller register
as a UDC when no external role provider has selected a host role.
Tested on a Firefly Station M3 by binding g_mass_storage to expose the
eMMC as a USB mass-storage gadget.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Link: https://patch.msgid.link/20260709005006.413145-1-festevam@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3588s-roc-pc ES8388 codec is connected to the i2s0_8ch audio
interface. Use the matching I2S0 MCLK output for the codec clock
instead of I2S1.
Using the I2S1 MCLK can leave the ALSA PCM running while the codec has
no usable master clock for the active audio path, resulting in silent
headphone output.
Also make the CPU DAI provide bitclock and frame clock. This matches
the active Rockchip I2S controller side and avoids relying on the codec
to drive the bus clocks.
Route the headphone output to LOUT2 and ROUT2, matching the old 5.10
BSP device tree. LOUT1 and ROUT1 are used for the speaker route there,
so using them for the headphone widget can leave the headphone jack
silent even while the ALSA path is active.
The old BSP also used hp-con-gpio on GPIO1_A4. Model that GPIO as a
simple audio amplifier so DAPM enables the headphone connection when the
headphone path is active.
Cc: stable@vger.kernel.org
Fixes: 7f95097915 ("arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC")
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Link: https://patch.msgid.link/20260703025648.180135-1-festevam@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The recently changes for 9Tripod X3568 mistakenly configured
the WiFi host-wake interrupt trigger type as IRQ_TYPE_LEVEL_LOW.
However, the associated pin `wifi_host_wake_irq` is configured
with an internal pull-down resistor.
When the WiFi module enters a low-power sleep state and leaves
the pin floating, this pull-down bias drives the pin low.
Since the interrupt is incorrectly set to level-low, this combination
traps the kernel in an endless interrupt loop.
Correct the interrupt trigger type to IRQ_TYPE_LEVEL_HIGH based on the
actual hardware logic: the pin is kept low by default and driven high by
the WiFi module to wake up the host.
Fixes: 993555b547 ("arm64: dts: rockchip: Add AP6275S support for 9Tripod X3568 v4")
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Link: https://patch.msgid.link/20260702202429.2341789-1-coiaprant@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The FriendlyELEC CM3588 NAS kit is often supplied with a case and a fan.
Enable control of the speed of the fan using the trip points and cooling
maps from rk3588-nanopc-t6.dtsi as a reference.
Signed-off-by: Vsevolod Kozlov <zaba@mm.st>
Link: https://patch.msgid.link/akkAvJap-MtbKp8B@Vsevolods-MacBook-Pro.local
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Describe the Haoyu HYM8563 RTC connected to I2C6 on the Radxa CM5 IO
carrier including its interrupt line.
Assisted-by: Grok:grok-build
Signed-off-by: Brian Mayer <bleemayer@gmail.com>
Link: https://patch.msgid.link/20260705181920.8633-1-bleemayer@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The HINLINK H28K (LinkStar H28K) is a SBC with the
Rockchip RK3528 SoC. It has the following features:
- 1x USB 2.0
- 8/32GB eMMC
- 1/2/4GB LPDDR4
- MicroSD card slot
- 1x 1GbE RTL8111H Ethernet
- 1x 1GbE RTL8211F Ethernet
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://patch.msgid.link/20260610100006.366963-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add full device tree definition for the integrated eDP controller
on RK3576, following the existing RK3588 hardware layout.
Configure required register range, clocks, interrupt, phy, power
domain, reset and grf properties to fully describe the controller.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://patch.msgid.link/20260605022305.3058853-4-damon.ding@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the required HCLK_VO1 bus clock to RK3588 eDP1 node with
corresponding clock-name "hclk". This clock is necessary for
the eDP controller to access video output GRF and work properly.
Previously the clock was enabled implicitly via GRF phandle
reference. Add it explicitly now to align with updated binding.
Fixes: a481bb0b1a ("arm64: dts: rockchip: Add eDP1 dt node for rk3588")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://patch.msgid.link/20260605022305.3058853-3-damon.ding@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the required HCLK_VO1 bus clock to RK3588 eDP0 node with
corresponding clock-name "hclk". This clock is necessary for the
eDP controller to access video output GRF and work properly.
Previously the clock was enabled implicitly via GRF phandle
reference. Add it explicitly now to align with updated binding.
Fixes: dc79d3d5e7 ("arm64: dts: rockchip: Add eDP0 node for RK3588")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://patch.msgid.link/20260605022305.3058853-2-damon.ding@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
According to the Jedec 5.1 specification, the device is held in reset
when RST_n is low, therefore the polarity of the line must be that, as
specified in the Device Tree binding (mmc/mmc-pwrseq-emmc.yaml).
Due to the wrong polarity, eMMC devices with RST_n_FUNCTION[162]
bitfield [1:0] set to 0x1 (the default is 0x0) will be held in reset
forever.
Cc: stable@vger.kernel.org
Fixes: c484cf93f6 ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://patch.msgid.link/20260626-ringneck-emmc-polarity-v1-1-90cefe57b316@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Three fixed-regulator names on the NanoPC-T6 don't match the board
schematic [1].
- vcc3v3_pcie2x1l0 -> vdd_mpcie_3v3
This GPIO-switched 3v3 regulator is labeled vcc3v3_pcie2x1l0, but
it is wired to and consumed by &pcie2x1l1. Per the schematic,
the GPIO PCIE_M2_1_PWREN controls the power net VDD_MPCIE_3.3V;
rename to match.
- vdd_2v0_pldo_s3 -> vcc_2v0_pldo_s3
Typo in the regulator-name property of RK806-1 DCDC reg7. The node
label and the schematic power-net name both already use the vcc_
form; only the regulator-name string had vdd_.
- vcc3v3_pcie30 -> vcc3v3_pcie_m2_0
The GPIO-switched 3v3 feeding the M.2 M-Key (NVMe) slot is named
after the PCIe controller it sits behind rather than the schematic
power net. The schematic names it VCC3V3_PCIE_M2_0 (produced by an
MP2143-based buck off VCC_5V0, enabled by PCIE_M2_0_PWREN); rename
to match.
No functional change.
[1] https://wiki.friendlyelec.com/wiki/images/9/97/NanoPC-T6_2301_SCH.PDF
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
Link: https://patch.msgid.link/20260605-rk3588-dts-rockchip-nanopct6-fix-schematic-names-v1-1-15dd3b23ab1a@pardini.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The YY3588 is a single board computer built around the Rockchip RK3588.
Specification:
- Rockchip RK3588 SoC
- 4/8/16/32 GB LPDDR4/4x
- up to 256 GB eMMC
- microSD card slot
- 1x 1000Base-T (Realtek RTL8211F) and 1x 2500Base-T (Realtek RTL8125)
- HDMI 2.1 output
- HDMI input
- 4x USB 3.0 Type-A via onboard hub, 1x USB 2.0 Type-A
- USB Type-C with USB 3.0
- M.2 M-key with PCIe 3.0 x4
- Mini PCIe slot for WiFi/BT or 4G modules
- SATA 3.0
- ES8388 audio codec with headphone jack and onboard microphone
- fan connector, RTC, recovery key
- 12 V DC input
Both Ethernet ports, eMMC, SD card, USB, Type-C, HDMI output, WiFi
on the Mini PCIe slot, audio, the recovery key and the fan have been
tested on the board.
Link: https://wiki.youyeetoo.com/YY3588
Signed-off-by: Daniele Briguglio <hello@superkali.me>
Link: https://patch.msgid.link/20260610-yy3588-board-v1-3-4bb7176b6826@superkali.me
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Canaan:
Support for the k230 SoC that was too late for the 7.2 window.
Consists of some bindings not taken by the various subsystem
maintainers, the original dts patches from Yangyu back in 2024
and the more recent clock, reset and pinctrl additions from various
contributors.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V devicetrees for v7.3 - early k230 material
Canaan:
Support for the k230 SoC that was too late for the 7.2 window.
Consists of some bindings not taken by the various subsystem
maintainers, the original dts patches from Yangyu back in 2024
and the more recent clock, reset and pinctrl additions from various
contributors.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: canaan: Add clock definition for K230
riscv: dts: canaan: add reset controller for K230
riscv: dts: canaan: k230: Add "b" ISA extension
riscv: dts: canaan: Add k230's pinctrl node
riscv: dts: canaan: Correct the formatting issues about k230 dts
riscv: dts: add initial canmv-k230 and k230-evb dts
dt-bindings: interrupt-controller: Add Canaan K230 PLIC
dt-bindings: timer: Add Canaan K230 CLINT
dt-bindings: add Canaan K230 boards compatible strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The reg-offset hack only works when the IXP4xx platform is
running in big endian mode, and it is there to byte-offset
the byte where the serial registers appear in the BE config.
This is clearly wrong, workarounds need to be in the
drivers. Drop the reg-offset.
Signed-off-by: Linus Walleij <linusw@kernel.org>
Link: https://lore.kernel.org/r/20260724-ixp4xx-dts-fix-v1-1-09bf7111e94e@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the
I2C0/1/3 busses. The I2C1 one is already added to the device tree, but
the I2C0/3 ones are not yet added.
Add device tree nodes for them.
Link: https://lore.kernel.org/r/20260714074515.1959352-6-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[Icenowy: added commit description, enable SoC pull-up, remove I2C1 and
aliases]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Add labels for GPIOs on the IO expansion chip on the I2C1 bus.
Link: https://lore.kernel.org/r/20260714074515.1959352-5-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[Icenowy: Splitted off the patch adding all 3 IO expansions]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
[fustini: align ioexp2 gpio-line-names with schematic]
Signed-off-by: Drew Fustini <fustini@kernel.org>
Although "D", "H" and "I" are earlier in the alphabet than "P", the DPU,
HDMI and I2C1 nodes were added after PADCTRL nodes in the Lichee Pi 4A
device tree; in addition the PADCTRL1 node is placed before the
PADCTRL0 one.
Sort the nodes in this device tree.
Link: https://lore.kernel.org/r/20260714074515.1959352-4-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Add nodes for the remaining five I2C controllers on the T-Head TH1520
RISCV SoC.
Link: https://lore.kernel.org/r/20260714074515.1959352-3-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
[Icenowy: rebase and reword commit message to exclude I2C1]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
The I2C1 node added previously to the th1520.dtsi file has two clocks
set -- one "ref" clock (CLK_I2C1) and one "pclk" (CLK_PERI_APB_PCLK).
However, the CLK_I2C1 clock is just a clock gate with the
CLK_PERI_APB_PCLK clock as its input. In addition, when it's gated,
reading registers from the I2C controller returns fixed value (the last
read value) for all registers. These facts indicate that the CLK_I2C1
clock is the true APB clock fed into the I2C controller instead of a
dedicated reference clock.
Leave only the CLK_I2C1 clock as the `clocks` property of the I2C1
device node and remove `clock-names` property, which represents the I2C
controller only takes a single clock both as the APB clock and the
reference clock.
Fixes: 2f60e35163 ("riscv: dts: thead: Add TH1520 I2C1 controller")
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Link: https://lore.kernel.org/r/20260714074515.1959352-2-zhengxingda@iscas.ac.cn
Signed-off-by: Drew Fustini <fustini@kernel.org>
The Banana Pi BPI-CM6 IO board combines the BPI-CM6 compute module with
an IO carrier board. The core module integrates the SpacemiT K1 SoC,
PMIC, DDR, eMMC, the eth0 PHY, and wireless connectivity. The companion
IO carrier board extends it by providing the eth1 PHY and exposing
standard interfaces, including dual Gigabit Ethernet, MicroSD, two USB-A
ports, a USB Type-C port, two PCIe M.2 slots, and a serial console.
The board also has two I2C EEPROMs. One is on the core module, which
stores factory manufacturing data and is marked read-only. The other is
on the carrier board, which is shipped unprogrammed and left writable
for evaluation purposes.
Add initial support for UART console, eMMC, SD card, I2C, EEPROMs,
PCIe, USB, and dual Ethernet interfaces.
Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6
Reviewed-by: Michael Opdenacker <michael.opdenacker@rootcommit.com>
Tested-by: Michael Opdenacker <michael.opdenacker@rootcommit.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260712-bpi-cm6-v3-3-8d1e2045179d@pigmoral.tech
Signed-off-by: Yixun Lan <dlan@kernel.org>
The gmac_clk_ref signal is optional for the GMAC controller and is not
strictly required for all hardware designs. The pins for gmac0_clk_ref
(GPIO 45) and gmac1_clk_ref (GPIO 46) may also be used as GPIOs for
other functions even when the Ethernet controller is active.
Split the refclk pins into independent pinctrl groups so boards can
request them only when the reference clock path is actually needed.
Among the already mainlined boards, BPI-F3, Jupiter and MusePi Pro have
optional hardware paths for the GMAC refclk pins. BPI-F3 and Jupiter
route both GMAC refclk pins to the PHYs through NC/0R option resistors,
while MusePi Pro only does so for GMAC0. Keep referencing the new
clk-ref pinctrl groups on these boards so the optional hardware paths
remain usable if the option resistors are populated.
OrangePi R2S has no publicly available schematic, so also keep the
clk-ref groups there to preserve the previous pinmux behavior.
Fixes: 60775f28cf ("riscv: dts: spacemit: Add Ethernet support for K1")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260712-bpi-cm6-v3-2-8d1e2045179d@pigmoral.tech
Signed-off-by: Yixun Lan <dlan@kernel.org>
The Banana Pi BPI-CM6 IO board consists of the BPI-CM6 compute module
plugged into an IO carrier board, which is used for evaluation and
development.
The core CM6 module is based on the SpacemiT K1 SoC and provides PMIC,
DDR, the eth0 PHY and wireless connectivity. The carrier board extends
this by adding the eth1 PHY and external interfaces including Ethernet,
PCIe M.2, USB, MicroSD, QSPI, and serial console connectivity.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260712-bpi-cm6-v3-1-8d1e2045179d@pigmoral.tech
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add CPU clock properties and OPP tables for the two CPU clusters in the
SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU
supply is shared by both clusters.
Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and
wiring the CPU nodes to the CPU regulator supply.
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
Tested-by: Andre Heider <a.heider@gmail.com> # k1-musepi-pro
Reviewed-by: Yixun Lan <dlan@kernel.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Tested-by: Gong Shuai <gsh517025@gmail.com> # OrangePi-RV2
Link: https://patch.msgid.link/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
Enable QSPI with proper pinmux on the Pico-ITX board, and describe the
NOR flash wired to it.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Vendor kernel enabled ALDPS (Advanced Link Down Power Saving) on the
RTL8211F PHY to save power when link down.
Vendor kernel also disabled the 125MHz clkout clock signal, and indeed
the schematics confirms that it only goes to a test point (TP14), so
let's do the same.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Yixun Lan <dlan@kernel.org>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-6-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add i2c aliases for i2c2 and i2c8 on K3 Pico-ITX board. This is useful
to keep a stable number for the /dev entries after loading the i2c-dev
module.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-5-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
The K3 Pico-ITX board includes a 24c02 eeprom, that stores the product
name, the part name, the MAC address of the network interfaces and the
board's serial number. These values are also exposed via an
onie,tlv-layout nvmem layout.
The eeprom is marked as read-only since its contents are not supposed to
be modified.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-4-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Define I2C2 pinctrl properties, and enable it on the K3 Pico-ITX board.
It will be used by the 24c02 eeprom.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-3-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Because the default console's baud rate is not set, defconfig kernels do
not have any serial output on this platform. Set the baud rate to
115200, matching what is used by U-Boot etc on this platform.
Fixes: 7a61318049 ("riscv: dts: spacemit: add K3 Pico-ITX board support")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Guodong Xu <docular.xu@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
The Performance Monitoring Unit of the Cortex-A8 cores in the Allwinner
A10 SoC is connected to interrupt line 66, not 3. This is shown in the
manual (where interrupt 3 is assigned to UART2, also in our .dtsi), but
has also been confirmed by triggering an PMU overflow interrupt and
inspecting the IRQ controller status registers (from U-Boot).
Please note that "perf stat" does not use interrupts, this might explain
why this evaded the initial testing.
Fixes: 7e345d25c7 ("ARM: dts: sun4i-a10: Add PMU node")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20260720215128.5761-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
