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riscv: dts: spacemit: Add cpu scaling for K1 SoC

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Add CPU clock properties and OPP tables for the two CPU clusters in the
SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU
supply is shared by both clusters.

Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and
wiring the CPU nodes to the CPU regulator supply.

Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
Tested-by: Andre Heider <a.heider@gmail.com> # k1-musepi-pro
Reviewed-by: Yixun Lan <dlan@kernel.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Tested-by: Gong Shuai <gsh517025@gmail.com> # OrangePi-RV2
Link: https://patch.msgid.link/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
This commit is contained in:
Shuwei Wu 2026-06-26 16:10:24 +08:00 committed by Yixun Lan
parent 736d655c84
commit 3b9c34556f
3 changed files with 147 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
View File

@ -4,6 +4,7 @@
*/
#include "k1.dtsi"
#include "k1-opp.dtsi"
#include "k1-pinctrl.dtsi"
/ {
@ -87,6 +88,38 @@ &combo_phy {
status = "okay";
};
&cpu_0 {
cpu-supply = <&buck1_0v9>;
};
&cpu_1 {
cpu-supply = <&buck1_0v9>;
};
&cpu_2 {
cpu-supply = <&buck1_0v9>;
};
&cpu_3 {
cpu-supply = <&buck1_0v9>;
};
&cpu_4 {
cpu-supply = <&buck1_0v9>;
};
&cpu_5 {
cpu-supply = <&buck1_0v9>;
};
&cpu_6 {
cpu-supply = <&buck1_0v9>;
};
&cpu_7 {
cpu-supply = <&buck1_0v9>;
};
&emmc {
bus-width = <8>;
mmc-hs400-1_8v;
@ -202,7 +235,7 @@ pmic@41 {
dldoin2-supply = <&buck5>;
regulators {
buck1 {
buck1_0v9: buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;

105
arch/riscv/boot/dts/spacemit/k1-opp.dtsi Normal file
View File

@ -0,0 +1,105 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/ {
cluster0_opp_table: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
opp-614400000 {
opp-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-819000000 {
opp-hz = /bits/ 64 <819000000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1050000 1050000 1050000>;
clock-latency-ns = <200000>;
};
};
cluster1_opp_table: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
opp-614400000 {
opp-hz = /bits/ 64 <614400000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-819000000 {
opp-hz = /bits/ 64 <819000000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-microvolt = <950000 950000 1050000>;
clock-latency-ns = <200000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1050000 1050000 1050000>;
clock-latency-ns = <200000>;
};
};
};
&cpu_0 {
operating-points-v2 = <&cluster0_opp_table>;
};
&cpu_1 {
operating-points-v2 = <&cluster0_opp_table>;
};
&cpu_2 {
operating-points-v2 = <&cluster0_opp_table>;
};
&cpu_3 {
operating-points-v2 = <&cluster0_opp_table>;
};
&cpu_4 {
operating-points-v2 = <&cluster1_opp_table>;
};
&cpu_5 {
operating-points-v2 = <&cluster1_opp_table>;
};
&cpu_6 {
operating-points-v2 = <&cluster1_opp_table>;
};
&cpu_7 {
operating-points-v2 = <&cluster1_opp_table>;
};

8
arch/riscv/boot/dts/spacemit/k1.dtsi
View File

@ -56,6 +56,7 @@ cpu_0: cpu@0 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <0>;
clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -86,6 +87,7 @@ cpu_1: cpu@1 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <1>;
clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -116,6 +118,7 @@ cpu_2: cpu@2 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <2>;
clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -146,6 +149,7 @@ cpu_3: cpu@3 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <3>;
clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -176,6 +180,7 @@ cpu_4: cpu@4 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <4>;
clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -206,6 +211,7 @@ cpu_5: cpu@5 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <5>;
clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -236,6 +242,7 @@ cpu_6: cpu@6 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <6>;
clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
@ -266,6 +273,7 @@ cpu_7: cpu@7 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <7>;
clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",