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riscv: dts: thead: Add TH1520 I2C nodes

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Add nodes for the remaining five I2C controllers on the T-Head TH1520
RISCV SoC.

Link: https://lore.kernel.org/r/20260714074515.1959352-3-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
[Icenowy: rebase and reword commit message to exclude I2C1]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
This commit is contained in:
Thomas Bonnefille 2026-07-14 15:45:12 +08:00 committed by Drew Fustini
parent 5ed8cdb56c
commit b6e4c8fe4c
1 changed files with 50 additions and 0 deletions
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50
arch/riscv/boot/dts/thead/th1520.dtsi
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@ -411,6 +411,16 @@ uart3: serial@ffe7f04000 {
status = "disabled";
};
i2c0: i2c@ffe7f20000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xe7f20000 0x0 0x4000>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_I2C0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@ffe7f24000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xe7f24000 0x0 0x4000>;
@ -421,6 +431,16 @@ i2c1: i2c@ffe7f24000 {
status = "disabled";
};
i2c4: i2c@ffe7f28000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xe7f28000 0x0 0x4000>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_I2C4>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
@ -519,6 +539,16 @@ padctrl0_apsys: pinctrl@ffec007000 {
thead,pad-group = <3>;
};
i2c2: i2c@ffec00c000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xec00c000 0x0 0x4000>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
@ -530,6 +560,16 @@ uart2: serial@ffec010000 {
status = "disabled";
};
i2c3: i2c@ffec014000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xec014000 0x0 0x4000>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_I2C3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm: pwm@ffec01c000 {
compatible = "thead,th1520-pwm";
reg = <0xff 0xec01c000 0x0 0x4000>;
@ -735,6 +775,16 @@ uart5: serial@fff7f0c000 {
status = "disabled";
};
i2c5: i2c@fff7f2c000 {
compatible = "thead,th1520-i2c", "snps,designware-i2c";
reg = <0xff 0xf7f2c000 0x0 0x4000>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_I2C5>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>;