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ARM: dts: allwinner: a10: Fix PMU interrupt

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The Performance Monitoring Unit of the Cortex-A8 cores in the Allwinner
A10 SoC is connected to interrupt line 66, not 3. This is shown in the
manual (where interrupt 3 is assigned to UART2, also in our .dtsi), but
has also been confirmed by triggering an PMU overflow interrupt and
inspecting the IRQ controller status registers (from U-Boot).
Please note that "perf stat" does not use interrupts, this might explain
why this evaded the initial testing.

Fixes: 7e345d25c7 ("ARM: dts: sun4i-a10: Add PMU node")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20260720215128.5761-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
This commit is contained in:
Andre Przywara 2026-07-20 23:51:28 +02:00 committed by Chen-Yu Tsai
parent a858dab480
commit eb7051f756
1 changed files with 1 additions and 1 deletions
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arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
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@ -185,7 +185,7 @@ de: display-engine {
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
interrupts = <66>;
};
reserved-memory {