- DT support for PRU-ICSS on AM3/4/5
- minor fixes & cleanups
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Merge tag 'omap-for-v7.3/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
ARM: dts: OMAP updates for v7.3
- DT support for PRU-ICSS on AM3/4/5
- minor fixes & cleanups
* tag 'omap-for-v7.3/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap:
ARM: dts: ti/omap: embt2ws: use mulit-led for RGB LED
ARM: dts: ti: omap: Correct indentation
ARM: dts: ti: Fix typos in comments
ARM: dts: ti: Add specific compatibles for SCM conf nodes
arm: dts: ti: Add device tree support for PRU-ICSS on AM335x
arm: dts: ti: Add device tree support for PRU-ICSS on AM437x
arm: dts: ti: Add device tree support for PRU-ICSS on AM57xx
ARM: dts: ti: var-som-om44: Add USB Ethernet controller node
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
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Merge tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into soc/dt
RISC-V SpacemiT DT changes for 7.3
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
* tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: (33 commits)
riscv: dts: spacemit: Add cpu scaling for Milk-V Jupiter
riscv: dts: spacemit: k1-bananapi-cm6: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-r2s: fix maximum CPU core voltage
riscv: dts: spacemit: k1-musepi-pro: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-rv2: fix maximum CPU core voltage
riscv: dts: spacemit: k1-milkv-jupiter: fix maximum CPU core voltage
riscv: dts: spacemit: k1-bananapi-f3: fix maximum CPU core voltage
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 com260 board
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 pico-itx board
riscv: dts: spacemit: k3: add i2s0-i2s5 nodes
riscv: dts: spacemit: k3: add USB controller and USB phy support
riscv: dts: spacemit: enable PCIe on OrangePi R2S
riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1
riscv: dts: spacemit: k3-com260: add eeprom on i2c2
riscv: dts: spacemit: add SPI controllers for K3
riscv: dts: spacemit: add K3 PDMA request numbers
riscv: dts: spacemit: Fix phy id check for the phy on com260 board
riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board
riscv: dts: spacemit: Add enough deassert time for the PHY on com260 board
riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Orange Pi 5 Pro, Vicharak Axon, Vicharak Vaaman2, Youyeetoo YY3588
New peripherals: eDP support on RK3576
And of course a number of board-fixes, style-fixes and some newly
enabled board-components.
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Merge tag 'v7.3-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: Graperain G3568, HINLINK H28K, LCKFB Taishan Pi 3M,
Orange Pi 5 Pro, Vicharak Axon, Vicharak Vaaman2, Youyeetoo YY3588
New peripherals: eDP support on RK3576
And of course a number of board-fixes, style-fixes and some newly
enabled board-components.
* tag 'v7.3-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (39 commits)
arm64: dts: rockchip: Fix rk3566-bigtreetech-cb2 touchscreen property
arm64: dts: rockchip: fix label of sys_led for nanopi-r4s
arm64: dts: rockchip: Fix the rk3566-radxa-cm3 Wifi compatible
arm64: dts: rockchip: Fix Gru WLAN sideband interrupt
arm64: dts: rockchip: Add Vicharak Vaaman2 board
dt-bindings: arm: rockchip: Add Vicharak Vaaman2
arm64: dts: rockchip: add Vicharak Axon board
dt-bindings: arm: rockchip: add Vicharak Axon board
arm64: dts: rockchip: Add LCKFB Taishan Pi 3M
dt-bindings: arm: rockchip: Add LCKFB Taishan Pi 3M
arm64: dts: rockchip: Add Orange Pi 5 Pro board support
arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro
arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5
dt-bindings: arm: rockchip: Add Orange Pi 5 Pro
arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2
dt-bindings: arm: rockchip: Add Graperain G3568 series
dt-bindings: vendor-prefixes: Add graperain
Revert "arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro"
arm64: dts: rockchip: fix HDMI-RX signal detect GPIO on yy3588
arm64: dts: rockchip: Enable USB device mode on rk3588s-roc-pc
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.
Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.
Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.
Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.
Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
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Merge tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v7.3
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.
Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.
Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.
Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.
Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
* tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (244 commits)
arm64: dts: qcom: eliza: Describe the ADSP GPR node
arm64: dts: qcom: eliza-evk: Add support for USB and SD card
dt-bindings: arm: qcom-soc: Allow WSA88xx speaker compatible
dt-bindings: arm: qcom-soc: Validate nodes with fallbacks
dt-bindings: arm: qcom-soc: Document more of existing legacy style compatibles
dt-bindings: arm: qcom-soc: Include Eliza, Kaanapali and others in SoC names
arm64: dts: qcom: eliza: Enable cpufreq cooling devices
arm64: dts: qcom: glymur: add SoCCP DT node
arm64: dts: qcom: glymur: fix SoCCP memory mappings
arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR
arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
arm64: dts: qcom: glymur: Add CX power domain to GCC
arm64: dts: qcom: glymur: Drop fake PCIe phy 3B
arm64: dts: qcom: glymur: add TRNG node
arm64: dts: qcom: glymur: enable ETR and CTCU devices
arm64: dts: qcom: glymur: Add PCIe port compatibles and ports
arm64: dts: qcom: smb2370: Disable SMB2370_2 by default
arm64: dts: qcom: eliza-mtp: Enable touchscreen
arm64: dts: qcom: purwa-iot-som: enable video
arm64: dts: qcom: purwa: Override Iris clocks and operating points
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Correct a few white-space issues, like missing space before bracket '{'
character or spurious space, which will be flagged by dt-check-style
("redundant-whitespace" warning). No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260801210450.384087-4-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Correct a few white-space issues, like double before bracket '{'
character, which will be flagged by dt-check-style
("redundant-whitespace" warning). No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260801210450.384087-3-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
This adds a couple of fixes and improvements for multiple
MediaTek SoCs.
In particular:
- Indentation/whitespace fixes for some devicetrees
- Documentation improvements for MediaTek Mute-X
- dtbs-check warnings fixes
- MT8390 Tungsten boards: removal of unnecessary cells
- MT6795 SoC: removal of deprecated property in UART DMA
- MT6359 PMIC's RTC now uses the correct compatible string
- MT8183/86/88/92/95 SoCs gain support for the UART DMA IPs
- MT8186 gets a new CCI OPP table to resolve lockups
- MT8188/83 Chromebooks now got the correct SPI NOR supply
- MT8192 Asurada drops support for the (unused) MMC1 port
- MediaTek Genio 510/700/1200 EVKs and Radxa NIO-12L now get
their PMIC power input tree completed with assignment of
the correct supplies
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Merge tag 'mtk-dts64-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates
This adds a couple of fixes and improvements for multiple
MediaTek SoCs.
In particular:
- Indentation/whitespace fixes for some devicetrees
- Documentation improvements for MediaTek Mute-X
- dtbs-check warnings fixes
- MT8390 Tungsten boards: removal of unnecessary cells
- MT6795 SoC: removal of deprecated property in UART DMA
- MT6359 PMIC's RTC now uses the correct compatible string
- MT8183/86/88/92/95 SoCs gain support for the UART DMA IPs
- MT8186 gets a new CCI OPP table to resolve lockups
- MT8188/83 Chromebooks now got the correct SPI NOR supply
- MT8192 Asurada drops support for the (unused) MMC1 port
- MediaTek Genio 510/700/1200 EVKs and Radxa NIO-12L now get
their PMIC power input tree completed with assignment of
the correct supplies
* tag 'mtk-dts64-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: dts: mediatek: mt6359: use proper compatible for rtc
arm64: dts: mediatek: mt8395-radxa-nio-12l: Add MT6365 PMIC supplies
arm64: dts: mediatek: mt8395-genio-common: Add MT6365 PMIC supplies
arm64: dts: mediatek: mt8390-genio-common: Add MT6365 PMIC supplies
arm64: dts: mediatek: mt8192-asurada: Disable mmc1 on Spherion
dt-bindings: soc: mediatek: mutex: Improve title and description
arm64: dts: mediatek: mt8195: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8188: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8183: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt6795: Remove deprecated UART DMA property
arm64: dts: mediatek: tungsten-smarc: Remove unnecessary cells
arm64: dts: mediatek: Correct indentation and whitespace
arm64: dts: mediatek: mt8188-geralt: Add supply for SPI NOR flash
arm64: dts: mediatek: mt8183-kukui: Add supply for SPI NOR flash
arm64: dts: mediatek: mt8186: change CCI OPP scaling mapping
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This fixes a minor indentation issue in the MT8127 devicetree
and adds support for the Auxiliary ADC found in the MT6323 PMIC.
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Merge tag 'mtk-dts32-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM32 DeviceTree updates
This fixes a minor indentation issue in the MT8127 devicetree
and adds support for the Auxiliary ADC found in the MT6323 PMIC.
* tag 'mtk-dts32-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
ARM: dts: mediatek: mt6323: add AUXADC support
ARM: dts: mediatek: mt8127: Correct indentation
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable CPU DVFS on Milk-V Jupiter by including the OPP tables and wiring the
CPU nodes to the CPU regulator supply.
Reviewed-by: Yixun Lan <dlan@kernel.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Link: https://patch.msgid.link/20260729160749.1621415-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Banana Pi BPI-CM6 module, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 46a8c01700 ("riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-7-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the OrangePi R2S board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 793cc54475 ("riscv: dts: spacemit: enable PMIC on OrangePi R2S")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-6-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the MusePi Pro board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: e2dac7c7a3 ("riscv: dts: spacemit: k1-musepi-pro: add PMIC and power infrastructure")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-5-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the OrangePi RV2 board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: c02c047b92 ("riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-4-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Milk-V Jupiter board, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 7d307daa12 ("riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-3-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Banana Pi BPI-F3 board, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 09a412d397 ("riscv: dts: spacemit: define regulator constraints")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Describe the ADSP Generic Packet Router (GPR) devicetree node as
part of audio subsystem on Qualcomm Eliza SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-dts-qcom-eliza-add-gpr-v3-1-2595beb0cdec@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Even though the EVK comes with 3 Type-C ports, the Eliza EVK only has
one USB controller and a single set of PHYs, which are connected to
the port marked as JUSB.
Also, the EVK comes with an SD card slot.
So describe the PMIC GLINK node, the connector graph, the PHYs and repeater
supplies and enable the USB controller.
Also enable the second SD host controller, describe the card detect GPIO
and the board specific supplies.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-dts-qcom-eliza-cqs-evk-enable-usb-sdcard-v3-1-eadf9da69226@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
One selects in this schema captures "^qcom,.*sa[0-9]+.*$" compatibles,
because there are SAxxxx Qualcomm SoCs. Unfortunately there is also
WSA8810 and WSA8855 I2C speakers, so they need listing too.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-4-8f275c9d3412@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The schema checking for expected naming patterns for SoC IP block nodes
was really incomplete and was checking only nodes with single
compatible.
Fix this by changing "select:" to "contains:" so every
node, except root nodes, having at least one matching compatible will be
evaluated.
This however will evaluate nodes which have some generic fallbacks (e.g.
syscon), thus the schema for expected compatible should also have
"contains:" (with "anyOf:").
These two above are the only functional changes in this commit and the
rest of the diff is indentation change. None of the patterns are
changed (neither in "Preferred naming style" group nor in "Legacy
namings"), none of the compatibles are affected. Basically the second
part of the diff is (simplifying):
properties:
compatible:
- oneOf:
- ......
+ contains:
+ anyOf:
+ ......
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-3-8f275c9d3412@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The schema misses several old style compatibles with SoC component
trailing in the compatible (qcom,IP-SoC):
- qcom,apss-wdt-x1e80100
- qcom,apss-wdt-xxx, qcom,rpm-xxx and qcom,scm-xxx for SoC with code
names (like qcom,rpm-shikra)
- qcom,kpss-gcc-xxx
- qcom,rpmcc-xxx
- qcom,tcsr-xxx
- qcom,usb-hs-phy-xxx
It also missed qcom,ipq806x-ahci.
None of these were flagged by schema, because they were used with
fallbacks and the schema checks only for single compatibles.
Nevertheless document them for complete picture and for future change,
which will apply the schema to fallbacks as well.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-2-8f275c9d3412@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Grow the schema checking for proper SoC compatible naming style with
recently upstreamed new Qualcomm SoCs: Eliza, Kaanapali, Hawi, Mahua,
Maili, Nord and Shikra. The list covers only SoC IP blocks, thus no
Hamoa or Talos in the names, because these are codenames but not used
for SoC IP block naming.
Since switching from model numbers to codenames, this list with explicit
codenames will have to grow and list them all in order for the schema to
work. It feels like a churn, but the compatible naming is still mess,
for example, the schema pci/qcom,pcie-x1e80100.yaml with a legacy naming
vendor,IP-SoC (qcom,pcie-x1e80100) received a new compatible with new
style (qcom,glymur-pcie).
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-1-8f275c9d3412@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add cooling-cells property to the CPU nodes to support
cpufreq cooling devices.
Signed-off-by: Haritha S K <haritha.k@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260724-eliza-cpufreq-v1-1-38f01e47f0f1@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
There is just one set of changes that the remaining IO expansion chips
on the TH1520-based LicheePi 4a board.
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Merge tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
T-HEAD device tree changes for v7.3
There is just one set of changes that the remaining IO expansion chips
on the TH1520-based LicheePi 4a board.
* tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions
riscv: dts: thead: Add IO labels for the IO expansion on I2C1
riscv: dts: thead: lpi4a: sort nodes
riscv: dts: thead: Add TH1520 I2C nodes
riscv: dts: thead: th1520: remove pclk for I2C1
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since the previous commit does not change the phy node name,
the dtschema can not recognize the type of the ethernet phy,
so the following error is produced:
/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$'
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', '
reset-deassert-us', 'reset-gpios' were unexpected)
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
Change the nodename to make the dtschema can recognize the right
PHY type.
Fixes: 9db839d52c ("riscv: dts: spacemit: Fix phy id check for the phy on com260 board")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729012418.154652-2-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Since the previous commit does not change the phy node name,
the dtschema can not recognize the type of the ethernet phy,
so the following error is produced:
/arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$'
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
/arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', 're
set-deassert-us', 'reset-gpios' were unexpected)
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
Change the nodename to make the dtschema can recognize the right
PHY type.
Fixes: 6d6536c880 ("riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729012418.154652-1-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add the six SSPA-based I2S controller nodes for the K3 SoC.
i2s0 and i2s2-i2s5 each have a dedicated per-controller sysclk
divider, so they use the published 7-clock layout (sysclk, bclk, bus,
func, sysclk_div, c_sysclk, c_bclk).
i2s1 uses 6 clocks (sysclk, bclk, bus, func, c_sysclk, c_bclk) because
its sysclk is driven directly by a DDN (ISCCR0) and has no separate
divider stage.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260721-kx-i2s-dts-v1-3-d22cb6cfaab5@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
This pull request includes the following Realtek DT updates for
v7.3, please pull the following:
- Add GPIO node support for the RTD1625 SoC.
- Marc adds the missing the EL2 virtual timer interrupt.
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Merge tag 'realtek-dt-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/yu_chun/linux into soc/dt
arm64: realtek: Device tree updates for v7.3
This pull request includes the following Realtek DT updates for
v7.3, please pull the following:
- Add GPIO node support for the RTD1625 SoC.
- Marc adds the missing the EL2 virtual timer interrupt.
* tag 'realtek-dt-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/yu_chun/linux:
arm64: dts: realtek: Add GPIO support for RTD1625
arm64: dts: realtek: Add EL2 virtual timer interrupt
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The X96QPro+ TV box uses the PH7 pin for its SPDIF output.
Add the relevant bits to the dts now that the dtsi knows about the pin.
Signed-off-by: Per Larsson <per@palvencia.se>
Link: https://patch.msgid.link/20260720174253.7686-2-per@palvencia.se
[wens@kernel.org: reorder property order for spdif-out]
[wens@kernel.org: fix up commit message]
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
When SPDIF support was added for the Allwinner A523 family of SoCs, only
two of the three possible pins were added to the dtsi, since the third
would clash with the first ethernet port (gmac0). However, some devices
don't use gmac0 and instead use gmac1 for the only available ethernet
port, leaving the pin free to use for SPDIF.
Add the remaining pin mux option from the PH pin group to the dtsi so
such devices can (later) use it.
Signed-off-by: Per Larsson <per@palvencia.se>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20260720174253.7686-1-per@palvencia.se
[wens@kernel.org: fix up commit message]
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
The current mount matrix for mpu6050 is wrong. The mount matrix is a
simple transform from the sensor coordinate space to the device
coordinate space described in DT, where, looking at the screen, X
points to the right, Y to the top, and Z towards the user.
The mpu6050 is mounted like this (looking at the screen from the
front; the sensor is on the near side of the PCB, so its Z axis
points towards the user; o marks the pin 1 corner):
+Xs
^
|
+------+
+Ys <--| |
| o |
+------+
so this gives:
Xd = -Ys [0, -1, 0]
Yd = Xs [1, 0, 0]
Zd = Zs [0, 0, 1]
Fixes: 2496b2aaac ("arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer")
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Link: https://patch.msgid.link/20260725111909.2244868-1-megi@xff.cz
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
The Avaota A1 board has an IR receiver chip on the PCB (next to the
Ethernet jacks), wired to the PI8 pin on the SoC.
Enable the CIR receiver in the main power domain.
Tested on the board with evtest and some random TV remote control.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[justin: move the PI8 pinmux node into the dtsi patch]
Signed-off-by: Justin Suess <utilityemal77@gmail.com>
Link: https://patch.msgid.link/20260728024916.993224-5-utilityemal77@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
The X96Q Pro+ TV box has an IR receiver window on the front panel,
wired to the SoC CIR input on PL11.
Enable the CIR receiver in the RTC power domain and mux its RX
signal to PL11.
Tested on an X96Q Pro+ with ir-keytable and nec keybindings with
the remote that it came with in the box.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Justin Suess <utilityemal77@gmail.com>
Link: https://patch.msgid.link/20260728024916.993224-4-utilityemal77@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
The A523 has two CIR receivers, both compatible with the A31 CIR: one
in the CPUX domain, clocked from the main CCU, and one in the RTC
power domain, clocked from the R-CCU.
The RTC domain instance's RX signal is typically muxed to PL11, as on
the X96Q Pro+. The CPUX instance's can be muxed to PI8, which is what
the Avaota A1 uses.
Add nodes for both instances, disabled by default. Since the RX signal
of each instance can be routed to more than one pin, boards with an IR
receiver are expected to add the pinctrl properties next to where they
enable the node.
Add pinmux nodes for both pins: PL11 for the RTC domain instance, and
PI8 for the CPUX one.
Co-developed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Justin Suess <utilityemal77@gmail.com>
Link: https://patch.msgid.link/20260728024916.993224-3-utilityemal77@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
The A523 (sun55i) contains a newer revision of the sunxi CIR receiver.
The reset defaults match the fixed behaviour of the older IP, so the
device works fine when driven as an A31 CIR receiver.
Add the A523 compatible, with allwinner,sun6i-a31-ir as the fallback.
While at it, merge the standalone compatible entries into a single
enum.
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Justin Suess <utilityemal77@gmail.com>
Link: https://patch.msgid.link/20260728024916.993224-2-utilityemal77@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Add the devicetree node for the mt6323 AUXADC.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Several SoCFPGA board DTS files labeled the first QSPI MTD partition
(qspi_boot / partition@0 under fixed-partitions) as "u-boot" while
others already used "Boot and fpga data". Align the QSPI boot
partition label only so naming matches the combined boot + FPGA
image layout and stays consistent across Agilex, N5X, and Stratix 10
SoCDK variants.
No QSPI partition layout or reg properties are changed.
Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls
USB Type-C, battery charging, and various other functions on Qualcomm SoCs.
Add the nodes required to enable SoCCP on Glymur/Mahua SoCs.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260709-glymur-soccp-v6-4-16f70227547d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The currently listed SoCCP and SoCCP DTB reserved memory regions
don't align with the memory requested by the SoCCP Firmware. Fix
this by updating the SoCCP/SoCCP DTB memory regions to reflect the
memory region requirements of the SoCCP firmware, as described in
the Glymur v21 memory map release.
Fixes: 41b6e8db40 ("arm64: dts: qcom: Introduce Glymur base dtsi")
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260709-glymur-soccp-v6-3-16f70227547d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The current PCIe device tree configuration only defines the MSI
interrupt, which is sufficient for basic PCIe operation but limits
advanced functionality.
Add the following interrupt lines to pcie0 and pcie1 nodes:
- dma: DMA interrupt for PCIe DMA operations
- intr: General controller events and link state changes
- aer: Advanced Error Reporting interrupt
- pme: Power Management Event interrupt
This enables enhanced PCIe features and capabilities that were
previously unavailable due to missing interrupt definitions.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
