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MediaTek ARM64 DeviceTree updates

Browse Source 
This adds a couple of fixes and improvements for multiple
 MediaTek SoCs.
 
 In particular:
 - Indentation/whitespace fixes for some devicetrees
 - Documentation improvements for MediaTek Mute-X
 - dtbs-check warnings fixes
   - MT8390 Tungsten boards: removal of unnecessary cells
   - MT6795 SoC: removal of deprecated property in UART DMA
 - MT6359 PMIC's RTC now uses the correct compatible string
 - MT8183/86/88/92/95 SoCs gain support for the UART DMA IPs
 - MT8186 gets a new CCI OPP table to resolve lockups
 - MT8188/83 Chromebooks now got the correct SPI NOR supply
 - MT8192 Asurada drops support for the (unused) MMC1 port
 - MediaTek Genio 510/700/1200 EVKs and Radxa NIO-12L now get
   their PMIC power input tree completed with assignment of
   the correct supplies
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Merge tag 'mtk-dts64-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

MediaTek ARM64 DeviceTree updates

This adds a couple of fixes and improvements for multiple
MediaTek SoCs.

In particular:
- Indentation/whitespace fixes for some devicetrees
- Documentation improvements for MediaTek Mute-X
- dtbs-check warnings fixes
  - MT8390 Tungsten boards: removal of unnecessary cells
  - MT6795 SoC: removal of deprecated property in UART DMA
- MT6359 PMIC's RTC now uses the correct compatible string
- MT8183/86/88/92/95 SoCs gain support for the UART DMA IPs
- MT8186 gets a new CCI OPP table to resolve lockups
- MT8188/83 Chromebooks now got the correct SPI NOR supply
- MT8192 Asurada drops support for the (unused) MMC1 port
- MediaTek Genio 510/700/1200 EVKs and Radxa NIO-12L now get
  their PMIC power input tree completed with assignment of
  the correct supplies

* tag 'mtk-dts64-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  arm64: dts: mediatek: mt6359: use proper compatible for rtc
  arm64: dts: mediatek: mt8395-radxa-nio-12l: Add MT6365 PMIC supplies
  arm64: dts: mediatek: mt8395-genio-common: Add MT6365 PMIC supplies
  arm64: dts: mediatek: mt8390-genio-common: Add MT6365 PMIC supplies
  arm64: dts: mediatek: mt8192-asurada: Disable mmc1 on Spherion
  dt-bindings: soc: mediatek: mutex: Improve title and description
  arm64: dts: mediatek: mt8195: Add and use UART AP_DMA controller
  arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller
  arm64: dts: mediatek: mt8188: Add and use UART AP_DMA controller
  arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller
  arm64: dts: mediatek: mt8183: Add and use UART AP_DMA controller
  arm64: dts: mediatek: mt6795: Remove deprecated UART DMA property
  arm64: dts: mediatek: tungsten-smarc: Remove unnecessary cells
  arm64: dts: mediatek: Correct indentation and whitespace
  arm64: dts: mediatek: mt8188-geralt: Add supply for SPI NOR flash
  arm64: dts: mediatek: mt8183-kukui: Add supply for SPI NOR flash
  arm64: dts: mediatek: mt8186: change CCI OPP scaling mapping

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-07-30 11:28:21 +02:00
commit 253b1036b9
17 changed files with 262 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
View File

@ -4,18 +4,21 @@
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek mutex
title: MediaTek Mute-X
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description: |
Mediatek mutex, namely MUTEX, is used to send the triggers signals called
Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
data path or MDP data path.
In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
the shadow register.
description:
MediaTek Mute-X, namely MUTEX, is used to "mute" or "unmute" trigger signals
like Start Of Frame (SOF), End Of Frame (EOF), Tearing Effect (TE / VSYNC)
and others to each hardware sub-modules in the Display Controller IP or in
the Media Data Path (MDP) IP.
In some SoCs like MT2701, this hardware module may feature functionality
to, for example, protect shadow registers by blocking auto write triggers
upon operation (usually frame push) completion.
MUTEX device node must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

2
arch/arm64/boot/dts/mediatek/mt6359.dtsi
View File

@ -287,7 +287,7 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
};
mt6359rtc: rtc {
compatible = "mediatek,mt6358-rtc";
compatible = "mediatek,mt6359-rtc", "mediatek,mt6358-rtc";
};
};
};

4
arch/arm64/boot/dts/mediatek/mt6795.dtsi
View File

@ -547,8 +547,7 @@ uart1: serial@11003000 {
};
apdma: dma-controller@11000380 {
compatible = "mediatek,mt6795-uart-dma",
"mediatek,mt6577-uart-dma";
compatible = "mediatek,mt6795-uart-dma";
reg = <0 0x11000380 0 0x60>,
<0 0x11000400 0 0x60>,
<0 0x11000480 0 0x60>,
@ -568,7 +567,6 @@ apdma: dma-controller@11000380 {
dma-requests = <8>;
clocks = <&pericfg CLK_PERI_AP_DMA>;
clock-names = "apdma";
mediatek,dma-33bits;
#dma-cells = <1>;
};

6
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
View File

@ -86,7 +86,7 @@ touchscreen: touchscreen@10 {
};
&i2c2 {
pinctrl-names = "default";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
@ -101,7 +101,7 @@ eeprom@58 {
};
&i2c4 {
pinctrl-names = "default";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
@ -381,5 +381,5 @@ &qca_wifi {
};
&i2c_tunnel {
google,remote-bus = <2>;
google,remote-bus = <2>;
};

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
View File

@ -19,6 +19,6 @@ / {
};
&panel {
status = "okay";
compatible = "boe,tv101wum-nl6";
status = "okay";
compatible = "boe,tv101wum-nl6";
};

2
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -849,6 +849,8 @@ w25q64dw: flash@0 {
compatible = "winbond,w25q64dw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
/* Power actually controlled by security chip */
vcc-supply = <&pp1800_alw>;
};
};

22
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1071,6 +1071,22 @@ gce: mailbox@10238000 {
clock-names = "gce";
};
apdma: dma-controller@11000780 {
compatible = "mediatek,mt8183-uart-dma", "mediatek,mt6577-uart-dma";
reg = <0 0x11000780 0 0x80>, <0 0x11000800 0 0x80>,
<0 0x11000880 0 0x80>, <0 0x11000900 0 0x80>,
<0 0x11000980 0 0x80>, <0 0x11000a00 0 0x80>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_AP_DMA>;
#dma-cells = <1>;
dma-requests = <6>;
};
auxadc: auxadc@11001000 {
compatible = "mediatek,mt8183-auxadc",
"mediatek,mt8173-auxadc";
@ -1088,6 +1104,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1098,6 +1116,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1108,6 +1128,8 @@ uart2: serial@11004000 {
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};

132
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -48,79 +48,79 @@ cci_opp: opp-table-cci {
compatible = "operating-points-v2";
opp-shared;
cci_opp_0: opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <600000>;
};
cci_opp_1: opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-microvolt = <675000>;
};
cci_opp_2: opp-612000000 {
opp-hz = /bits/ 64 <612000000>;
opp-microvolt = <693750>;
};
cci_opp_3: opp-682000000 {
opp-hz = /bits/ 64 <682000000>;
opp-microvolt = <718750>;
};
cci_opp_4: opp-752000000 {
opp-hz = /bits/ 64 <752000000>;
opp-microvolt = <743750>;
};
cci_opp_5: opp-822000000 {
opp-hz = /bits/ 64 <822000000>;
opp-microvolt = <768750>;
};
cci_opp_6: opp-875000000 {
opp-hz = /bits/ 64 <875000000>;
opp-microvolt = <781250>;
};
cci_opp_7: opp-927000000 {
opp-hz = /bits/ 64 <927000000>;
cci_opp_0: opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <800000>;
};
cci_opp_8: opp-980000000 {
opp-hz = /bits/ 64 <980000000>;
opp-microvolt = <818750>;
cci_opp_1: opp-840000000 {
opp-hz = /bits/ 64 <840000000>;
opp-microvolt = <806250>;
};
cci_opp_9: opp-1050000000 {
opp-hz = /bits/ 64 <1050000000>;
opp-microvolt = <843750>;
cci_opp_2: opp-880000000 {
opp-hz = /bits/ 64 <880000000>;
opp-microvolt = <812500>;
};
cci_opp_10: opp-1120000000 {
cci_opp_3: opp-920000000 {
opp-hz = /bits/ 64 <920000000>;
opp-microvolt = <825000>;
};
cci_opp_4: opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-microvolt = <831250>;
};
cci_opp_5: opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <837500>;
};
cci_opp_6: opp-1040000000 {
opp-hz = /bits/ 64 <1040000000>;
opp-microvolt = <850000>;
};
cci_opp_7: opp-1080000000 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <856250>;
};
cci_opp_8: opp-1120000000 {
opp-hz = /bits/ 64 <1120000000>;
opp-microvolt = <862500>;
};
cci_opp_11: opp-1155000000 {
opp-hz = /bits/ 64 <1155000000>;
cci_opp_9: opp-1160000000 {
opp-hz = /bits/ 64 <1160000000>;
opp-microvolt = <887500>;
};
cci_opp_12: opp-1190000000 {
opp-hz = /bits/ 64 <1190000000>;
opp-microvolt = <906250>;
cci_opp_10: opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <912500>;
};
cci_opp_13: opp-1260000000 {
opp-hz = /bits/ 64 <1260000000>;
opp-microvolt = <950000>;
cci_opp_11: opp-1240000000 {
opp-hz = /bits/ 64 <1240000000>;
opp-microvolt = <937500>;
};
cci_opp_14: opp-1330000000 {
opp-hz = /bits/ 64 <1330000000>;
opp-microvolt = <993750>;
cci_opp_12: opp-1280000000 {
opp-hz = /bits/ 64 <1280000000>;
opp-microvolt = <962500>;
};
cci_opp_13: opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <987500>;
};
cci_opp_14: opp-1360000000 {
opp-hz = /bits/ 64 <1360000000>;
opp-microvolt = <1012500>;
};
cci_opp_15: opp-1400000000 {
@ -1142,6 +1142,22 @@ systimer: timer@10017000 {
clocks = <&clk13m>;
};
apdma: dma-controller@10200d80 {
compatible = "mediatek,mt8186-uart-dma", "mediatek,mt6835-uart-dma";
reg = <0 0x10200d80 0 0x80>, <0 0x10200e00 0 0x80>,
<0 0x10200e80 0 0x80>, <0 0x10200f00 0 0x80>,
<0 0x10200f80 0 0x80>, <0 0x10201000 0 0x80>;
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
#dma-cells = <1>;
dma-requests = <6>;
};
gce: mailbox@1022c000 {
compatible = "mediatek,mt8186-gce";
reg = <0 0X1022c000 0 0x4000>;
@ -1218,6 +1234,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1228,6 +1246,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1482,6 +1502,8 @@ uart2: serial@11018000 {
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};

1
arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
View File

@ -645,6 +645,7 @@ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
vcc-supply = <&pp1800_ldo_z1>;
};
};

33
arch/arm64/boot/dts/mediatek/mt8188.dtsi
View File

@ -1360,6 +1360,31 @@ spmi: spmi@10027000 {
clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
};
apdma: dma-controller@10220880 {
compatible = "mediatek,mt8188-uart-dma", "mediatek,mt6835-uart-dma";
reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>,
<0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>,
<0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>,
<0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>,
<0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>,
<0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
#dma-cells = <1>;
dma-requests = <12>;
};
infra_iommu: iommu@10315000 {
compatible = "mediatek,mt8188-iommu-infra";
reg = <0 0x10315000 0 0x1000>;
@ -1512,6 +1537,8 @@ uart0: serial@11001100 {
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1521,6 +1548,8 @@ uart1: serial@11001200 {
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1530,6 +1559,8 @@ uart2: serial@11001300 {
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1539,6 +1570,8 @@ uart3: serial@11001400 {
interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
clock-names = "baud", "bus";
dmas = <&apdma 6>, <&apdma 7>;
dma-names = "tx", "rx";
status = "disabled";
};

4
arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
View File

@ -64,6 +64,10 @@ &rt5682 {
VBAT-supply = <&pp3300_ldo_z>;
};
&mmc1 {
status = "disabled";
};
&sound {
compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682";

17
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -741,6 +741,19 @@ spmi: spmi@10027000 {
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
apdma: dma-controller@10217a80 {
compatible = "mediatek,mt8192-uart-dma", "mediatek,mt6835-uart-dma";
reg = <0 0x10217a80 0 0x80>, <0 0x10217b00 0 0x80>,
<0 0x10217b80 0 0x80>, <0 0x10217c00 0 0x80>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg CLK_INFRA_AP_DMA>;
#dma-cells = <1>;
dma-requests = <4>;
};
gce: mailbox@10228000 {
compatible = "mediatek,mt8192-gce";
reg = <0 0x10228000 0 0x4000>;
@ -765,6 +778,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -775,6 +790,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};

37
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -904,6 +904,31 @@ spmi: spmi@10027000 {
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
apdma: dma-controller@10220880 {
compatible = "mediatek,mt8195-uart-dma", "mediatek,mt6835-uart-dma";
reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>,
<0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>,
<0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>,
<0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>,
<0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>,
<0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
#dma-cells = <1>;
dma-requests = <12>;
};
iommu_infra: infra-iommu@10315000 {
compatible = "mediatek,mt8195-iommu-infra";
reg = <0 0x10315000 0 0x5000>;
@ -1040,6 +1065,8 @@ uart0: serial@11001100 {
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1050,6 +1077,8 @@ uart1: serial@11001200 {
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1060,6 +1089,8 @@ uart2: serial@11001300 {
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1070,6 +1101,8 @@ uart3: serial@11001400 {
interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
clock-names = "baud", "bus";
dmas = <&apdma 6>, <&apdma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1080,6 +1113,8 @@ uart4: serial@11001500 {
interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
clock-names = "baud", "bus";
dmas = <&apdma 8>, <&apdma 9>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1090,6 +1125,8 @@ uart5: serial@11001600 {
interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
clock-names = "baud", "bus";
dmas = <&apdma 10>, <&apdma 11>;
dma-names = "tx", "rx";
status = "disabled";
};

19
arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
View File

@ -7,7 +7,7 @@
*
* Copyright (C) 2025 Collabora Ltd.
* Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include "mt6365.dtsi"
@ -1304,6 +1304,23 @@ ethernet_phy0: ethernet-phy@1 {
&pmic {
interrupt-parent = <&pio>;
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
vsys-smps-supply = <&reg_vsys>;
vsys-vcore-supply = <&reg_vsys>;
vsys-vgpu11-supply = <&reg_vsys>;
vsys-vgpu12-supply = <&reg_vsys>;
vsys-vpa-supply = <&reg_vsys>;
vsys-vproc1-supply = <&reg_vsys>;
vsys-vproc2-supply = <&reg_vsys>;
vsys-vpu-supply = <&reg_vsys>;
vsys-vs1-supply = <&reg_vsys>;
vsys-vs2-supply = <&reg_vsys>;
vsys-vmodem-supply = <&reg_vsys>;
vsys-ldo1-supply = <&reg_vsys>;
vsys-ldo2-supply = <&reg_vsys>;
vs1-ldo1-supply = <&mt6359_vs1_buck_reg>;
vs1-ldo2-supply = <&mt6359_vs1_buck_reg>;
vs2-ldo1-supply = <&mt6359_vs2_buck_reg>;
vs2-ldo2-supply = <&mt6359_vs2_buck_reg>;
mt6365keys: keys {
compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys";

4
arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi
View File

@ -265,8 +265,6 @@ &disp_pwm0 {
};
&disp_dsi0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
@ -1049,8 +1047,6 @@ &xhci2 {
ethernet@1 {
compatible = "usb424,7850";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mdio {
#address-cells = <1>;

17
arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
View File

@ -1170,6 +1170,23 @@ pins {
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
vsys-smps-supply = <&reg_vsys>;
vsys-vcore-supply = <&reg_vsys>;
vsys-vgpu11-supply = <&reg_vsys>;
vsys-vgpu12-supply = <&reg_vsys>;
vsys-vpa-supply = <&reg_vsys>;
vsys-vproc1-supply = <&reg_vsys>;
vsys-vproc2-supply = <&reg_vsys>;
vsys-vpu-supply = <&reg_vsys>;
vsys-vs1-supply = <&reg_vsys>;
vsys-vs2-supply = <&reg_vsys>;
vsys-vmodem-supply = <&reg_vsys>;
vsys-ldo1-supply = <&reg_vsys_buck>;
vsys-ldo2-supply = <&reg_vsys_buck>;
vs1-ldo1-supply = <&mt6359_vs1_buck_reg>;
vs1-ldo2-supply = <&mt6359_vs1_buck_reg>;
vs2-ldo1-supply = <&mt6359_vs2_buck_reg>;
vs2-ldo2-supply = <&mt6359_vs2_buck_reg>;
mt6365keys: keys {
compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys";

17
arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
View File

@ -1033,6 +1033,23 @@ &pciephy {
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
vsys-smps-supply = <&vsys>;
vsys-vcore-supply = <&vsys>;
vsys-vgpu11-supply = <&vsys>;
vsys-vgpu12-supply = <&vsys>;
vsys-vpa-supply = <&vsys>;
vsys-vproc1-supply = <&vsys>;
vsys-vproc2-supply = <&vsys>;
vsys-vpu-supply = <&vsys>;
vsys-vs1-supply = <&vsys>;
vsys-vs2-supply = <&vsys>;
vsys-vmodem-supply = <&vsys>;
vsys-ldo1-supply = <&vsys_buck>;
vsys-ldo2-supply = <&vsys_buck>;
vs1-ldo1-supply = <&mt6359_vs1_buck_reg>;
vs1-ldo2-supply = <&mt6359_vs1_buck_reg>;
vs2-ldo1-supply = <&mt6359_vs2_buck_reg>;
vs2-ldo2-supply = <&mt6359_vs2_buck_reg>;
mt6365keys: keys {
compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys";