From c41cd028e8fb138aa6243d224d637db15354ea95 Mon Sep 17 00:00:00 2001 From: Mark Tseng Date: Fri, 29 May 2026 18:05:08 +0800 Subject: [PATCH 01/17] arm64: dts: mediatek: mt8186: change CCI OPP scaling mapping The original CCI OPP table minimum frequency 500Mhz is too low to cause system stall, So it need update to new version, 1.4G ~ 0.8G. Signed-off-by: Mark Tseng Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 110 +++++++++++------------ 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index b91f88ffae0e..fded6345d422 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -48,79 +48,79 @@ cci_opp: opp-table-cci { compatible = "operating-points-v2"; opp-shared; - cci_opp_0: opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <600000>; - }; - - cci_opp_1: opp-560000000 { - opp-hz = /bits/ 64 <560000000>; - opp-microvolt = <675000>; - }; - - cci_opp_2: opp-612000000 { - opp-hz = /bits/ 64 <612000000>; - opp-microvolt = <693750>; - }; - - cci_opp_3: opp-682000000 { - opp-hz = /bits/ 64 <682000000>; - opp-microvolt = <718750>; - }; - - cci_opp_4: opp-752000000 { - opp-hz = /bits/ 64 <752000000>; - opp-microvolt = <743750>; - }; - - cci_opp_5: opp-822000000 { - opp-hz = /bits/ 64 <822000000>; - opp-microvolt = <768750>; - }; - - cci_opp_6: opp-875000000 { - opp-hz = /bits/ 64 <875000000>; - opp-microvolt = <781250>; - }; - - cci_opp_7: opp-927000000 { - opp-hz = /bits/ 64 <927000000>; + cci_opp_0: opp-800000000 { + opp-hz = /bits/ 64 <800000000>; opp-microvolt = <800000>; }; - cci_opp_8: opp-980000000 { - opp-hz = /bits/ 64 <980000000>; - opp-microvolt = <818750>; + cci_opp_1: opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <806250>; }; - cci_opp_9: opp-1050000000 { - opp-hz = /bits/ 64 <1050000000>; - opp-microvolt = <843750>; + cci_opp_2: opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-microvolt = <812500>; }; - cci_opp_10: opp-1120000000 { + cci_opp_3: opp-920000000 { + opp-hz = /bits/ 64 <920000000>; + opp-microvolt = <825000>; + }; + + cci_opp_4: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <831250>; + }; + + cci_opp_5: opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <837500>; + }; + + cci_opp_6: opp-1040000000 { + opp-hz = /bits/ 64 <1040000000>; + opp-microvolt = <850000>; + }; + + cci_opp_7: opp-1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <856250>; + }; + + cci_opp_8: opp-1120000000 { opp-hz = /bits/ 64 <1120000000>; opp-microvolt = <862500>; }; - cci_opp_11: opp-1155000000 { - opp-hz = /bits/ 64 <1155000000>; + cci_opp_9: opp-1160000000 { + opp-hz = /bits/ 64 <1160000000>; opp-microvolt = <887500>; }; - cci_opp_12: opp-1190000000 { - opp-hz = /bits/ 64 <1190000000>; - opp-microvolt = <906250>; + cci_opp_10: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <912500>; }; - cci_opp_13: opp-1260000000 { - opp-hz = /bits/ 64 <1260000000>; - opp-microvolt = <950000>; + cci_opp_11: opp-1240000000 { + opp-hz = /bits/ 64 <1240000000>; + opp-microvolt = <937500>; }; - cci_opp_14: opp-1330000000 { - opp-hz = /bits/ 64 <1330000000>; - opp-microvolt = <993750>; + cci_opp_12: opp-1280000000 { + opp-hz = /bits/ 64 <1280000000>; + opp-microvolt = <962500>; + }; + + cci_opp_13: opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <987500>; + }; + + cci_opp_14: opp-1360000000 { + opp-hz = /bits/ 64 <1360000000>; + opp-microvolt = <1012500>; }; cci_opp_15: opp-1400000000 { From 1f16e99cd8361b33758205eba587dbe40a82975a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jul 2026 16:37:45 +0800 Subject: [PATCH 02/17] arm64: dts: mediatek: mt8183-kukui: Add supply for SPI NOR flash The SPI NOR flash is powered from the always on 1.8V power rail through a load switch that is controlled by the security chip. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index a8e257b21a88..5ea499f349f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -849,6 +849,8 @@ w25q64dw: flash@0 { compatible = "winbond,w25q64dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; + /* Power actually controlled by security chip */ + vcc-supply = <&pp1800_alw>; }; }; From eb3e990db356964d64f5cc258d30776c0363f9e9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jul 2026 16:37:58 +0800 Subject: [PATCH 03/17] arm64: dts: mediatek: mt8188-geralt: Add supply for SPI NOR flash The SPI NOR flash is powered the "always on" 1.8V LDO regulated power rail. Add the supply for the SPI NOR flash. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 4cb23595d17b..f382f90c48f5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -645,6 +645,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; + vcc-supply = <&pp1800_ldo_z1>; }; }; From 7f9fc91718bd7e69c3c82123f3c05748a3f2793d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:35:16 +0200 Subject: [PATCH 04/17] arm64: dts: mediatek: Correct indentation and whitespace Correct spaces or mix of tabs+spaces into proper tab-indented lines and remove other whitespace violations. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi | 6 +++--- arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index b702ff066636..b210845277e1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -86,7 +86,7 @@ touchscreen: touchscreen@10 { }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; @@ -101,7 +101,7 @@ eeprom@58 { }; &i2c4 { - pinctrl-names = "default"; + pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; @@ -381,5 +381,5 @@ &qca_wifi { }; &i2c_tunnel { - google,remote-bus = <2>; + google,remote-bus = <2>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts index 095279e55d50..cc8c913d2763 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts @@ -19,6 +19,6 @@ / { }; &panel { - status = "okay"; - compatible = "boe,tv101wum-nl6"; + status = "okay"; + compatible = "boe,tv101wum-nl6"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index b0c97930a0e6..ce27f314d19d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -7,7 +7,7 @@ * * Copyright (C) 2025 Collabora Ltd. * Louis-Alexis Eyraud - * AngeloGioacchino Del Regno + * AngeloGioacchino Del Regno */ #include "mt6365.dtsi" From dee885034faf7c9b265987407ab303b464ed0058 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:20:21 +0200 Subject: [PATCH 05/17] arm64: dts: mediatek: tungsten-smarc: Remove unnecessary cells Remove unnecessary address and size cells from both the disp_dsi0 and the xhci2's ethernet usb device subnode to fix a dtbs_check warning for avoid_unnecessary_addr_size. Fixes: 9fda4a8a479f ("arm64: dts: mediatek: add device tree for Tungsten 510 board") Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi index 9f5a0ec563e8..8256279c5629 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -265,8 +265,6 @@ &disp_pwm0 { }; &disp_dsi0 { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; ports { @@ -1049,8 +1047,6 @@ &xhci2 { ethernet@1 { compatible = "usb424,7850"; reg = <1>; - #address-cells = <1>; - #size-cells = <0>; mdio { #address-cells = <1>; From b6db6e4b4bfb339c0e3db87d23545af53ac2eaeb Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:18 +0200 Subject: [PATCH 06/17] arm64: dts: mediatek: mt6795: Remove deprecated UART DMA property Remove the mediatek,dma-33bits property as it is now deprecated and, while at it, also remove the fallback compatible as it was not entirely right to use anyway, because this IP is not fully compatible with the one found in MT6577 and would create more issues than the ones it could resolve (as in - it's better to not probe the controller than to probe it and manage it in some incorrect way). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 134cfa77e3b1..6dd706b27830 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -547,8 +547,7 @@ uart1: serial@11003000 { }; apdma: dma-controller@11000380 { - compatible = "mediatek,mt6795-uart-dma", - "mediatek,mt6577-uart-dma"; + compatible = "mediatek,mt6795-uart-dma"; reg = <0 0x11000380 0 0x60>, <0 0x11000400 0 0x60>, <0 0x11000480 0 0x60>, @@ -568,7 +567,6 @@ apdma: dma-controller@11000380 { dma-requests = <8>; clocks = <&pericfg CLK_PERI_AP_DMA>; clock-names = "apdma"; - mediatek,dma-33bits; #dma-cells = <1>; }; From 5551862f57e5b673fe4d9f3542b7037dbc95ddc9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:20 +0200 Subject: [PATCH 07/17] arm64: dts: mediatek: mt8183: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each of the three UART controllers. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 95cc06799533..8b0992548431 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1071,6 +1071,22 @@ gce: mailbox@10238000 { clock-names = "gce"; }; + apdma: dma-controller@11000780 { + compatible = "mediatek,mt8183-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000780 0 0x80>, <0 0x11000800 0 0x80>, + <0 0x11000880 0 0x80>, <0 0x11000900 0 0x80>, + <0 0x11000980 0 0x80>, <0 0x11000a00 0 0x80>; + interrupts = , + , + , + , + , + ; + clocks = <&infracfg CLK_INFRA_AP_DMA>; + #dma-cells = <1>; + dma-requests = <6>; + }; + auxadc: auxadc@11001000 { compatible = "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc"; @@ -1088,6 +1104,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1098,6 +1116,8 @@ uart1: serial@11003000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1108,6 +1128,8 @@ uart2: serial@11004000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; From e3999d8e4cfeb84ac67d8dbe185943304e54c1f9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:21 +0200 Subject: [PATCH 08/17] arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each of the three UART controllers. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index fded6345d422..621408439ffa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1142,6 +1142,22 @@ systimer: timer@10017000 { clocks = <&clk13m>; }; + apdma: dma-controller@10200d80 { + compatible = "mediatek,mt8186-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10200d80 0 0x80>, <0 0x10200e00 0 0x80>, + <0 0x10200e80 0 0x80>, <0 0x10200f00 0 0x80>, + <0 0x10200f80 0 0x80>, <0 0x10201000 0 0x80>; + interrupts = , + , + , + , + , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + #dma-cells = <1>; + dma-requests = <6>; + }; + gce: mailbox@1022c000 { compatible = "mediatek,mt8186-gce"; reg = <0 0X1022c000 0 0x4000>; @@ -1218,6 +1234,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1228,6 +1246,8 @@ uart1: serial@11003000 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1482,6 +1502,8 @@ uart2: serial@11018000 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; From f58f96921848f4037c71c48ddda0a408fed0a879 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:22 +0200 Subject: [PATCH 09/17] arm64: dts: mediatek: mt8188: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each of the four UART controllers that are declared. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 75133794cec3..14a320f0c70c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1360,6 +1360,31 @@ spmi: spmi@10027000 { clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; }; + apdma: dma-controller@10220880 { + compatible = "mediatek,mt8188-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>, + <0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>, + <0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>, + <0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>, + <0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>, + <0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + #dma-cells = <1>; + dma-requests = <12>; + }; + infra_iommu: iommu@10315000 { compatible = "mediatek,mt8188-iommu-infra"; reg = <0 0x10315000 0 0x1000>; @@ -1512,6 +1537,8 @@ uart0: serial@11001100 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1521,6 +1548,8 @@ uart1: serial@11001200 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1530,6 +1559,8 @@ uart2: serial@11001300 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1539,6 +1570,8 @@ uart3: serial@11001400 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; From f0c918fe2469c35390def236ea1da32686461100 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:23 +0200 Subject: [PATCH 10/17] arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to its two uart controllers. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9f8f115edd4c..898953acdb61 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -741,6 +741,19 @@ spmi: spmi@10027000 { assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; }; + apdma: dma-controller@10217a80 { + compatible = "mediatek,mt8192-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10217a80 0 0x80>, <0 0x10217b00 0 0x80>, + <0 0x10217b80 0 0x80>, <0 0x10217c00 0 0x80>; + interrupts = , + , + , + ; + clocks = <&infracfg CLK_INFRA_AP_DMA>; + #dma-cells = <1>; + dma-requests = <4>; + }; + gce: mailbox@10228000 { compatible = "mediatek,mt8192-gce"; reg = <0 0x10228000 0 0x4000>; @@ -765,6 +778,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -775,6 +790,8 @@ uart1: serial@11003000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; From d8461fe07c1e4defee981da778eaeec43d4cbba0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:24 +0200 Subject: [PATCH 11/17] arm64: dts: mediatek: mt8195: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each uart controller. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c72e34c57629..9aaf8b6edcb5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -904,6 +904,31 @@ spmi: spmi@10027000 { assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; }; + apdma: dma-controller@10220880 { + compatible = "mediatek,mt8195-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>, + <0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>, + <0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>, + <0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>, + <0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>, + <0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + #dma-cells = <1>; + dma-requests = <12>; + }; + iommu_infra: infra-iommu@10315000 { compatible = "mediatek,mt8195-iommu-infra"; reg = <0 0x10315000 0 0x5000>; @@ -1040,6 +1065,8 @@ uart0: serial@11001100 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1050,6 +1077,8 @@ uart1: serial@11001200 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1060,6 +1089,8 @@ uart2: serial@11001300 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1070,6 +1101,8 @@ uart3: serial@11001400 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1080,6 +1113,8 @@ uart4: serial@11001500 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; clock-names = "baud", "bus"; + dmas = <&apdma 8>, <&apdma 9>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1090,6 +1125,8 @@ uart5: serial@11001600 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; clock-names = "baud", "bus"; + dmas = <&apdma 10>, <&apdma 11>; + dma-names = "tx", "rx"; status = "disabled"; }; From 11c3fc9e3db80adb129e78c296cf2bd9ea6daca7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Jul 2026 14:20:38 +0200 Subject: [PATCH 12/17] dt-bindings: soc: mediatek: mutex: Improve title and description Improve both the title and the description of this hardware to disambiguate its functionality from a hardware mutex and/or from a hwspinlock. Though in datasheets this is called "DISP_MUTEX", the meaning is is "Mute-X" (where "X" means "any hardware trigger signal") really as this is what this piece of hardware does: muting or unmuting of signals in each sub-IP of the display or other multimedia related controllers. Based on that, also clarify the description text, as to make sure that the information is actually accurate. While at it, also avoid forcing literal blocks in the description as there is nothing in there needing that (no ascii graph or other stuff that needs a literal block anyway), and add myself in the list of maintainers. Acked-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/soc/mediatek/mediatek,mutex.yaml | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 5267cfe92572..1ba086ad749d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -4,18 +4,21 @@ $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek mutex +title: MediaTek Mute-X maintainers: + - AngeloGioacchino Del Regno - Chun-Kuang Hu - Philipp Zabel -description: | - Mediatek mutex, namely MUTEX, is used to send the triggers signals called - Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display - data path or MDP data path. - In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects - the shadow register. +description: + MediaTek Mute-X, namely MUTEX, is used to "mute" or "unmute" trigger signals + like Start Of Frame (SOF), End Of Frame (EOF), Tearing Effect (TE / VSYNC) + and others to each hardware sub-modules in the Display Controller IP or in + the Media Data Path (MDP) IP. + In some SoCs like MT2701, this hardware module may feature functionality + to, for example, protect shadow registers by blocking auto write triggers + upon operation (usually frame push) completion. MUTEX device node must be siblings to the central MMSYS_CONFIG node. For a description of the MMSYS_CONFIG binding, see Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml From 934cccd2c6795a20d04bd470ec7eb3151950fbfc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 20 Jul 2026 17:27:57 +0800 Subject: [PATCH 13/17] arm64: dts: mediatek: mt8192-asurada: Disable mmc1 on Spherion Spherion does not have an micro SD card slot. Disable mmc1. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index 163960f58db5..68caf4c58cfe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -64,6 +64,10 @@ &rt5682 { VBAT-supply = <&pp3300_ldo_z>; }; +&mmc1 { + status = "disabled"; +}; + &sound { compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682"; From 917b5c98d768a47daff91f2d21a000bc3e24a7a4 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Mon, 1 Jun 2026 16:15:45 +0200 Subject: [PATCH 14/17] arm64: dts: mediatek: mt8390-genio-common: Add MT6365 PMIC supplies Mediatek Genio 510 and 700 EVK boards integrate a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board common definition include file. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8390-genio-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index ce27f314d19d..0dfd0c7de41d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1304,6 +1304,23 @@ ethernet_phy0: ethernet-phy@1 { &pmic { interrupt-parent = <&pio>; interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <®_vsys>; + vsys-vcore-supply = <®_vsys>; + vsys-vgpu11-supply = <®_vsys>; + vsys-vgpu12-supply = <®_vsys>; + vsys-vpa-supply = <®_vsys>; + vsys-vproc1-supply = <®_vsys>; + vsys-vproc2-supply = <®_vsys>; + vsys-vpu-supply = <®_vsys>; + vsys-vs1-supply = <®_vsys>; + vsys-vs2-supply = <®_vsys>; + vsys-vmodem-supply = <®_vsys>; + vsys-ldo1-supply = <®_vsys>; + vsys-ldo2-supply = <®_vsys>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; mt6365keys: keys { compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; From cc90ec9b892061a3e4dbd4e944e18a81758da2ff Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Mon, 1 Jun 2026 16:15:46 +0200 Subject: [PATCH 15/17] arm64: dts: mediatek: mt8395-genio-common: Add MT6365 PMIC supplies Mediatek Genio 1200 EVK board integrates a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board common definition include file. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-genio-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index edc5539bebde..7ea45b6bc663 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -1170,6 +1170,23 @@ pins { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <®_vsys>; + vsys-vcore-supply = <®_vsys>; + vsys-vgpu11-supply = <®_vsys>; + vsys-vgpu12-supply = <®_vsys>; + vsys-vpa-supply = <®_vsys>; + vsys-vproc1-supply = <®_vsys>; + vsys-vproc2-supply = <®_vsys>; + vsys-vpu-supply = <®_vsys>; + vsys-vs1-supply = <®_vsys>; + vsys-vs2-supply = <®_vsys>; + vsys-vmodem-supply = <®_vsys>; + vsys-ldo1-supply = <®_vsys_buck>; + vsys-ldo2-supply = <®_vsys_buck>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; mt6365keys: keys { compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; From 759e989b840b4c2ffdb74cf1e1da0cee66e89f4c Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Mon, 1 Jun 2026 16:15:47 +0200 Subject: [PATCH 16/17] arm64: dts: mediatek: mt8395-radxa-nio-12l: Add MT6365 PMIC supplies Radxa NIO-12L EVK board integrates a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board devicetree file. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index b279eed1bfc3..9cf0315da035 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -1033,6 +1033,23 @@ &pciephy { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&vsys>; + vsys-vcore-supply = <&vsys>; + vsys-vgpu11-supply = <&vsys>; + vsys-vgpu12-supply = <&vsys>; + vsys-vpa-supply = <&vsys>; + vsys-vproc1-supply = <&vsys>; + vsys-vproc2-supply = <&vsys>; + vsys-vpu-supply = <&vsys>; + vsys-vs1-supply = <&vsys>; + vsys-vs2-supply = <&vsys>; + vsys-vmodem-supply = <&vsys>; + vsys-ldo1-supply = <&vsys_buck>; + vsys-ldo2-supply = <&vsys_buck>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; mt6365keys: keys { compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; From 3dc552c1bab6e83bb45af0a49f3a900845a24495 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 1 Jul 2026 10:38:21 +0200 Subject: [PATCH 17/17] arm64: dts: mediatek: mt6359: use proper compatible for rtc The MT6359 PMIC include file uses directly "mediatek,mt6358-rtc" compatible string for the rtc subnode, but not its own compatible string. Now that the "mediatek,mt6359-rtc" compatible is properly declared in the dt-bindings, use it with "mediatek,mt6358-rtc" as fallback. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index a953fb527b69..52fb0f832260 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -287,7 +287,7 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { }; mt6359rtc: rtc { - compatible = "mediatek,mt6358-rtc"; + compatible = "mediatek,mt6359-rtc", "mediatek,mt6358-rtc"; }; }; };