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arm64: dts: qcom: glymur: add SoCCP DT node

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The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls
USB Type-C, battery charging, and various other functions on Qualcomm SoCs.

Add the nodes required to enable SoCCP on Glymur/Mahua SoCs.

Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260709-glymur-soccp-v6-4-16f70227547d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Sibi Sankar 2026-07-09 23:39:45 -07:00 committed by Bjorn Andersson
parent 61e5b39e96
commit fe76d6b32e
2 changed files with 49 additions and 0 deletions
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5
arch/arm64/boot/dts/qcom/glymur-crd.dtsi
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@ -956,6 +956,11 @@ right_tweeter: speaker@0,1 {
};
};
&remoteproc_soccp {
firmware-name = "qcom/glymur/soccp.mbn",
"qcom/glymur/soccp_dtb.mbn";
};
&tlmm {
gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
<10 2>, /* OOB UART */

44
arch/arm64/boot/dts/qcom/glymur.dtsi
View File

@ -2330,6 +2330,50 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
remoteproc_soccp: remoteproc@d00000 {
compatible = "qcom,glymur-soccp-pas";
reg = <0x0 0x00d00000 0x0 0x200000>;
interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"pong";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MX>;
power-domain-names = "cx",
"mx";
memory-region = <&soccp_mem>,
<&soccpdtb_mem>;
qcom,smem-states = <&soccp_smp2p_out 0>,
<&soccp_smp2p_out 8>;
qcom,smem-state-names = "stop",
"ping";
glink-edge {
interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_SOCCP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <19>;
label = "soccp";
};
};
usb_hs_phy: phy@fa0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";