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riscv: dts: spacemit: k3: Add QSPI support for Pico-ITX board

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Enable QSPI with proper pinmux on the Pico-ITX board, and describe the
NOR flash wired to it.

Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
This commit is contained in:
Zhengyu He 2026-07-11 09:38:52 +08:00 committed by Yixun Lan
parent e0c1145f4c
commit c7d6ed1ebb
3 changed files with 94 additions and 0 deletions
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56
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
View File

@ -240,6 +240,62 @@ phy0: phy@1 {
};
};
&qspi_cfg {
qspi-pins {
power-source = <1800>;
};
qspi-cs0-pins {
power-source = <1800>;
};
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_cfg>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <26500000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootinfo@0 {
reg = <0x0 0x20000>;
};
fsbl@20000 {
reg = <0x20000 0x80000>;
};
env@a0000 {
reg = <0xa0000 0x10000>;
};
esos@b0000 {
reg = <0xb0000 0x100000>;
};
opensbi@1b0000 {
reg = <0x1b0000 0x60000>;
};
uboot@210000 {
reg = <0x210000 0x5f0000>;
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_0_cfg>;

21
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
View File

@ -690,6 +690,27 @@ pwm19-2-pins {
};
};
/omit-if-no-ref/
qspi_cfg: qspi-cfg {
qspi-pins {
pinmux = <K3_PADCONF(138, 0)>, /* qspi dat0 */
<K3_PADCONF(139, 0)>, /* qspi dat1 */
<K3_PADCONF(140, 0)>, /* qspi dat2 */
<K3_PADCONF(141, 0)>, /* qspi dat3 */
<K3_PADCONF(144, 0)>; /* qspi clk */
bias-disable;
drive-strength = <25>;
};
qspi-cs0-pins {
pinmux = <K3_PADCONF(142, 0)>; /* qspi cs0 */
bias-disable;
drive-strength = <25>;
};
};
/omit-if-no-ref/
uart0_0_cfg: uart0-0-cfg {
uart0-0-pins {

17
arch/riscv/boot/dts/spacemit/k3.dtsi
View File

@ -1099,6 +1099,23 @@ pll: clock-controller@d4090000 {
#clock-cells = <1>;
};
qspi: spi@d420c000 {
compatible = "spacemit,k3-qspi",
"spacemit,k1-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xd420c000 0x0 0x1000>,
<0x0 0xb8000000 0x0 0xc00000>;
reg-names = "QuadSPI", "QuadSPI-memory";
clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>,
<&syscon_apmu CLK_APMU_QSPI>;
clock-names = "qspi_en", "qspi";
resets = <&syscon_apmu RESET_APMU_QSPI>,
<&syscon_apmu RESET_APMU_QSPI_BUS>;
interrupts = <117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci0: mmc@d4280000 {
compatible = "spacemit,k3-sdhci";
reg = <0x0 0xd4280000 0x0 0x200>;