linux

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Author	SHA1	Message	Date
Stephen Boyd	8397c58ea7	Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next - Add Mediatek MT8196 clk drivers * clk-marvell: clk: mmp: pxa1908: Instantiate power driver through auxiliary bus * clk-xilinx: clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() * clk-mediatek: (31 commits) clk: mediatek: Add MT8196 vencsys clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 apmixedsys clock support dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro ... * clk-loongson: clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible	2025-10-06 13:00:22 -05:00
Stephen Boyd	b91217d912	Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next - Speed up clk_core_lookup() by using a hashtable * clk-microchip: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable * clk-lookup: clk: Use hashtable for global clk lookups clk: Sort include statements * clk-st: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings	2025-10-06 13:00:12 -05:00
Stephen Boyd	f0fd248204	Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next * clk-scmi: clk: scmi: Add duty cycle ops only when duty cycle is supported * clk-qcom: (27 commits) clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller clk: qcom: Select the intended config in QCS_DISPCC_615 clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register() clk: qcom: alpha-pll: convert from round_rate() to determine_rate() clk: qcom: milos: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock Controller dt-bindings: clock: qcom: document the Glymur Global Clock Controller clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL clk: qcom: rpmh: Add support for Glymur rpmh clocks clk: qcom: Add TCSR clock driver for Glymur SoC dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs clk: qcom: dispcc-glymur: Add support for Display Clock Controller dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs ... * clk-broadcom: clk: bcm: rpi: Maximize V3D clock clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing clk: bcm: rpi: Add missing logs if firmware fails	2025-10-06 12:57:03 -05:00
Stephen Boyd	c1e102f349	Merge branches 'clk-imx', 'clk-allwinner' and 'clk-ti' into clk-next * clk-imx: clk: imx95-blk-ctl: Save/restore registers when RPM routines are called clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure * clk-allwinner: clk: sunxi-ng: add support for the A523/T527 MCU CCU clk: sunxi-ng: div: support power-of-two dividers clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock clk: sunxi-ng: sun6i-rtc: Add A523 specifics * clk-ti: clk: keystone: sci-clk: use devm_kmemdup_array() clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled	2025-10-06 12:56:54 -05:00
Stephen Boyd	3aae991cc2	Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next * clk-samsung: clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units clk: samsung: exynos990: Add missing USB clock registers to HSI0 clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC clk: samsung: Add clock PLL support for ARTPEC-8 SoC dt-bindings: clock: Add ARTPEC-8 clock controller clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes clk: samsung: pll: convert from round_rate() to determine_rate() clk: samsung: cpu: convert from round_rate() to determine_rate() clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block dt-bindings: clock: Add CAM_CSI clock macro for FSD * clk-tegra: clk: tegra: dfll: Add CVB tables for Tegra114 clk: tegra: Add DFLL DVCO reset control for Tegra114 dt-bindings: arm: tegra: Add ASUS TF101G and SL101 dt-bindings: reset: Add Tegra114 CAR header dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) dt-bindings: clock: tegra30: Add IDs for CSI pad clocks dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C * clk-amlogic: clk: amlogic: fix recent code refactoring clk: amlogic: c3-peripherals: use helper for basic composite clocks clk: amlogic: align s4 and c3 pwm clock descriptions clk: amlogic: add composite clock helpers clk: amlogic: use the common pclk definition clk: amlogic: introduce a common pclk definition clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks clk: amlogic: move PCLK definition to clkc-utils clk: amlogic: aoclk: use clkc-utils syscon probe clk: amlogic: use probe helper in mmio based controllers clk: amlogic: add probe helper for mmio based controllers clk: amlogic: drop meson-clkcee clk: amlogic: naming consistency alignment	2025-10-06 12:56:46 -05:00
Stephen Boyd	ec7336475d	Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next * clk-bindings: dt-bindings: clock: mediatek: Add power-domains property dt-bindings: clock: silabs,si5341: Add missing properties dt-bindings: clock: adi,axi-clkgen: add clock-output-names property dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding dt-bindings: clock: Convert silabs,si570 to DT schema dt-bindings: clock: Convert silabs,si5341 to DT schema dt-bindings: clock: Convert silabs,si514/544 to DT schema * clk-cleanup: clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes dt-bindings: clock: st: flexgen: remove deprecated compatibles clk: st: flexgen: remove unused compatible clk: clk-axi-clkgen: remove unneeded semicolon clk: tegra: Remove redundant semicolons clk: npcm: select CONFIG_AUXILIARY_BUS clk: remove unneeded 'fast_io' parameter in regmap_config * clk-renesas: (27 commits) clk: renesas: r9a09g05[67]: Reduce differences clk: renesas: r9a09g047: Add USB3.0 clocks/resets clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init() clk: renesas: r9a09g056: Add clock and reset entries for I3C clk: renesas: r9a09g057: Add clock and reset entries for I3C dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert() clk: renesas: rzv2h: Re-assert reset on deassert timeout clk: renesas: rzg2l: Re-assert reset on deassert timeout clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert() dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs clk: renesas: r9a09g047: Add GPT clocks and resets clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5 clk: renesas: rzv2h: remove round_rate() in favor of determine_rate() clk: renesas: rzg2l: convert from round_rate() to determine_rate() clk: renesas: r9a07g04[34]: Use tabs instead of spaces clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL clk: renesas: r9a07g044: Add MSTOP for RZ/G2L clk: renesas: r9a08g045: Add MSTOP for GPIO ... * clk-thead: clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL clk: thead: support changing DPU pixel clock rate clk: thead: add support for enabling/disabling PLLs clk: thead: Correct parent for DPU pixel clocks clk: thead: th1520-ap: fix parent of padctrl0 clock clk: thead: th1520-ap: describe gate clocks with clk_gate * clk-spacemit: clk: spacemit: fix i2s clock clk: spacemit: introduce pre-div for ddn clock dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock clk: spacemit: ccu_pll: convert from round_rate() to determine_rate() clk: spacemit: ccu_mix: convert from round_rate() to determine_rate() clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate() clk: spacemit: fix sspax_clk dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA	2025-10-06 12:56:23 -05:00
Linus Torvalds	86bcf7be1e	RISC-V updates for the v6.18 merge window (part two) Second set of RISC-V updates for the v6.18 merge window, consisting of: - Support for the RISC-V-standardized RPMI interface. RPMI is a platform management communication mechanism between OSes running on application processors, and a remote platform management processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip, mailbox, and clk changes. - Support for the RISC-V-standardized MPXY SBI extension. MPXY is a RISC-V-specific standard implementing a shared memory mailbox between S-mode operating systems (e.g., Linux) and M-mode firmware (e.g., OpenSBI). It is part of this PR since one of its use cases is to enable M-mode firmware to act as a single RPMI client for all RPMI activity on a core (including S-mode RPMI activity). Includes a mailbox driver. - Some ACPI-related updates to enable the use of RPMI and MPXY. - The addition of Linux-wide memcpy_{from,to}_le32() static inline functions, for RPMI use. - An ACPI Kconfig change to enable boot logos on any ACPI-using architecture (including RISC-V) - A RISC-V defconfig change to add GPIO keyboard and event device support, for front panel shutdown or reboot buttons This PR also includes a recent, one-line Kconfig patch from Geert to keep non-RISC-V users from being asked about building the RPMI virtual clock driver when !COMPILE_TEST. THere's nothing preventing non-RISC-V SoCs from implementing RPMI, but until some users show up, let's not annoy others with it. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAmjfNccACgkQx4+xDQu9 KkugVBAAsa9Oc6iEV1rwj1clWDrvz/bFJRxr/oH3PX0yJ4JJcZaBTydeW3fyJTJ8 CzmRClGJ18YWjapJXYhMp1AS/VfsULu2AVfUzZUqHTjVZyxgt8xFgygpI+BHIyUN vD26iKJz/JvnytRmUi7mMtS0O48nTzdMiiOmu4Ved68YMJCRJKFZw8+rWVcAzrwb FHZlIE5Fcb1PRaUDg/45Baj0nEr+NRGKDLsR1rbocbmCmRMnz3ufPTcXk128+3gC VB1rQplcMBf2RpCl7p4LW2N746hcbg/RogfpjFy7KLlnEH+Xoh2nCxcWHaiEgR9q 6JPsYBeekA54ZZsdoNBg1i5rGk3j/G1XGaV1bo7HDLTvShSByhaYrhAedQZEbw// xC3Eb7EQ6rNYUUjXiX0y5nhvl+nVlu/FmcsZmcP30ppOV4MQasTZ0zqfso23xhjL 2e06PwTqsmXDeDNDQ4ruBKrpu8tkA7ZZvjCMq1rvSWjTPObzuGBe/ENrdBUOBb2E 6UUeAGCZpQm1IxTcKHHxaIDT5ami745kqaBrXanIMKPX1JdCs7ahUqqWzC0LEgSy qB/T12bYg5O/yKXdXJuAuTHFb3TOPn6l8aNxRJve+uFwv4r1XXptdal9Yg2xoBWo EoGktm8KAp5Ndn5BntXI4xG4Ia3HOsj9YA7y4Iep4EO94JZk3Fk= =Ys1m -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Paul Walmsley: - Support for the RISC-V-standardized RPMI interface. RPMI is a platform management communication mechanism between OSes running on application processors, and a remote platform management processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip, mailbox, and clk changes. - Support for the RISC-V-standardized MPXY SBI extension. MPXY is a RISC-V-specific standard implementing a shared memory mailbox between S-mode operating systems (e.g., Linux) and M-mode firmware (e.g., OpenSBI). It is part of this PR since one of its use cases is to enable M-mode firmware to act as a single RPMI client for all RPMI activity on a core (including S-mode RPMI activity). Includes a mailbox driver. - Some ACPI-related updates to enable the use of RPMI and MPXY. - The addition of Linux-wide memcpy_{from,to}_le32() static inline functions, for RPMI use. - An ACPI Kconfig change to enable boot logos on any ACPI-using architecture (including RISC-V) - A RISC-V defconfig change to add GPIO keyboard and event device support, for front panel shutdown or reboot buttons * tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits) clk: COMMON_CLK_RPMI should depend on RISCV ACPI: support BGRT table on RISC-V MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers RISC-V: Enable GPIO keyboard and event device in RV64 defconfig irqchip/riscv-rpmi-sysmsi: Add ACPI support mailbox/riscv-sbi-mpxy: Add ACPI support irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() ACPI: RISC-V: Add RPMI System MSI to GSI mapping ACPI: RISC-V: Add support to update gsi range ACPI: RISC-V: Create interrupt controller list in sorted order ACPI: scan: Update honor list for RPMI System MSI ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args() ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop irqchip: Add driver for the RPMI system MSI service group dt-bindings: Add RPMI system MSI interrupt controller bindings dt-bindings: Add RPMI system MSI message proxy bindings clk: Add clock driver for the RISC-V RPMI clock service group dt-bindings: clock: Add RPMI clock service controller bindings dt-bindings: clock: Add RPMI clock service message proxy bindings mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver ...	2025-10-04 10:36:22 -07:00
Linus Torvalds	d955299b5c	soc: build fix for 6.18 One commit for the dt bindings was missing from the dt branch, this one is already pending in the clk tree that contains the corresponding device driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmje970ACgkQYKtH/8kJ UieWdQ/9EKbkRWleVJ9Cuz4oX1vOv6TKISkboqb4b7ZFh56AKV/PeVanAiy+wsaI tnVuiIi8aVBiPxddi4xVY4+RaRp0ZjaOEDYhxvJ1huc1p7i0I4viHo0G4MYflgbM Db+yjqaSGMfpKEcWJSmtVt1qZF89t/8ZE0vlPxQ0Z+wAqTEX3b6zofI1UnAiFtGH vgvXcW6798n+czaZulE98tC+oAWlrbyruVh0SC8q7UfchCrCFsJQYSkw9GecmoaR RS48mM+JHdKxgHsNXR5qbWkktHcsvC8TJ8Jscxqn71cJYB1TldGEdBAEpfxlVkYD rWbCr6mr6XHg0N/5yVF0n5VwLESGJeUhRsFMiBUHfq9HgWred6iwP/pu6LQGWaKE fKUDlM/ukTzuyVaG1Ipxr9wbecpIHlETmaVSBZMrBHYj0hSeDvV5qVkKHORYX/QN OdtIcIsoez7VReqhnHIBy/MNRbLrZZCkEscX6H2i41d7pXDmFdBZZIGTN7W9kuNx DEvPVJtXznLxTIOawftoB1AG/PBUaa8zLZ6w/7DmFXx4rRSztyBmYV14bE86JTwF y0Hux3DHaAYtj4qI25awwzMLdNyMDc7BQry9fF/5wdZYBzAHbbv1OEZ/J+Fm6YNn q4ERE7NpB8TVG1DAFuKrzI4OsFxHzurco2snso5yY8OYvDn/BMs= =DlPR -----END PGP SIGNATURE----- Merge tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC build fix from Arnd Bergmann: "One commit for the dt bindings was missing from the dt branch, this one is already pending in the clk tree that contains the corresponding device driver" * tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: dt-bindings: clock: Add ARTPEC-8 clock controller	2025-10-03 19:36:39 -07:00
Linus Torvalds	38057e3236	soc: driver updates for 6.18 Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdpaoACgkQmmx57+YA GNnBXA//QgmFXYGG7QfB825mt0orKZxpfpLcwvqO7hkWgbXtl7Gokw2lGYN6bwLu zvY4MQ/bVoZ8R5uTVmuaSHBRsttSen8mBf+V0vzsBM/DRRVxvIN/7TESrY3J7Dtx J5syHKIBiUtdkDebWWC6jIElczIBItsd03Ln4Xjjt8Vas5YOO4n44zFrPo+FwlN/ I6D2K86AiNZTtUCDMtB6VfJ6YtjYBWcWnJm7FXw/vE8FAXdZUnNWnZ8hbdQ5GaME JZGepUhONaOMUoGNZNaDGw511RdPhYzPjj9rCsIx2qdsRO9/4tJ8ccpW2aUMYh8c nA6w8Hj8jCwco6aYYrDUDV9uRtURDrmyJgTJBNLU05e/L+MuJ3IZNlzHFWlsxIAE vhyTdmg/P04ClQyixCl67IH/66F/0smX9C+1761LrD7GTdfR92KPl5W6q+DPBg/x yf+s2p3+f7ItV5XobKOrbf3w0xazeDb5o/EK8BufMx9vSe9bpzJ0gOf0CmNXEpyZ owAhbh6wXX1YwPcyA9LHv6gthyJwc/3fLu49ggMZP2rU01ccKOYn9H0cr7C8NVmy wEpJR0lp5aSw2oRkPkxB6sFmUohcpr8/OXGGJuvCXkYsUY1BEup4lewvbIWK4WoE c84kbbaHsjgFhe3IRlQw3G4KLYQT3jRtF7fH+gPx556BcI6K+lg= =mcZR -----END PGP SIGNATURE----- Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0" * tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits) soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu() soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Change GPIO driver to a proper platform driver tee: fix register_shm_helper() pmdomain: apple: Add "apple,t8103-pmgr-pwrstate" dt-bindings: spmi: Add Apple A11 and T2 compatible serial: qcom-geni: Load UART qup Firmware from linux side spi: geni-qcom: Load spi qup Firmware from linux side i2c: qcom-geni: Load i2c qup Firmware from linux side soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem soc: qcom: geni-se: Cleanup register defines and update copyright dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Documentation: tee: Add Qualcomm TEE driver tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl tee: qcom: add primordial object tee: add Qualcomm TEE driver tee: increase TEE_MAX_ARG_SIZE to 4096 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF tee: add close_context to TEE driver operation ...	2025-10-01 17:32:51 -07:00
Linus Torvalds	0f048c878e	soc: dt changes for 6.18 There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdn9oACgkQmmx57+YA GNnHwg//RBWBI+6Wj8DP9vkz+0/UKNNPVPZNIwL3+X9zWBnQ/nRDj8U6Z8q8uqeP 42M+kWTt6WwgHLYItcKa7o1YTdkq1cNuxSt4QIliWxcy58RnsJUbfYErmB6ouM3I yUbJNJdarQAkewypsZ6TYA1z/fMPK8uWLSCvEpIsfxMn6GV9bKOaCSDCM1htDwYV /CXiJEP4ytlpOXz1JkrQ8yljiEX5mBTe4Gfc70FKS+9UMdOwx74od8cUwmptw2ej g/LiDPbKWJ3OLUeUBxZiJW6PDEH0MjBmXTamZo56cniSP3ZJ5H4T//ZEqYspYR+f Dcj9AjtT0QHOpLnrTPsTmXHme/oGodmgEXuooSJxEEfFSv0fxfjNXHOR6gUoSSLz cCe6wcu4nBLmAK0QqI8oMJO4Ey6NE74Kz4kJwad2Oe7Aee7eCnjX6ZwyB4sJvBtf ii401i3GYdOWV0DkgAAqREMNPbUZH9WWdCYd/izI3fO1TooBptaPWRo60rrIpx3M u1ntYyj1PFrnYadESATgmmj+3PE7mRaL6prvCtI19vt12qQONDVzoFgzjxh+I7tV 8PQTb3QbciZuMiX36GNgt5OLz9KqE31xtZtxo/+a8CNOzuZu8UwonpkMkkrwGMRU /3jjZvuiRBh2xW32yqszAFw0JII+2cGPQUG5dcoijcEqWorKMto= =9OtD -----END PGP SIGNATURE----- Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC dt updates from Arnd Bergmann: "There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation" * tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits) arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node ARM: dts: microchip: sam9x7: Add qspi controller arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes arm64: dts: allwinner: h313: Add Amediatech X96Q dt-bindings: arm: sunxi: Add Amediatech X96Q arm64: dts: apple: t8015: Add SPMI node arm64: dts: apple: t8012: Add SPMI node arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT arm64: dts: rockchip: update pinctrl names for Radxa E52C arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C arm64: dts: apple: Add J474s, J475c and J475d device trees arm64: dts: apple: Add J414 and J416 Macbook Pro device trees arm64: dts: apple: Add initial t6020/t6021/t6022 DTs ...	2025-10-01 17:19:38 -07:00
Anup Patel	b385830290	dt-bindings: clock: Add RPMI clock service controller bindings Add device tree bindings for the RPMI clock service group based controller for the supervisor software. The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-10-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>	2025-09-25 13:16:42 -06:00
Anup Patel	54e184f0f5	dt-bindings: clock: Add RPMI clock service message proxy bindings Add device tree bindings for the RPMI clock service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20250818040920.272664-9-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org>	2025-09-25 13:16:13 -06:00
Arnd Bergmann	17752efeca	Allwinner Device Tree changes for 6.18 This tag contains two DT binding header changes that are shared with the clk tree. In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. 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In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. Default audio routing for these two boards (to be used with the addon) were added to complement the overlay. * tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami SoM riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing ARM: dts: allwinner: orangepi-zero: Add default audio routing arm64: dts: allwinner: a523: Add NPU device node arm64: dts: allwinner: a523: Add MCU PRCM CCU node dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add LEDs Link: https://lore.kernel.org/r/aMrtuZg8HlR--TAt@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-23 22:17:56 +02:00
Yao Zi	793e6b7480	dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible Document the clock controller shipped in Loongson-2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, LS2K0300 requires a 120MHz external clock input. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 12:48:30 -07:00
André Draszik	b92ef17f0c	dt-bindings: clock: samsung,s2mps11: add s2mpg10 The Samsung S2MPG10 clock controller is similar to the existing clock controllers supported by this binding. Register offsets / layout are slightly different, so it needs its own compatible. Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:43:16 -07:00
Gabriel Fernandez	099760708a	dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings - drop minItems from access-controllers - remove rcc label from example - fixes typos - remove double '::' from 'See also::' Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:31:57 -07:00
Gabriel Fernandez	49f6c8b74d	dt-bindings: stm32: add STM32MP21 clocks and reset bindings Adds clock and reset binding entries for STM32MP21 SoC family. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:31:55 -07:00
Raphael Gallais-Pou	b52297f6eb	dt-bindings: clock: st: flexgen: remove deprecated compatibles st/stih407-clock.dtsi file has been removed in commit 65322c1daf51 ("clk: st: flexgen: remove unused compatible"). This file has three compatibles which are now dangling. Remove them from documentation. Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 09:52:31 -07:00
Laura Nao	dd240e95f1	dt-bindings: clock: mediatek: Describe MT8196 clock controllers Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 09:35:59 -07:00
Julien Massot	ac28c75986	dt-bindings: clock: mediatek: Add power-domains property The mt8183-mfgcfg node uses a power domain in its device tree node. To prevent schema validation warnings, add the optional `power-domains` property to the binding schema for mediatek syscon clocks. Fixes: `1781f2c461` ("arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-19 22:45:07 -07:00
Duje Mihanović	5bcf9e1d0a	dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu Add required syscon compatible and #power-domain-cells to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. Device tree bindings for said power domains are also added. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>	2025-09-17 16:09:14 +02:00
Rob Herring (Arm)	7c85e4da8c	dt-bindings: clock: silabs,si5341: Add missing properties Add "clock-output-names" which is a standard property for clock providers. Add the "always-on" boolean property which was undocumented, but already in use for some time. The flag prevents a clock output from being disabled. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-16 17:47:12 -07:00
Janne Grunau	ff0b47ab71	dt-bindings: clock: apple,nco: Add t6020-nco compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,nco" anymore [1]. Use "apple,t8103-nco" as base compatible as it is the SoC the driver and bindings were written for. The block found on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-nco" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>	2025-09-14 21:51:01 +02:00
Chen-Yu Tsai	0f610e650d	dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>	2025-09-13 13:49:09 +08:00
Denzeel Oliva	43bd82eb33	dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units Add clock management unit bindings for PERIC0 and PERIC1 blocks which provide clocks for USI, I2C and UART peripherals. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-09-07 11:10:55 +02:00
Bjorn Andersson	154691e7c9	Merge branch '20250903-msm8937-v9-1-a097c91c5801@mainlining.org' into clk-for-6.18 Merge the MSM8937 global clock controller binding through a topic branch to allow merging the constants into the DeviceTree branch as well.	2025-09-04 08:38:00 -05:00
Barnabás Czémán	4d32c1f66a	dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller Add device tree bindings for the global clock controller on Qualcomm MSM8937 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250903-msm8937-v9-1-a097c91c5801@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-04 08:37:53 -05:00
Taniya Das	ee2d967030	dt-bindings: clock: qcom: document the Glymur Global Clock Controller Add device tree bindings for global clock controller on Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:15:43 -05:00
Taniya Das	ae5b84788e	dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe and USB. Add this to the TCSR clock controller binding together with identifiers for the clocks. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-2-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:14:44 -05:00
Taniya Das	f9b007a96a	dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs Add bindings and update documentation compatible for RPMh clock controller on Glymur SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-1-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:14:44 -05:00
Taniya Das	781c118c3e	dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC Add the device tree bindings for the display clock controller which are required on Qualcomm Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com [bjorn: Dropped unnecessary include in DT example] Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 17:13:16 -05:00
Hakyeong Kim	91f98de423	dt-bindings: clock: Add ARTPEC-8 clock controller Add dt-schema for Axis ARTPEC-8 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-08-31 15:22:10 +02:00
David Lechner	6793ca9a43	dt-bindings: clock: adi,axi-clkgen: add clock-output-names property Add an optional `clock-output-names` property to the ADI AXI Clock Generator binding. This is already being used in the Linux driver and real-world dtbs, so we should document it to allow for correct binding validation. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20250811-dt-bindings-clk-axi-clkgen-add-clock-output-names-property-v1-1-f02727736aa7@baylibre.com Reviewed-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:41:32 -07:00
Rob Herring (Arm)	bedeb73fb9	dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding The fujitsu,mb86s70-crg11 binding is unused. The driver for it was removed in 2017. It's not used for Synquacer DT either like some other mb86s70 bindings are. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804175304.3423965-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:28:20 -07:00
Rob Herring (Arm)	7513cc3914	dt-bindings: clock: Convert silabs,si570 to DT schema Convert the Silicon Labs SI570 binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804222010.4082782-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:02:06 -07:00
Rob Herring (Arm)	b02011c8c6	dt-bindings: clock: Convert silabs,si5341 to DT schema Convert the Silicon Labs SI5341 binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804222034.4083410-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:01:37 -07:00
Rob Herring (Arm)	d903f5c60a	dt-bindings: clock: Convert silabs,si514/544 to DT schema Convert the Silicon Labs SI514 and SI544 bindings to DT schema format. Combine the bindings into a single schema as they are the same. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250804222042.4083656-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-08-13 11:01:16 -07:00
Satya Priya Kakitapalli	be477c3924	dt-bindings: clock: qcom,videocc: Add sc8180x compatible The sc8180x video clock controller block is identical to that of sm8150. Add a new compatible string for sc8180x videocc and use sm8150 as fallback. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250710-sc8180x-videocc-dt-v4-1-07a9d9d5e0e6@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-08-11 22:56:50 -05:00
Sricharan Ramabadhran	c17ccefb61	dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-08-11 10:05:20 -05:00
Linus Torvalds	2d945dde7f	This is the usual collection of primarily clk driver updates. The big part of the diff is all the new Qualcomm clk drivers added for a few SoCs they're working on. The other two vendors with significant work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some new SoCs while Amlogic is starting a significant refactoring to simplify their code. The core framework gained a pair of helpers to get the 'struct device' or 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit tests were added for these simple helpers as well. Beyond that core change there are lots of little fixes throughout the clk drivers for the stuff we see every day, wrong clk driver data that affects tree topology or supported frequencies, etc. They're not found until the clks are actually used by some consumer device driver. New Drivers: - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the Qualcomm Milos SoC - Camera, display, GPU, and video clock controllers for Qualcomm QCS615 - Video clock controller driver for Qualcomm SM6350 - Camera clock controller driver for Qualcomm SC8180X - I3C clocks and resets on Renesas RZ/G3E - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/V2H(P) and RZ/V2N - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P) - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H - Ethernet clocks and resets on Renesas RZ/G3E - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas RZ/V2N Updates: - Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers - Replace round_rate() with determine_rate() in various clk drivers - Convert clk DT bindings to DT schema format for DT validation - Various clk driver cleanups and refactorings from static analysis tools and possibly real humans - A lot of little fixes here and there to things like clk tree topology, missing frequencies, flagging clks as critical, etc. The full details are in the commits and sub-tree merge logs -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmiLljkUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSVR1BAAm5hnFdYvNX/AYK+bNNbb/YkbveGr wxrZFjd/1QEZii7UBBOENLjvbrxT4N93TGuwuHOy+iz53X4mWg1BST0RENtmks9v rys7suEkDVA7KoDEbcvbUhLbLObEQvr3sxurl2mvq563y02hkJ+rt3kDqdCn/MFK fUfqZ79oPLaMULy3XwFyrEQEcxqQTX7i+j1atCB4TPmBSu3R5WMsCS+IVKPCuxCF qcan5hCXakv4gBE/jF9x/u28j0m9v16uB2O/7sH3uDzHo/FxShBmC53Bj2Mtaf2w lSKhEngCAMItU2LtruO2szpsmoy9EZTIqzELr5GJGXFDQDHiTzcigRtD5MCWjdG1 aapgWs47Yslh0M+d8Im81hu1YaLGDuoY7QiOVMN/htn0nPEozU1farKJbD3/gj9U C6648EXYa/dqDBRRHeqLi4n1RK0Fzb15VvsanKn1nLy+cOvzNI4bpJjEJlUQjZMN 8MzvzBgLNsydDQC5I8JAPPK2Fcdpk3KpchphZrXLZY8iRco5kvx1mRjh90Lvr8N8 rmpUC6p1BdEIGhL+NAh7qCz9DOKfsaFr13tHpqD/PItzfHIyd7mss+7GSD6WCa/b MduE9172Uq0mY8ZnWe0vV7/+s9GE7oTsxdMC6oF5yTXRIpog7evkUqNyXhpNTxgS C2DLCDhaqpHI28c= =S+dB -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This is the usual collection of primarily clk driver updates. The big part of the diff is all the new Qualcomm clk drivers added for a few SoCs they're working on. The other two vendors with significant work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some new SoCs while Amlogic is starting a significant refactoring to simplify their code. The core framework gained a pair of helpers to get the 'struct device' or 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit tests were added for these simple helpers as well. Beyond that core change there are lots of little fixes throughout the clk drivers for the stuff we see every day, wrong clk driver data that affects tree topology or supported frequencies, etc. They're not found until the clks are actually used by some consumer device driver. New Drivers: - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the Qualcomm Milos SoC - Camera, display, GPU, and video clock controllers for Qualcomm QCS615 - Video clock controller driver for Qualcomm SM6350 - Camera clock controller driver for Qualcomm SC8180X - I3C clocks and resets on Renesas RZ/G3E - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/V2H(P) and RZ/V2N - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P) - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H - Ethernet clocks and resets on Renesas RZ/G3E - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas RZ/V2N Updates: - Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers - Replace round_rate() with determine_rate() in various clk drivers - Convert clk DT bindings to DT schema format for DT validation - Various clk driver cleanups and refactorings from static analysis tools and possibly real humans - A lot of little fixes here and there to things like clk tree topology, missing frequencies, flagging clks as critical, etc" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: spacemit: ccu_pll: fix error return value in recalc_rate callback clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls ...	2025-07-31 13:36:27 -07:00
Linus Torvalds	24e5c3241a	MFD for v6.17 - New Support & Features * Add extensive support for the Analog Devices ADP5589 I/O expander, including core MFD, GPIO, PWM, and a new keypad matrix input driver. This also adds support for handling various events including GPI, keypad, reset and unlock ev ents. * Add support for the TI TPS652G1 PMIC, a stripped-down version of the TPS65224, including core MFD, PFSM, pinctrl, and GPIO support. * Add support for the Apple Silicon System Management Controller (SMC), including the core MFD driver which handles the RTKit-based protocol, a new GPIO driver for PMU GPIOs, and a new reboot/power-off driver. - Improvements & Fixes * Dynamically add ADP5585 sub-devices based on device tree properties. * Move ADP5585 oscillator control from the child PWM driver to the main MFD driver to better handle shared resources. * Add support for a hardware reset pin and VDD regulator to the ADP5585 driver. * Update the TPS65219 MFD cell's GPIO compatible string for the TPS65214 to reflect hardware capabilities correctly. * Separate the ChromeOS EC charge-control probing from the USB-PD subsystem, allowing it to probe independently based on the dedicated EC_FEATURE_CHARGER. * Fix an interrupt naming typo in the MT6370 driver. * Fix RK806 PMIC reset behavior by allowing the reset mode to be customized via a new device tree property. * Fix AXP20X regulator cell ID conflicts for secondary PMICs on boards without an IRQ line connected. * Fix MT6397 keypad sub-device creation to use specific names instead of a generic one, ensuring correct driver binding. * Fix a build warning in the stm32-timers driver by adding a missing include for export.h. - Cleanups & Refactoring * Refactor the ADP5585 driver to simplify how regmap defaults are handled, making it easier to add new chip variants. * Introduce per-chip register map structures for the ADP5585/ADP5589 family to handle differences between the devices. * Convert several drivers to use dev_fwnode() instead of of_fwnode_handle(). * Make various static structures const in the cs40l50, rohm-bd71828, tps65219, and twl6040 drivers. * Remove redundant pm_runtime_mark_last_busy() calls from several drivers. * Alphabetize Kconfig entries for Cirrus Logic and Maxim drivers. * Remove unused fields from the 'tps65219' struct. * Update several MFD-related headers to follow the 'Include What You Use' (IWYU) principle. - Removals * Remove the old, platform-data-based adp5589-keys input driver, which is now superseded by the new MFD-based adp5585-keys driver. * Remove the unused twl6030_mmc_card_detect() functions and associated header declarations. * Remove the now unused pcf50633/core.h header file. * Remove the fsl,imx8qxp-csr device tree binding, which was being used incorrectly. - Device Tree Bindings Updates * Add support for the Analog Devices ADP5589 I/O expander to the adi,adp5585.yaml binding. * Add new properties to the adi,adp5585.yaml binding for input events, including keypad pins, unlock events, and reset events. * Add a reset-gpios property to the adi,adp5585.yaml binding. * Add the TI TPS652G1 PMIC to the ti,tps6594.yaml binding. * Add new bindings for the Apple Mac System Management Controller (SMC) and its sub-devices: apple,smc.yaml, apple,smc-gpio.yaml, and apple,smc-reboot.yaml. * Convert the Freescale MXS LRADC binding (mxs-lradc) to YAML schema format. * Convert and combine the NXP LPC1850 CREG, DMAMUX, and USB OTG PHY bindings into a single YAML schema file. * Convert the TI TPS65910 binding to YAML schema format. * Add a comment to the samsung,s2mps11.yaml binding to clarify the use of 'oneOf' for interrupt properties. * Add the rockchip,reset-mode property to the rockchip,rk806.yaml binding to allow customization of the PMIC's reset behavior. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAmiKNQgACgkQUa+KL4f8 d2HXOw//bquorwKRgOmi85ZMFNVowywRiUfEYUmKKkjlaK/mfUwmiPxlzREWmR0p paAvlL2bKHYsEt/3gh8l8Q8cIo3ELlhSHmECG22Pz8+msq06n7vZ/fpzXhjqdHLR PIyA7oJv2kBE+glmRiDL2yRGQU42i/Mmq5vo9eJD49aOL8nOzNk17N7fFp9aDGQ6 C+MDrvaFV4jYjMH8/A/pBh9KaPwzvuIvNvMFeC4F5Zjpym6X1gClDEVgQvSHsyz0 NyT2qpHG6KkUVNhm8dBcYUxdAbpZLjWiPpqfe4KzWflZ9kUjAow5z2NhiwtDxZuG DVICs64O1YvoqZXIazptYEIHLmDks1URdADd/efJDbBKm12G2DgRJtbLVFW/hWUz g7itYgJk3cpRoFUVjiniLvy+Nlp67XfN5qADNiHnRJpk4DCW5sNqPp5AHFhhD8hC 5t6EyOYaO7U1I+0ZgWvsSaCv+D/r4pjcUBalUB1Wh7QcEWOXVJgFmkggbXEPEzob FtM6GCFcIr+yrrqGL3o6DNgQmuiAenuIjGs9jk6on+0zUmDvgvwbERpktweEofki anW4jtm0tDKSP9qBFEhGC8dOygFU/jnXqaHGsXeEHOv5zb5mSk/dL+W/QHqmG2QO 08UEh02sfWiUE8hwL3vZ/cXvR7SfgK00nBC3g8QfEWF1AHplGE0= =YYgL -----END PGP SIGNATURE----- Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Support & Features: - Add extensive support for the Analog Devices ADP5589 I/O expander, including core MFD, GPIO, PWM, and a new keypad matrix input driver. This also adds support for handling various events including GPI, keypad, reset and unlock ev ents - Add support for the TI TPS652G1 PMIC, a stripped-down version of the TPS65224, including core MFD, PFSM, pinctrl, and GPIO support - Add support for the Apple Silicon System Management Controller (SMC), including the core MFD driver which handles the RTKit-based protocol, a new GPIO driver for PMU GPIOs, and a new reboot/power-off driver. Improvements & Fixes: - Dynamically add ADP5585 sub-devices based on device tree properties - Move ADP5585 oscillator control from the child PWM driver to the main MFD driver to better handle shared resources - Add support for a hardware reset pin and VDD regulator to the ADP5585 driver - Update the TPS65219 MFD cell's GPIO compatible string for the TPS65214 to reflect hardware capabilities correctly - Separate the ChromeOS EC charge-control probing from the USB-PD subsystem, allowing it to probe independently based on the dedicated EC_FEATURE_CHARGER - Fix an interrupt naming typo in the MT6370 driver - Fix RK806 PMIC reset behavior by allowing the reset mode to be customized via a new device tree property - Fix AXP20X regulator cell ID conflicts for secondary PMICs on boards without an IRQ line connected - Fix MT6397 keypad sub-device creation to use specific names instead of a generic one, ensuring correct driver binding - Fix a build warning in the stm32-timers driver by adding a missing include for export.h. Cleanups & Refactoring: - Refactor the ADP5585 driver to simplify how regmap defaults are handled, making it easier to add new chip variants - Introduce per-chip register map structures for the ADP5585/ADP5589 family to handle differences between the devices - Convert several drivers to use dev_fwnode() instead of of_fwnode_handle() - Make various static structures const in the cs40l50, rohm-bd71828, tps65219, and twl6040 drivers - Remove redundant pm_runtime_mark_last_busy() calls from several drivers - Alphabetize Kconfig entries for Cirrus Logic and Maxim drivers - Remove unused fields from the 'tps65219' struct - Update several MFD-related headers to follow the 'Include What You Use' (IWYU) principle. Removals: - Remove the old, platform-data-based adp5589-keys input driver, which is now superseded by the new MFD-based adp5585-keys driver - Remove the unused twl6030_mmc_card_detect() functions and associated header declarations - Remove the now unused pcf50633/core.h header file - Remove the fsl,imx8qxp-csr device tree binding, which was being used incorrectly. Device Tree Bindings Updates: - Add support for the Analog Devices ADP5589 I/O expander to the adi,adp5585.yaml binding - Add new properties to the adi,adp5585.yaml binding for input events, including keypad pins, unlock events, and reset events - Add a reset-gpios property to the adi,adp5585.yaml binding - Add the TI TPS652G1 PMIC to the ti,tps6594.yaml binding - Add new bindings for the Apple Mac System Management Controller (SMC) and its sub-devices: apple,smc.yaml, apple,smc-gpio.yaml, and apple,smc-reboot.yaml - Convert the Freescale MXS LRADC binding (mxs-lradc) to YAML schema format - Convert and combine the NXP LPC1850 CREG, DMAMUX, and USB OTG PHY bindings into a single YAML schema file - Convert the TI TPS65910 binding to YAML schema format - Add a comment to the samsung,s2mps11.yaml binding to clarify the use of 'oneOf' for interrupt properties - Add the rockchip,reset-mode property to the rockchip,rk806.yaml binding to allow customization of the PMIC's reset behavior" * tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (28 commits) mfd: dt-bindings: Convert TPS65910 to DT schema mfd: Minor Cirrus/Maxim Kconfig order fixes mfd: Remove redundant pm_runtime_mark_last_busy() calls mfd: mt6397: Do not use generic name for keypad sub-devices mfd: axp20x: Set explicit ID for regulator cell if no IRQ line is present mfd: mt6370: Fix the interrupt naming typo mfd: rk8xx-core: Allow to customize RK806 reset mode dt-bindings: mfd: rk806: Allow to customize PMIC reset mode mfd: syscon: atmel-smc: Don't use "proxy" headers mfd: madera: Don't use "proxy" headers mfd: wm8350-core: Don't use "proxy" headers dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties mfd: davinci_voicecodec: Don't use "proxy" headers mfd: pcf50633: Remove the header file core.h mfd: tps65219: Remove another unused field from 'struct tps65219' mfd: tps65219: Remove an unused field from 'struct tps65219' mfd: tps65219: Constify struct regmap_irq_sub_irq_map and tps65219_chip_data mfd: rohm-bd71828: Constify some structures dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation mfd: axp20x: Set explicit ID for AXP313 regulator ...	2025-07-31 11:50:25 -07:00
Linus Torvalds	f1aa129d80	DT updates for ralink, mobileye and ralink Clean up of mc146818 usage Speed up delay calibration for CPS Other cleanups and fixes -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmiKJdMaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHCJYA/9HzXnlEbszpTAQl/1BEYY sr0AQDjJCnDKep9/nnWilAEZrBRNJ6wkv64MIzEN59gpDc5EKbZrTA8AJkwr34Rt TJqnpaeAGyErJwc/1VZvlDUUlsySOd5sAhQ7v2HdhSn4txMAbEY5SXW1EfmfFx5q Uj9Ku6Llr8xP29QA75CG2uOfS/wxc0zPio9ykxZxnvk4SL7QqzCaSMYJndJ2GqKg GTFlbgkpFjlAidJuflijM4ZN4oE7PG6ZhFUSJOBpdML4lzbEsx5e9zWxfVFjh8Db ZFOuIlpvwzn4+nAc7V3ywc5+7YoCrrBL6HbR5VIy4VAz0ktjp5sV6OBFi8izDIEe 2ncOJXS/Dc0NjY4GBagigwlB1r85+kW2bZVCp2naSXNnUJvqjDW/kRVw/bLVIWMv AiWxNJMYFAvmK28i52PRMu2i8HeAy3jaYj26Gy9cBAayNRs807y21rKkutO1x65h 3cQTjTzOB9p1zCs3yOPg9s+oOz/okpnLfQFt5fty1mVzHAn7lV9JLArwdW36mLO8 6GeQzxlKrgQZyBvCdtzDCNncCnp/q2rLPLbiZslJmAZFV76wkkLzNpSR2LUl5NYx /ShFcQQNVSrfuMk4tWS8zeFdaTMSBDSDM+gdx9yQBrA+tZVgqhBz3GtsjXM84HOj HDBBLtmJ6CFJeY2b3k7odqo= =H2nx -----END PGP SIGNATURE----- Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - DT updates for ralink, mobileye and atheros/qualcomm - Clean up of mc146818 usage - Speed up delay calibration for CPS - Other cleanups and fixes * tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (50 commits) MIPS: Don't use %pK through printk MIPS: Update Joshua Kinard's e-mail address MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller MIPS: mm: tlb-r4k: Uniquify TLB entries on init MIPS: SGI-IP27: Delete an unnecessary check before kfree() in hub_domain_free() mips/malta,loongson2ef: use generic mc146818_get_time function mips: remove redundant macro mc146818_decode_year mips/mach-rm: remove custom mc146818rtc.h file mips: remove unused function mc146818_set_rtc_mmss MIPS: CPS: Optimise delay CPU calibration for SMP MIPS: CPS: Improve mips_cps_first_online_in_cluster() MIPS: disable MMID when not supported by the hardware MIPS: eyeq5_defconfig: add I2C subsystem, driver and temp sensor driver MIPS: eyeq5_defconfig: add GPIO subsystem & driver MIPS: mobileye: eyeq5: add two GPIO bank nodes MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor MIPS: mobileye: eyeq5: add 5 I2C controller nodes MIPS: eyeq5_defconfig: Update for v6.16-rc1 MIPS: vpe-mt: add missing prototypes for vpe_{alloc,start,stop,free} mips: boot: use 'targets' instead of extra-y in Makefile ...	2025-07-31 11:08:55 -07:00
Stephen Boyd	64c21f253a	Merge branch 'clk-fixes' into clk-next Resolve conflicts with i.MX95 changes `88768d6f8c` ("clk: imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx and `aacc875a44` ("clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data") in clk-fixes. * clk-fixes: clk: sunxi-ng: v3s: Fix TCON clock parents clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name clk: sunxi-ng: v3s: Fix CSI SCLK clock name dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data clk: scmi: Handle case where child clocks are initialized before their parents clk: sunxi-ng: a523: Mark MBUS clock as critical	2025-07-31 09:10:06 -07:00
Stephen Boyd	c30cc9ffc1	Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next * clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 132MHz * clk-thead: clk: thead: th1520-ap: Describe mux clocks with clk_mux clk: thead: th1520-ap: Correctly refer the parent of osc_12m clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED * clk-microchip: clk: at91: sam9x7: update pll clk ranges * clk-imx: MAINTAINERS: Update i.MX Clock Entry clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR clk: imx95-blk-ctl: Rename lvds and displaymix csr blk clk: imx95-blk-ctl: Fix synchronous abort dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data * clk-qcom: (65 commits) dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom: Remove double colon from description clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos dt-bindings: clock: qcom: document the Milos Video Clock Controller clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos dt-bindings: clock: qcom: document the Milos GPU Clock Controller clk: qcom: Add Display Clock controller (DISPCC) driver for Milos dt-bindings: clock: qcom: document the Milos Display Clock Controller clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos dt-bindings: clock: qcom: document the Milos Camera Clock Controller clk: qcom: Add Global Clock controller (GCC) driver for Milos dt-bindings: clock: qcom: document the Milos Global Clock Controller clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe clk: qcom: gcc-x1e80100: Add missing video resets dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC ...	2025-07-29 15:19:17 -07:00
Stephen Boyd	e3abdd1870	Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next * clk-renesas: (42 commits) clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs clk: renesas: r9a09g057: Add XSPI clock/reset clk: renesas: r9a09g056: Add XSPI clock/reset clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting clk: renesas: r9a09g057: Add support for xspi mux and divider clk: renesas: r9a09g056: Add support for xspi mux and divider clk: renesas: r9a09g077: Add RIIC module clocks clk: renesas: r9a09g077: Add PLL2 and SDHI clock support clk: renesas: rzv2h: Drop redundant base pointer from pll_clk clk: renesas: r9a09g057: Add entries for the RSPIs dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock clk: renesas: rzv2h: Add missing include file clk: renesas: rzv2h: Use devm_kmemdup_array() clk: renesas: Add CPG/MSSR support to RZ/N2H SoC clk: renesas: r9a09g077: Add PCLKL core clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID ... * clk-samsung: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD * clk-spacemit: clk: spacemit: ccu_pll: fix error return value in recalc_rate callback reset: spacemit: add support for SpacemiT CCU resets clk: spacemit: mark K1 pll1_d8 as critical clk: spacemit: define three reset-only CCUs clk: spacemit: set up reset auxiliary devices soc: spacemit: create a header for clock/reset registers dt-bindings: soc: spacemit: define spacemit,k1-ccu resets * clk-allwinner: clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate() clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll clk: sunxi-ng: v3s: Fix de clock definition clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset * clk-amlogic: clk: amlogic: s4: remove unused data clk: amlogic: drop clk_regmap tables clk: amlogic: get regmap with clk_regmap_init clk: amlogic: remove unnecessary headers clk: amlogic: axg-audio: use the auxiliary reset driver	2025-07-29 15:18:33 -07:00
Linus Torvalds	115e74a29b	soc: dt changes for 6.17 There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now. - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it. There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042. - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95. - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm. Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiEp54ACgkQmmx57+YA GNmE+BAAvGeMkjz05rl3kSeNWCxm3WlQtrVAS3CGxXlmuB3GH4svAYO7ZFqnA1Lq oLKfvH9TXQgNTRlRV2bKSVCcgsvMdRukqvaNIp+9jOHKkdapgGUHr7XALZCITODp Ey2YPOKVi3aY2tEqUiuV09oLBFYBB5ldSuPG7SnFHNS0+IWlqqFDdQhrFXfBNf02 Upzca6J96A6TRG7Rq+VD4127QLapNDLm1S2R+3PbEapz/v/XNxQEtigWl+E88N5L ju1pXu9f93w1EeQla6rN6S8RKI6Ed0kVt0I7mtwJ5KrPs9jzQwZZc5t7z+0HVyaK o5ldagj7nEVlth2Fc2+E67DnxB6Xe8BkTcNspnS6oWscqvyYo2WCjYOBQcTocU5m ej4urbS80z2bGbew9zp/ZCBJjmqOdXW/B8z9mokg1u/aktHmAiOWXnFZtws5+rBM It/GjP4b8MzS3JYq1oNSCUV2KpYF9hzfSg1Td7DEvyhhvSgeJyXNsc4OozZzTCv6 bO3h1PBW6JBWVupRIAz7IrqseAsCabCMfIHduvtYWJieRzv24z1Dfv8p73v3iknN qpOOyGOvWdPH0u04LAbovYdJfGrR/IN04wOYGcH0uB/bufW5qCKBb9AEAvxvTaJR Jg1Q7ac/+TVJSFwBQJresw4WdFPHVKVwd2s382Q5hKtx3B5Cn4Y= =0VBL -----END PGP SIGNATURE----- Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC devicetree updates from Arnd Bergmann: "There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042 - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95 - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5" * tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ...	2025-07-29 11:04:52 -07:00
Frank Li	17a6d7cece	dt-bindings: clock: convert lpc1850-cgu.txt to yaml format Convert lpc1850-cgu.txt to yaml format. Additional changes: - remove extra clock source nodes in example. - remove clock consumer in example. - remove clock-output-names and clock-clock-indices from required list to match existed dts. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250606162410.1361169-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:26:01 -07:00
Rob Herring (Arm)	3849ceec49	dt-bindings: clock: Convert qca,ath79-pll to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232625.3700213-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:19:46 -07:00
Rob Herring (Arm)	71b80a3365	dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232637.3700584-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:19:42 -07:00
Rob Herring (Arm)	f2cb67d73a	dt-bindings: clock: Convert moxa,moxart-clock to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232644.3700781-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:19:37 -07:00
Rob Herring (Arm)	ce2930aefb	dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232652.3701007-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:19:32 -07:00
Rob Herring (Arm)	1a25e13de6	dt-bindings: clock: Convert maxim,max9485 to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232658.3701225-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 14:11:26 -07:00
Rob Herring (Arm)	1eef76f463	dt-bindings: clock: Convert qcom,krait-cc to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250630232617.3699954-1-robh@kernel.org [sboyd@kernel.org: Update to korg] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 12:30:13 -07:00
Luca Weiss	e51c16f9ee	dt-bindings: clock: qcom: Remove double colon from description No double colon is necessary in the description. Fix it for all bindings so future bindings won't have the same copy-paste mistake. Reported-by: Rob Herring <robh@kernel.org> Closes: https://lore.kernel.org/lkml/20250625150458.GA1182597-robh@kernel.org/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250717-bindings-double-colon-v1-1-c04abc180fcd@fairphone.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-07-24 12:24:08 -07:00
Frank Li	5d005cf799	dt-bindings: mfd: Convert lpc1850-creg-clk, pc1850-dmamux and phy-lpc18xx-usb-otg to YAML format Combine the following separate plain text based bindings to YAML: lpc1850-creg-clk.txt pc1850-dmamux.txt phy-lpc18xx-usb-otg.txt Additional changes: - remove label in example. - remove dmamux consumer in example. - remove clock consumer in example. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250602143612.943516-1-Frank.Li@nxp.com Signed-off-by: Lee Jones <lee@kernel.org>	2025-07-24 11:26:58 +01:00
Arnd Bergmann	7723866e8b	Qualcomm Arm64 DeviceTree updates for v6.17 `79b896e7da` arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree `6516961352` arm64: dts: qcom: Add support for X1-based Asus Zenbook A14 The DB410c D3 camera mezzanine is converted to an overlay. On MSM8976 SDC2 pinctrl definitions are introduced and BLSP DMA controller is marked to be managed by another entity. Add camera subsystem on the QCM2290 platform. Add and enable remoteproc and related devices on QCS615. Add and enable Video encoder/decoder on QCS8300 and SA8775P. Also on SA8775P add CPU OPP tables for scaling DDR/L3 bandwidth based on CPU frequency, add L3 interconnect definitions, DSI and video encoder/decoder support. Enable the SLPI remoteproc on SDM850-based Lenovo Yoga C630. On SM6350, add the video clock controller, APR and some audio related services. Describe the camera subsystem on SM8550 and add Iris video encoder/decoder node for SM8650. On SM8750 introduce UFS and Soundwire support, enable these and describe the sound hardware on MTP and QRD. Add camera clock controller on SC8180X. On X Elite, for the Dell XPS13, add WiFi and Bluetooth pwrseq and enable the fingerprint sensor. For HP Omnibook X14 USB1 SS1 SBU mux and do some misc cleanup. Replace the thermal zones inherited from X Elite with X Plus-specific ones. Add missing interrupts and clean up unrelated clocks for PCIe controllers across a variety of platforms. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmh3GBgVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FHKgP/3fD3fSclattuh80iPSjhx85vy3E ZZXT++lYy+UayENPOYwA2BToTgogWUmZvxRnrCCagJWm0MfBk1F76q2b01HlD64P kxztJfdVPlcQKDcjKZONzmGeLH0Bqx2/c96YBZ/8fSqAJI24NJ0KMKQq2LfgfiI3 5j3VQprf4ec/OdHanWrWupN4OIgpG916fonsvPc7GLE5pkqeE6miYuRVdWlmPX8L tP5vrOAIvUJGtgwQGz/TuB8J2ua6ZTy8Uj4PbPA5Lj5C79SHXiUJL6/lqhsPWBpW uGNyJo6pJ3LIGujS9rxvD9z8egnAxiDxovByCmT0yRx+NOQ4mAEzd0Q3nKgBD67U LDuOrurVPlZmCMchcfwXgg9qK6do3D56+Cql8yUn4CsdHJkGSygly7hyKXT9s1KK cBTKVom/WrBn+RGWhFAEa3cbM1qeWJSBtqVJuV88e+3h0kImDR0zCcqxXE6dWfIO DB5IeG7iCTtYws6O2mKaHdAuqGJ4eFdA7W5oL0bDKD7dlZvDUz9suGacWRaSKktM 9g36SLBR5x9rHQzaEyq3NCtWO3jAYuXvxTqdumf99xNwYhfbOmwQzwpDJRBPc+Lx Vbu4gGJoCHk7A3ts4PUS83Hcq5h/6B8PAjK26hih6ntc+T+6SlUZakFuQ7lx6GJI EP9JSa+rD4fbrxgt =SyDg -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmh/8l8ACgkQmmx57+YA GNln7A/+Ie7lDZLAluHFWngBCg1OFyfKm5m9qp0ETfF9XYaGXXrE+gqOIwKLbh94 FzP0HTvFeTHqz0sl77CGv/Lu4MwfxlSnmjqiXI+yzXMDuornc2lX7e1xGYKVOBYF FpBtetEXiU6ljar7hchJMeB27VfAc20456aE4BBgngWpStMTRonV1uruOJVWTzQZ sdvRDL/h7mJbIXYFQcG6ZaaRGpi4PQW26Fn2V60p+2ta0S59v8tYZ7zt3FnIZRE1 GBQ6zn6QsF7oVjLOPgKPD2y2KZEfHGrLBMySdkISBazbJZ6cFS37OeqFyf/SCP3r xHMvbqmxgbouYsXesnECoRAHHFENTeFE45o9Vo5GDVhMr8tePyPSndDNTZvQ3Woo QLiKdG1HdZSbDG5Rt4+BC3goJ8m9NM2hG3mBjdYlzqHf2oIe1V9oipmJvgXCFRnd SuJFQxr6zR0U4CaLiTdX1XA5UyKg1knpeAN1Bff5uwY1x4yFyOD9TFoDLqsSZlOf j3MxVW2SKoEeOmqb5/CGe1AlO8Y2l4wglEETDY40wWXtVgsMjSiTvTBpPP7kh5eK ufiBYB6TqTV0WSYr336H5QuxB+CjOEOxBzF9D3mhIK3MvEAimgGmBKtkBJVHsQXU KkcR5Of5up0dpgh2zRAFqUpprQLO0FeGmSw5Y0n2oRoLareSej8= =VsT2 -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree updates for v6.17 `79b896e7da` arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree `6516961352` arm64: dts: qcom: Add support for X1-based Asus Zenbook A14 The DB410c D3 camera mezzanine is converted to an overlay. On MSM8976 SDC2 pinctrl definitions are introduced and BLSP DMA controller is marked to be managed by another entity. Add camera subsystem on the QCM2290 platform. Add and enable remoteproc and related devices on QCS615. Add and enable Video encoder/decoder on QCS8300 and SA8775P. Also on SA8775P add CPU OPP tables for scaling DDR/L3 bandwidth based on CPU frequency, add L3 interconnect definitions, DSI and video encoder/decoder support. Enable the SLPI remoteproc on SDM850-based Lenovo Yoga C630. On SM6350, add the video clock controller, APR and some audio related services. Describe the camera subsystem on SM8550 and add Iris video encoder/decoder node for SM8650. On SM8750 introduce UFS and Soundwire support, enable these and describe the sound hardware on MTP and QRD. Add camera clock controller on SC8180X. On X Elite, for the Dell XPS13, add WiFi and Bluetooth pwrseq and enable the fingerprint sensor. For HP Omnibook X14 USB1 SS1 SBU mux and do some misc cleanup. Replace the thermal zones inherited from X Elite with X Plus-specific ones. Add missing interrupts and clean up unrelated clocks for PCIe controllers across a variety of platforms. * tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits) arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts arm64: dts: qcom: x1-asus-zenbook: support sound arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes arm64: dts: qcom: sm6115: add debug UART pins arm64: dts: qcom: sm8650: add iris DT node arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree arm64: dts: qcom: msm8976: Add sdc2 GPIOs dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc arm64: dts: qcom: sm8550: Add support for camss arm64: dts: qcom: qcs615: disable the CTI device of the camera block arm64: dts: qcom: qcs615-ride: enable remoteprocs arm64: dts: qcom: qcs615: add ADSP and CDSP nodes arm64: dts: qcom: qcs615: Add IMEM and PIL info region arm64: dts: qcom: qcs615: Add mproc node for SEMP2P arm64: dts: qcom: Add support for X1-based Asus Zenbook A14 arm64: dts: qcom: sc7180: Expand IMEM region arm64: dts: qcom: sdm845: Expand IMEM region ... Link: https://lore.kernel.org/r/20250716031059.76348-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-07-22 22:19:42 +02:00
Peng Fan	0b0cd1857b	dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR Add i.MX94 LVDS/DISPLAY CSR compatible string. Add clock index for the two CSRs. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-1-c1b676ec13be@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2025-07-21 10:33:54 +03:00
Satya Priya Kakitapalli	45dd59885c	dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml Reference the common qcom,gcc.yaml schema to unify the common parts of the binding. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250717-gcc-ref-fixes-v2-4-a2a571d2be28@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-19 22:42:28 -05:00
Satya Priya Kakitapalli	9df98d4b50	dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml Reference the common qcom,gcc.yaml schema to unify the common parts of the binding. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250717-gcc-ref-fixes-v2-3-a2a571d2be28@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-19 22:42:28 -05:00
Satya Priya Kakitapalli	56245968a7	dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml Reference the common qcom,gcc.yaml schema to unify the common parts of the binding. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250717-gcc-ref-fixes-v2-2-a2a571d2be28@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-19 22:42:28 -05:00
Satya Priya Kakitapalli	92b7d67614	dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml Reference the common qcom,gcc.yaml schema to unify the common parts of the binding. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250717-gcc-ref-fixes-v2-1-a2a571d2be28@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-19 22:42:28 -05:00
Luca Weiss	40f7d6d176	dt-bindings: clock: qcom: Remove double colon from description No double colon is necessary in the description. Fix it for all bindings so future bindings won't have the same copy-paste mistake. Reported-by: Rob Herring <robh@kernel.org> Closes: https://lore.kernel.org/lkml/20250625150458.GA1182597-robh@kernel.org/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250717-bindings-double-colon-v1-1-c04abc180fcd@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-19 22:41:39 -05:00
Luca Weiss	a4937e9741	dt-bindings: clock: qcom: document the Milos Video Clock Controller Add bindings documentation for the Milos (e.g. SM7635) Video Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:17:05 -05:00
Luca Weiss	7e5368a14b	dt-bindings: clock: qcom: document the Milos GPU Clock Controller Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:17:05 -05:00
Luca Weiss	63edb206a3	dt-bindings: clock: qcom: document the Milos Display Clock Controller Add bindings documentation for the Milos (e.g. SM7635) Display Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:17:05 -05:00
Luca Weiss	dbb9d53b71	dt-bindings: clock: qcom: document the Milos Camera Clock Controller Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:17:05 -05:00
Luca Weiss	95ba6820a6	dt-bindings: clock: qcom: document the Milos Global Clock Controller Add bindings documentation for the Milos (e.g. SM7635) Global Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:17:04 -05:00
Stephan Gerhold	3b4e2820e1	dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible X1E80100 videocc is largely identical to SM8550, but needs slightly different PLL frequencies. Add a separate qcom,x1e80100-videocc compatible to the existing schema used for SM8550. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-1-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:16:15 -05:00
Luca Weiss	5009024ad7	dt-bindings: clock: qcom: document the Milos TCSR Clock Controller Add bindings documentation for the Milos (e.g. SM7635) TCSR Clock Controller. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-3-b49f19055768@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:15:25 -05:00
Luca Weiss	136e6393a5	dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller Add bindings documentation for the Milos (e.g. SM7635) RPMH Clock Controller. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-1-b49f19055768@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:15:25 -05:00
Taniya Das	9c51c66c99	dt-bindings: clock: Add Qualcomm QCS615 Video clock controller Add DT bindings for the Video clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:12:06 -05:00
Taniya Das	3590dfbdd1	dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:12:06 -05:00
Taniya Das	8b1750ea00	dt-bindings: clock: Add Qualcomm QCS615 Display clock controller Add DT bindings for the Display clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:12:06 -05:00
Taniya Das	8df2964990	dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller Add DT bindings for the Camera clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:12:05 -05:00
Bjorn Andersson	3c4ee2cc7f	Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17 Merge the IPQ5018 CMN PLL binding through a topic branch, to allow merging the clock defines into DeviceTree branch as well.	2025-07-16 23:04:22 -05:00
George Moussalem	314b903c30	dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-07-16 23:03:27 -05:00
Ezra Buehler	292f0b50d3	dt-bindings: clock: mediatek,mtmips-sysc: Adapt compatible for MT7688 boards As the MT7628 and MT7688 are identical in most respects, mt7628a.dtsi is used for both SoCs. To prevent "Kernel panic - not syncing: unable to get CPU clock, err=-2" and allow an MT7688-based board to boot, the following must be allowed: compatible = "ralink,mt7628-sysc", "ralink,mt7688-sysc", "syscon"; Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>	2025-07-02 13:17:24 +02:00
Julien Massot	a42b4dcc4f	dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 The '#reset-cells' property is permitted for some of the MT8188 clock controllers, but not listed as a valid property. Fixes: `9a5cd59640` ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-20 18:17:23 -07:00
Frank Li	4c55936671	dt-bindings: clock: convert lpc1850-ccu.txt to yaml format Convert lpc1850-ccu.txt to yaml format. Additional changes: - remove label in examples. - remove clock consumer in examples. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250602141937.942091-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-19 13:02:33 -07:00
Geert Uytterhoeven	5701451e84	Renesas RZ/N2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087) SoC, shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaFRUEAAKCRCKwlD9ZEnx cC7OAP0bFBqHJmfJezBF/yGFbatO4Ci9uXsBvVd8cSOesd75FQD/Xc8fLaf5hkPL TCushNiZfVZqPE3AXJBgzdCYqPH7cw4= =/rkp -----END PGP SIGNATURE----- Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17 Renesas RZ/N2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087) SoC, shared by driver and DT source files.	2025-06-19 20:19:13 +02:00
Lad Prabhakar	292bf6c5b8	dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support Document support for Module Standby and Software Reset found on the Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP is similar to that found on the RZ/T2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2025-06-19 20:08:13 +02:00
Rob Herring (Arm)	2e090ae61f	dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema Convert the Alphascale Clock Controller binding to DT schema format. Add the undocumented 'clocks' property which is used in DTS. Drop the clock defines and consumer examples from the old binding. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004712.1793193-1-robh@kernel.org Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:42:10 -07:00
Rob Herring (Arm)	cc33289129	dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema Convert the Marvell Armada 3xx Core Divider clock binding to DT schema format. Add the missing "marvell,armada-390-corediv-clock" compatible and "clock-output-names" property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521211840.77487-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:41:42 -07:00
Rob Herring (Arm)	ed4ce1d924	dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema Convert the Marvell Armada 3700 peripheral clock binding to DT schema format. The north bridge is also a "syscon", so add the compatible to it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521211826.77098-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:41:30 -07:00
Rob Herring (Arm)	7cbc8535b2	dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema Convert the Marvell SoC core clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210844.62613-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:41:24 -07:00
Rob Herring (Arm)	75cc48275f	dt-bindings: clock: Convert marvell,berlin2-clk to DT schema Convert the Marvell Berlin2 clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210839.62409-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:41:02 -07:00
Rob Herring (Arm)	e3fcba910a	dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema Convert the Marvell Dove PLL divider clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210832.62177-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:40:48 -07:00
Rob Herring (Arm)	9919d2a81b	dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema Convert the Marvell Armada 3700 TBG clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210826.61957-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:40:34 -07:00
Rob Herring (Arm)	e9a17eaaf1	dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema Convert the Marvell gating clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210813.61484-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:40:24 -07:00
Rob Herring (Arm)	12fa3aaf8b	dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema Convert the Marvell Armada XP CPU clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210806.61286-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:40:14 -07:00
Rob Herring (Arm)	f139defc6b	dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema Convert the TI-NSPIRE clock bindings to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210750.60759-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:40:02 -07:00
Rob Herring (Arm)	bb21488670	dt-bindings: clock: Convert lsi,axm5516-clks to DT schema Convert the Intel/LSI AXM5516 clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210741.60467-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:39:52 -07:00
Rob Herring (Arm)	46dba2e6a3	dt-bindings: clock: Convert img,pistachio-clk to DT schema Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210712.59742-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:39:41 -07:00
Rob Herring (Arm)	100026f4b5	dt-bindings: clock: Convert brcm,bcm2835-cprman to DT schema Convert the Broadcom BCM2835 CPRMAN clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004625.1791913-1-robh@kernel.org Reviewed-by: Stefan Wahren <wahrenst@gmx.net> [sboyd@kernel.org: Add list to maintainers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:38:43 -07:00
Rob Herring (Arm)	add0c5621c	dt-bindings: clock: Convert cirrus,ep7209-clk to DT schema Convert the Cirrus EP7xxx (aka CLPS711x) binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004923.1795927-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:36:48 -07:00
Rob Herring (Arm)	094e11183d	dt-bindings: clock: Convert APM XGene clocks to DT schema Convert the APM XGene clocks to DT schema. The device clock binding is a bit different from the others, so put it in its own schema file. Drop the examples. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004655.1792703-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:35:16 -07:00
Rob Herring (Arm)	bd6ada566e	dt-bindings: clock: Convert axis,artpec6-clkctrl to DT schema Convert the Axis ARTPEC-6 clock controller to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004647.1792464-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:35:01 -07:00
Rob Herring (Arm)	4a7d79c8b0	dt-bindings: clock: Convert brcm,bcm53573-ilp to DT schema Convert the Broadcom BCM53573 ILP clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004618.1791669-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-18 18:25:43 -07:00
Bjorn Andersson	c1e21ccfe4	Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17 Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the newly introduced clock constants to be made available to the DeviceTree branch as well.	2025-06-18 17:16:38 -05:00
Luo Jie	0c25ae62f5	dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference input clock. The output clocks are the same as IPQ9574 SoC, except for the clock rate of output clocks to PPE and NSS. Also, add the new header file to export the CMN PLL output clock specifiers for IPQ5424 SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-06-18 17:16:26 -05:00
Raghav Sharma	da5cb65d25	dt-bindings: clock: exynosautov920: add hsi2 clock definitions Add device tree clock binding definitions for CMU_HSI2 Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250529112640.1646740-3-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-06-12 17:26:57 +02:00
Raghav Sharma	3d6470990b	dt-bindings: clock: exynosautov920: sort clock definitions Sort all the clock compatible strings in alphabetical order Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250529112640.1646740-2-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-06-12 17:26:57 +02:00
Rob Herring (Arm)	554ec5b1bd	dt-bindings: clock: Convert brcm,bcm63xx-clocks to DT schema Convert the Broadcom BCM63xx clock bindings to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521004610.1791426-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-11 11:21:55 -05:00
Sukrut Bellary	358df002da	dt-bindings: clock: ti: add ti,autoidle.yaml reference ti,divider-clock uses properties from ti,autoidle. As we are converting autoidle binding to ti,autoidle.yaml, fix the reference here. Signed-off-by: Sukrut Bellary <sbellary@baylibre.com> Link: https://lore.kernel.org/r/20250516081612.767559-4-sbellary@baylibre.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-11 11:13:16 -05:00
Sukrut Bellary	a7953b62de	dt-bindings: clock: ti: Convert fixed-factor-clock to yaml This uses the ti,autoidle.yaml for clock autoidle support. Clean up the example to meet the current standards. Add the creator of the original binding as a maintainer. Signed-off-by: Sukrut Bellary <sbellary@baylibre.com> Link: https://lore.kernel.org/r/20250516081612.767559-3-sbellary@baylibre.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-11 11:13:08 -05:00
Sukrut Bellary	5ffe2d2f53	dt-bindings: clock: ti: Convert autoidle binding to yaml Autoidle clock is not an individual clock; it is always a derivate of some basic clock like a gate, divider, or fixed-factor. This binding will be referred in ti,divider-clock.yaml, and ti,fixed-factor-clock.yaml. As all clocks don't support the autoidle feature e.g., in DRA77xx/AM57xx[1], dpll_abe_x2* and dpll_per_x2 don't have autoidle, remove required properties from the binding. Add the creator of the original binding as a maintainer. [1] https://www.ti.com/lit/ug/spruhz6l/spruhz6l.pdf Signed-off-by: Sukrut Bellary <sbellary@baylibre.com> Link: https://lore.kernel.org/r/20250516081612.767559-2-sbellary@baylibre.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-06-11 11:12:54 -05:00
Bjorn Andersson	910ad0190c	Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17 Merge topic branch with missing GCC clocks and the camera clock controller for SC8180X through a topic branch, to make it available for DeviceTree inclusion as well.	2025-06-10 22:14:41 -05:00
Satya Priya Kakitapalli	b5975ce461	dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller Add device tree bindings for the camera clock controller on Qualcomm SC8180X platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-06-10 22:14:31 -05:00
Jagadeesh Kona	842fa74829	dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc SC8280XP camcc only requires the MMCX power domain, unlike SM8450 camcc which now supports both MMCX and MXC power domains. Hence move SC8280XP camcc from SM8450 to SA8775P camcc, to have single power domain support. SA8775P camcc doesn't support required-opps property currently but SC8280XP camcc need that property, so add required-opps based on SC8280XP camcc conditional check in SA8775P camcc bindings. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-3-02303b3a582d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-06-10 12:59:19 -05:00
Vladimir Zapolskiy	a02a8f8cb7	dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the camcc bindings to include the MXC power domain on these platforms. Fixes: `9cbc64745f` ("dt-bindings: clock: qcom: Add SM8550 camera clock controller") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-06-10 12:59:19 -05:00
Jagadeesh Kona	1a42f4d4bb	dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain To configure the video PLLs and enable the video GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the videocc bindings to include the MXC power domain on these platforms. Fixes: `1e910b2ba0` ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-06-10 12:59:19 -05:00
Claudiu Beznea	705d9f8f18	Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S" This reverts commit `f33dca9ed6`. Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain IDs. Currently, there are no device tree users for #power-domain-cell = <1>. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2025-06-10 10:24:17 +02:00
Geert Uytterhoeven	e5e8a9cce5	Renesas RZ/T2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077) SoC, shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaDRVwgAKCRCKwlD9ZEnx cDE1AP0UJ+Ooch5SIEiaDLkJ6uH+3YY4W+11LnjSQ/ir7XIIpwD/aK9jWxjWcWLd sqFXKOVwql/oAKgja6fwzfUqR2qZ5Qg= =pQ0H -----END PGP SIGNATURE----- Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17 Renesas RZ/T2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.	2025-06-10 10:23:58 +02:00
Andrea della Porta	7b746d584a	dt-bindings: clock: Add RaspberryPi RP1 clock bindings Add device tree bindings for the clock generator found in RP1 multi function device, and relative entries in MAINTAINERS file. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>	2025-06-09 10:10:30 -07:00
Linus Torvalds	ec71f661a5	soc: devicetree updates for 6.16 There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straig reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmg5zYMACgkQmmx57+YA GNl1Ag/8CX35g42Gwxyr2X8wit+O2eU0axGoxM+SD1cmIcSnutZjMGu17lDGduOO 8FC524yLE6Z9HxAUa2/cd+5fOiJcsd6Ggi5WXEFc+dHz0+P5End2DNsdIANbGcFU OAhCpuSB63/Mb5dcecoUULw+LIXIBffwt3FCJ0AaXFDi4RvWr0WatzQxHk/G63ci IoE5pAs/6W9mFvQ5R8Kt4jKISy1zF3JgqOmzy+JIsczPHlyMsbFosZRDxBWMRDza PenoULO/RSe3k37PGe8XCU1sja0lSCVEeJINUB11mSVGoIKRZ9Wxf57O9J81cEqF 8HiqQ58vA/HpStPKfWZV3rXSlc3U3XGUj0lbG4iUSIOE4gMKnjWbPVuBTrr5mYsc cJ1pnzbZ0gbylufeS088GkCCKY/ej40aH0vLeoXEHwGh9LoWudI2xMrTJgwX5AlM H+X9kmP+JaC/woMmY7fr9XpMYuggraIMvDzI1j3qfohGnAUFCG7kh2IvfqkLNAEM o2dJkI/r/PY+fPeHBPw6EvsP6ZJhcorczwB7CxVEYJ8fqKOOunATs+aECa6HLPpv toh86d9rnKUrR9+hbuxacx5xxE/YT30muzh66lnV2p1rCS1RJcnzhAkFzeFNJEXf lpNLMauW1D3Elmk/qawKIxICazeuh4NJyQtNfdrCt/9hEpnmmeM= =ewvq -----END PGP SIGNATURE----- Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...	2025-05-31 08:08:56 -07:00
Stephen Boyd	63bfd78aae	Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next * clk-amlogic: clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc * clk-allwinner: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: sunxi: Do not enable by default during compile testing clk: sunxi-ng: Do not enable by default during compile testing * clk-rockchip: clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux dt-bindings: clock: rk3036: add SCLK_USB480M clock-id clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region clk: rockchip: Support MMC clocks in GRF region dt-bindings: clock: Add GRF clock definition for RK3528 clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576 clk: rockchip: introduce GRF gates clk: rockchip: introduce auxiliary GRFs dt-bindings: clock: rk3576: add IOC gated clocks clk: rockchip: rk3568: Add PLL rate for 33.3MHz clk: rockchip: Drop empty init callback for rk3588 PLL type clk: rockchip: rk3588: Add PLL rate for 1500 MHz * clk-qcom: clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz dt-bindings: clock: add SM6350 QCOM video clock bindings clk: qcom: gpucc-sm6350: Add _wait_val values for GDSCs clk: qcom: gcc-sm6350: Add _wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add _wait_val values for GDSCs clk: qcom: camcc-sm6350: Add _wait_val values for GDSCs clk: qcom: Fix missing error check for dev_pm_domain_attach()	2025-05-29 00:30:39 -07:00
Stephen Boyd	3e515fc860	Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next * clk-socfpga: clk: socfpga: stratix10: Optimize local variables clk: socfpga: clk-pll: Optimize local variables * clk-sophgo: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC * clk-thead: clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC dt-bindings: clock: thead: Add TH1520 VO clock controller * clk-samsung: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function	2025-05-29 00:30:28 -07:00
Stephen Boyd	7459da16c9	Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next * clk-bindings: dt-bindings: clock: Drop st,stm32h7-rcc.txt dt-bindings: clock: convert bcm2835-aux-clock to yaml dt-bindings: clock: Drop maxim,max77686.txt dt-bindings: clock: convert vf610-clock.txt to yaml format * clk-renesas: (26 commits) clk: renesas: r9a09g047: Add XSPI clock/reset clk: renesas: r9a09g047: Add support for xspi mux and divider dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks clk: renesas: Use str_on_off() helper clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() ... * clk-spacemit: clk: spacemit: k1: Add TWSI8 bus and function clocks clk: spacemit: Add clock support for SpacemiT K1 SoC dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon * clk-cleanup: clk: test: Forward-declare struct of_phandle_args in kunit/clk.h clk: davinci: Use of_get_available_child_by_name() clk: bcm: rpi: Add NULL check in raspberrypi_clk_register() clk: bcm: rpi: Drop module alias clk: bcm: kona: Remove unused scaled_div_build	2025-05-29 00:30:17 -07:00
Thierry Bultel	4e591b890a	dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support Document RZ/T2H (a.k.a. r9a09g077) cpg-mssr (Clock Pulse Generator) binding. Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250515141828.43444-3-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2025-05-26 13:51:00 +02:00
Arnd Bergmann	ba32d96e90	RISC-V SpacemiT DT changes for 6.16 - Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKTBAABCgB9FiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmgkEphfFIAAAAAALgAo aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldEI1 QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRUQACgkQMarqR1lN u+2A0Q//fwnp36zuiqqYoZ7N9iFmLYjJlM9UEU2FSZ0/RWxL/1Y7ZBNAUajf7e7p N124gpRM5BJMyA+vHEJH1t8WblKoxwt9fjbn9QlcDYnoq5NuHjLkxwfySe+2V5tW kZoPrSwgZ3ODKn/HL+/ghT4ckNV6V+al6yh9x3Cv70ZYZjSOzRwshIf7JJBjzp9X y89QfuqRVT1YMdzCnWTMb7OVFM1fbPP88jjUR43VRieW9ER/8oaaNQNxg9r3wDFZ V6yOIhI5i43jDZcCKZLJCH+WjcIjDj8zQTbIvZOdZuFOR8FPPK2f+zvJ77C2eT6f fG6iB/yAWMFGNPQ064wWev43Ppq7KDkt2/qzTecBJRg6/+x6ILQy9TElkazkJDb2 EYIiucWoPqNMjSL3BRohJ+d6fSaFHaujhP5MGBYPVA6drAIYlwFPhH2HfebECUt9 4Ip9yzdTJAlXhvzlfXL6KBSCft2LinKVHEFvaNJKaZ5V6E93GP+lNv4rkgRoF+Hz uZsMpE2ex7uAskhFT4DQF7VAKaUvLSBUDVM8La1wy3jJFEl+w7YsSxYRTk3bRYt1 bSUdxCDDR+sD26ceMpiILdEy9cDE91B+ypUF1pu3C4P0vYEDi5pdIiuZmaYuAuXm SSC7ymRy2Ao0TGOtycRInTRtGzFnk9DZKLk+HU8rDJOq3WGpjFg= =yMSa -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmguShMACgkQmmx57+YA GNkNvQ/9EIjYie44k9ZyGxjQHuht6IayZHxyQvNVEp/Ef9l/S3M1PUMexgeHLG+0 8z8eITaP+9zz0wYA0mdoFdh8kdvHkGDVh8cKFrAQmXb1DMk/scQVfOShwh7F4wb4 bTohJIq4pVh/Y/b7Yz9kuCKZFmqx5Wpfg+s5iw9vR4SZ7kRCYnhdbBBXo9dOAFN/ KoGPQf6Pw3pKGMrxRifYyvrhJYuDZER3U+oERA+Rr2pB5tRf1TRHSvHNY//gBmVh bwh09t49pqkMWY0iJoJe7syIRjSLwzZF5HIPZYW8f33r/HKYYrS6quTuq9X3hnGI WYwBUftxIW9EU0vFQ/U+vZZRbArYfuydvpuh1iaHSo3ZBeu9cHQKH4HFQg/oUoaG rgvRKBd0Zb+bChvkpTj6hPrFht9m1IYhoDnazD9hhKXXHVSZsENm/3jhpUmQdOfW vpzW6AWUKCM7+ScFqMyvzTvCnuBdZNGzS1L9SWMwv8k6vs5mhTuO1Zqzli2WDEae D1MNzonF5NR91K4ayYMOz+HOZzQ6cOzJHUADd7Zk/zh0BClS0h6M88Dqql0C68ww 3Oeao9Z1e9BhO7Ubzh+/YV3fRff+/U1UZnRpFQnnqzbVw8YmAbivltJj86R7ftVp HnW5S9NLUz+UonGAwRRWck78I4/pRG2EbyQvFofta0U7ILePDYM= =09rm -----END PGP SIGNATURE----- Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux into soc/dt RISC-V SpacemiT DT changes for 6.16 - Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat * tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: add gpio LED for system heartbeat riscv: dts: spacemit: add gpio support for K1 SoC riscv: dts: spacemit: Acquire clocks for UART riscv: dts: spacemit: Acquire clocks for pinctrl riscv: dts: spacemit: Add clock tree for SpacemiT K1 dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-05-21 23:48:03 +02:00
Matthew Gerlach	24822c4b47	dt-bindings: clock: socfpga: convert to yaml Convert the clock device tree bindings to yaml for the Altera SoCFPGA Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are subnodes to Altera SOCFPGA Clock Manager, the yaml was added to socfpga-clk-manager.yaml. Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>	2025-05-21 18:49:56 +02:00
Ryan Walklin	ab1a94b504	dt-bindings: allwinner: add H616 DE33 clock binding The Allwinner H616 and variants have a new display engine revision (DE33). Add a clock binding for the DE33. Signed-off-by: Ryan Walklin <ryan@testtoast.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://patch.msgid.link/20250511104042.24249-7-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>	2025-05-12 23:55:06 +08:00
Konrad Dybcio	b887afb9b2	dt-bindings: clock: add SM6350 QCOM video clock bindings Add device tree bindings for video clock controller for SM6350 SoCs. Signed-off-by: Konrad Dybcio <konradybcio@kernel.org> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-2-cc22386433f4@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-05-10 11:50:29 -05:00
Michal Wilczynski	1b4bb451f3	dt-bindings: clock: thead: Add TH1520 VO clock controller Add device tree bindings for the TH1520 Video Output (VO) subsystem clock controller. The VO sub-system manages clock gates for multimedia components including HDMI, MIPI, and GPU. Document the VIDEO_PLL requirements for the VO clock controller, which receives its input from the AP clock controller. The VIDEO_PLL is a Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz with maximum FOUTVCO of 2376 MHz. This binding complements the existing AP sub-system clock controller which manages CPU, DPU, GMAC and TEE PLLs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Drew Fustini <drew@pdp7.com>	2025-05-07 10:08:10 -07:00
Inochi Amaoto	1a21590498	dt-bindings: clock: sophgo: add clock controller for SG2044 The clock controller on the SG2044 provides common clock function for all IPs on the SoC. This device requires PLL clock to function normally. Add definition for the clock controller of the SG2044 SoC. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250418020325.421257-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>	2025-05-07 07:44:30 +08:00
Inochi Amaoto	6d880961f5	dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC As previous binding uses a wildcard compatible for existed clock device of CV1800 series SoC, it is not suitable for existed requirement. The only exception is sophgo,sg2000-clk, it does match a real device, so keep it as is. Add new precise compatible for existed clock devices of CV1800 series SoCs and make old wildcard compatible deprecated. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250504104553.1447819-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>	2025-05-07 07:42:35 +08:00
Rob Herring (Arm)	72b421e645	dt-bindings: clock: Drop st,stm32h7-rcc.txt The binding is already covered by st,stm32-rcc.yaml. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250505161933.1432791-1-robh@kernel.org Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-05-06 14:15:02 -07:00
Stefan Wahren	619ddc6935	dt-bindings: clock: convert bcm2835-aux-clock to yaml Convert the DT binding document for BCM2835 auxiliary peripheral clock from .txt to YAML. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250503080949.3945-1-wahrenst@gmx.net Acked-by: Conor Dooley <conor.dooley@microchip.com> [sboyd@kernel.org: Drop aux label] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-05-06 14:13:01 -07:00
Rob Herring (Arm)	66bd98084f	dt-bindings: clock: Drop maxim,max77686.txt The clock binding for Maxim MAX77686/MAX77802/MAX77620 is already covered by mfd/maxim,max77686.yaml. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250505161943.1433081-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-05-06 14:10:36 -07:00
Shin Son	3c50137aa4	dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions Add cpucl1 and cpucl2 clock definitions. CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250428113517.426987-2-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-04-30 09:24:04 +02:00
Frank Li	7021a86694	dt-bindings: clock: convert vf610-clock.txt to yaml format Convert vf610-clock.txt to yaml format. Additional changes: - swap audio_ext and enet_ext to match existed dts order - remove clock consumer in example Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250411212339.3273202-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-04-29 14:05:14 -07:00
Shin Son	e2642509e3	dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Add cpucl0 clock definitions. CPUCL0 refers to CPU Cluster 0, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250423044153.1288077-2-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-04-27 21:21:40 +02:00
Haylen Chu	8090804045	dt-bindings: clock: spacemit: Add spacemit,k1-pll Add definition for the PLL found on SpacemiT K1 SoC, which takes the external 24MHz oscillator as input and generates clocks in various frequencies for the system. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-3-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>	2025-04-17 03:22:49 +08:00
Lad Prabhakar	c04269c022	dt-bindings: clock: renesas: Document RZ/V2N SoC CPG Document the device tree bindings for the Renesas RZ/V2N (R9A09G056) SoC Clock Pulse Generator (CPG). Update `renesas,rzv2h-cpg.yaml` to include the compatible string for RZ/V2N SoC and adjust the title and description accordingly. Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific clock driver will be reused for this SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2025-04-14 10:48:18 +02:00
Linus Torvalds	59c35416f4	Here's the pile of clk driver patches. The usual suspects^Wsilicon vendors are all here, adding new SoC support and fixing existing code. There are a few patches to the clk framework here as well. They've been baking in linux-next for weeks so I'm hoping we don't have to revert them. The disable OF node patch is probably the scariest one although it seems unlikely that a system would be relying on a driver _not_ probing because the clk never appeared, but you never know. Nothing looks out of the ordinary on the driver side but that's because it's mostly a bunch of data. Core: - Use dev_err_probe() in the clk registration path (Peering into the crystal ball shows many patches that remove printks) - Check for disabled OF nodes in of_clk_get_hw_from_clkspec() New Drivers: - Allwinner A523/T527 clk driver - Qualcomm IPQ9574 NSS clk driver - Qualcomm QCS8300 GPU and video clk drivers - Qualcomm SDM429 RPM clks - Qualcomm QCM6490 LPASS (low power audio) resets - Samsung Exynos2200: driver for several clock controllers (Alive, CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS) - Samsung Exynos7870: Driver for several clock controllers (Alive, MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI) - Rockchip rk3528 and rk3562 clk driver Updates: - Various fixes to SoC clk drivers for incorrect data, avoid touching protected registers, etc. - Additions for some missing clks in existing SoC clk drivers - DT schema conversions from text to YAML - Kconfig cleanups to allow drivers to be compiled on moar architectures -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmfm9fYRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWl9w/9Ed68QreuOgHOo8tnOeqtGMvYEaJ7fnA4 4P4nsLtSwD1J5ZxOMgE4d2PpyRAFeaRhcbqYhiyk/DJZ0qnkXfQWOwhRS33IS7A/ cf+n0liMMXDDjQ5E0mLqbjzrJVKnb1q9Y0QnKaPJBtl/Ehn8l2bPluJlO5AdmgkE /wn9uCxY/5qaffaLWjVp/el5QnwixCbYsn5NV/gBwSCj8quTAGu5MNIE547gjhXK p2zfAcQ66r+Sdd2MT5sXnMpvuzvFxhRl21Nz7Ea9yo8legzdbrVqNuH1WSlvLHUV w1rshP1IcEBRseiP96eTlz6BJfjGfFClbzP9dv5s+XxinRpxTh+izp8xaEQGcsGP VrDIAo6vW9TO5U3HQHt7u2LgzGNB+kLKmXzxYvPyCB4lW8dIKfPv4QE+EGGCiMM/ KHGeukREObqW7vOvTMejBGxwer7qUB75DWRDMtTQJYmncvPn9efO0+cl0SbT8M9b fXJsTI4PuGoFEowwq4VPoELhiafB9hXlzaFF58IHwssLEjM4GgdUePuDizsfNYzr zD0k+o6zWXXP5jJLvHsdxuiRK99rEHRb03s+v4yAilTK+cRislQIvyUy3mSw6LBF bZe77U/9aEINMsxTehVXmsG7aaf3B32RHi03YOXWu8JtC36hhRhdJQKXMgl2G0gZ ND7dptBkM9M= =RRKz -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Here's the pile of clk driver patches. The usual suspects^Wsilicon vendors are all here, adding new SoC support and fixing existing code. There are a few patches to the clk framework here as well. They've been baking in linux-next for weeks so I'm hoping we don't have to revert them. The disable OF node patch is probably the scariest one although it seems unlikely that a system would be relying on a driver _not_ probing because the clk never appeared, but you never know. Nothing looks out of the ordinary on the driver side but that's because it's mostly a bunch of data. Core: - Use dev_err_probe() in the clk registration path (Peering into the crystal ball shows many patches that remove printks) - Check for disabled OF nodes in of_clk_get_hw_from_clkspec() New Drivers: - Allwinner A523/T527 clk driver - Qualcomm IPQ9574 NSS clk driver - Qualcomm QCS8300 GPU and video clk drivers - Qualcomm SDM429 RPM clks - Qualcomm QCM6490 LPASS (low power audio) resets - Samsung Exynos2200: driver for several clock controllers (Alive, CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS) - Samsung Exynos7870: Driver for several clock controllers (Alive, MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI) - Rockchip rk3528 and rk3562 clk driver Updates: - Various fixes to SoC clk drivers for incorrect data, avoid touching protected registers, etc. - Additions for some missing clks in existing SoC clk drivers - DT schema conversions from text to YAML - Kconfig cleanups to allow drivers to be compiled on moar architectures" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits) clk: qcom: Add NSS clock Controller driver for IPQ9574 clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps clk: amlogic: a1: fix a typo clk: amlogic: gxbb: drop non existing 32k clock parent clk: amlogic: gxbb: drop incorrect flag on 32k clock clk: amlogic: g12b: fix cluster A parent data clk: amlogic: g12a: fix mmc A peripheral clock dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles dt-bindings: reset: fix double id on rk3562-cru reset ids drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 dt-bindings: clock: qcom: Add compatible for QCM6490 boards clk: qcom: gdsc: Update the status poll timeout for GDSC clk: qcom: gdsc: Set retain_ff before moving to HW CTRL clk: davinci: remove support for da830 ...	2025-03-29 17:23:34 -07:00
Linus Torvalds	1c83601b8f	Added support for multi-cluster configuration Added quirks for enabling multi-cluster mode on EyeQ6 Added DTS clocks for ralink Cleanup realtek DTS Other cleanups and fixes -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmfnxUoaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHD/MA//aMzae6TL2S/vKVx/QCwL I+Lww1O8CvCgRBiBVkVoS5eXeqt8NzyCwicFT5LmLxI+lw5wFrgBO6rbcq2NxLHY q9I8dz5qTpGomT7TWoL8t97ZGxpLSYIqx4cqvvQrIhczWCGsvgAtep03sstlX6iT RouZ6JIxRh0xSRuloT1947C6dH204t/kuFDJ4uCXrbkmstXhQ/+dip8s7/XMaXHk sU1cjPV8Tpxlwv8X9SR39IKVk7LoHW/92w/J1se5CosHnSlJ7IjaUuO3Y7bp3xdw SLYBxge/JfIcXh0YURS2hhlsdls9e55Zrg+ACn8DTDfFy6kq6v5ZsUEsnWpCKfQl IymQ5246EJgtk8hNGe77qjiMnxbkNeM4v8DB7UVZHPxsGBrUlSNYZL2fSMdXkd2Y JlobF9QgyXf+aZyLtn1g3B6yn8Ajd2L5rmq4fXKbRhMfMno/nnsi8nZ24OPp3lkY KoWkXPwNZfxE7xOnBjk9BleijIHoC7w291j4h4/QMfzJqlkpRDJAKGOTBMOUYrER B5PYGPjTWD8Os0xzp/PGkTMagoKcxzX7LYfAL0iEQ3ixgtwHtni/gUGJItBK6XTK 1KQZaXDcr5EAa6IcGjaNTrpaSQK5duZThPRiUE6fqboHFtB7JmLJZmsFE0BZbcEe mJ21gTa4hFQOQ3J5YZoytEI= =hUDw -----END PGP SIGNATURE----- Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - Add support for multi-cluster configuration - Add quirks for enabling multi-cluster mode on EyeQ6 - Add DTS clocks for ralink - Cleanup realtek DTS - Other cleanups and fixes * tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits) MIPS: config: omega2+, vocore2: enable CLK_MTMIPS arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX MIPS: cm: Fix warning if MIPS_CM is disabled MIPS: Fix Macro name MIPS: ds1287: Match ds1287_set_base_clock() function types MIPS: cevt-ds1287: Add missing ds1287.h include MIPS: dec: Declare which_prom() as static MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy() mips: dts: ralink: mt7628a: update system controller node and its consumers mips: dts: ralink: mt7620a: update system controller node and its consumers mips: dts: ralink: rt3883: update system controller node and its consumers mips: dts: ralink: rt3050: update system controller node and its consumers mips: dts: ralink: rt2880: update system controller node and its consumers dt-bindings: clock: add clock definitions for Ralink SoCs MIPS: Use arch specific syscall name match function mips: dts: realtek: Add restart to Cisco SG220-26P mips: dts: realtek: Add RTL838x SoC peripherals mips: dts: realtek: Replace uart clock property mips: dts: realtek: Correct uart interrupt-parent mips: dts: realtek: Add SoC IRQ node for RTL838x ...	2025-03-29 12:47:09 -07:00
Stephen Boyd	e988adcb5d	Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next * clk-allwinner: clk: sunxi-ng: add support for the A523/T527 PRCM CCU clk: sunxi-ng: a523: add reset lines clk: sunxi-ng: a523: add bus clock gates clk: sunxi-ng: a523: remaining mod clocks clk: sunxi-ng: a523: add USB mod clocks clk: sunxi-ng: a523: add interface mod clocks clk: sunxi-ng: a523: add system mod clocks clk: sunxi-ng: a523: add video mod clocks clk: sunxi-ng: a523: Add support for bus clocks clk: sunxi-ng: Add support for the A523/T527 CCU PLLs dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs clk: sunxi-ng: Add support for update bit clk: sunxi-ng: mp: provide wrappers for setting feature flags clk: sunxi-ng: mp: introduce dual-divider clock clk: sunxi-ng: h616: Reparent GPU clock during frequency changes clk: sunxi-ng: h616: Add clock/reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset * clk-amlogic: clk: amlogic: a1: fix a typo clk: amlogic: gxbb: drop non existing 32k clock parent clk: amlogic: gxbb: drop incorrect flag on 32k clock clk: amlogic: g12b: fix cluster A parent data clk: amlogic: g12a: fix mmc A peripheral clock * clk-qcom: (41 commits) clk: qcom: Add NSS clock Controller driver for IPQ9574 clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 dt-bindings: clock: qcom: Add compatible for QCM6490 boards clk: qcom: gdsc: Update the status poll timeout for GDSC clk: qcom: gdsc: Set retain_ff before moving to HW CTRL clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable() clk: qcom: videocc: Constify 'struct qcom_cc_desc' clk: qcom: gpucc: Constify 'struct qcom_cc_desc' clk: qcom: dispcc: Constify 'struct qcom_cc_desc' clk: qcom: camcc: Constify 'struct qcom_cc_desc' dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover clk: qcom: Add support for Video Clock Controller on QCS8300 clk: qcom: Add support for GPU Clock Controller on QCS8300 ...	2025-03-26 11:26:36 -07:00
Stephen Boyd	3ce2e14a5b	Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-next * clk-rockchip: dt-bindings: reset: fix double id on rk3562-cru reset ids clk: rockchip: Add clock controller for the RK3562 dt-bindings: clock: Add RK3562 cru clk: rockchip: rk3528: Add reset lookup table clk: rockchip: Add clock controller driver for RK3528 SoC clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE dt-bindings: clock: Document clock and reset unit of RK3528 clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent clk: rockchip: rk3568: mark hclk_vi as critical clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1 * clk-samsung: clk: samsung: Drop unused clk.h and of.h headers clk: samsung: Add missing mod_devicetable.h header clk: samsung: add initial exynos7870 clock driver clk: samsung: introduce Exynos2200 clock driver clk: samsung: clk-pll: add support for pll_4311 dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU dt-bindings: clock: add Exynos2200 SoC clk: samsung: Fix UBSAN panic in samsung_clk_init() clk: samsung: Fix spelling mistake "stablization" -> "stabilization" clk: samsung: exynos990: Add CMU_PERIS block dt-bindings: clock: exynos990: Add CMU_PERIS block * clk-imx: clk: imx8mp: inform CCF of maximum frequency of clocks dt-bindings: clock: imx8m: document nominal/overdrive properties clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents dt-bindings: clock: imx8mp: add axi clock	2025-03-26 11:26:32 -07:00
Stephen Boyd	316f4b91f9	Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next * clk-parent: clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec() * clk-renesas: (24 commits) clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 clk: renesas: r7s9210: Distinguish clocks by clock type clk: renesas: rzg2l: Remove unneeded nullify checks clk: renesas: cpg-mssr: Remove obsolete nullify check clk: renesas: r9a09g057: Add entries for the DMACs clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks ... * clk-mediatek: clk: mediatek: Add SMI LARBs reset for MT8188 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock * clk-cleanup: dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles clk: davinci: remove support for da830 dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema clk: mmp: Fix NULL vs IS_ERR() check clk: Print an error when clk registration fails clk: Correct the data types of the variables in clk_calc_new_rates clk: imgtec: use %pe for better readability of errors while printing clk: stm32f4: fix an uninitialized variable clk: keystone: syscon-clk: Do not use syscon helper to build regmap	2025-03-26 11:26:26 -07:00
Bjorn Andersson	0139f7d4e5	Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into clk-for-6.15 Merge the IPQ9574 NSSCC binding through a topic branch, to allow them to also be merged and used in the DeviceTree source tree.	2025-03-17 10:10:46 -05:00
Devi Priya	28300ecedc	dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions Add NSSCC clock and reset definitions for ipq9574. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-03-17 10:10:37 -05:00
Vladimir Zapolskiy	d547913e87	dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps The switch to multiple power domains implies that the required-opps property shall be updated accordingly, a record in one property corresponds to a record in another one. Fixes: `7ec95ff9ab` ("dt-bindings: clock: move qcom,x1e80100-camcc to its own file") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20250304143152.1799966-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-03-16 21:28:31 -05:00
Arnd Bergmann	56beaf1444	Samsung DTS ARM64 changes for v6.15 1. Google GS101: - Disable GSA core pinctrl because its registers are not available for normal world. - Add APM (Active Power Management) mailbox and the ACPM firmware nodes. - Add new boards: Google Pixel 6 Pro (Raven). - Enable framebuffer and reboot-mode. 2. Exynos990: - Add PERIS clock controller, MCT timer 3. Exynos8895: - Define all remaining serial engine (USI) and syscon nodes, add MMC. - Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte). 4. ExynosAutov920: Add UFS and CPU cache information. 5. Various cleanups. This includes two topic branches with DT bindings, which might be shared with other trees depending on needs: 1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller header constants. 2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines header constants rework. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmfN4bEQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1wy7EACAh54/LUmLUP2RDSVPAXsYXkyiL+xbvdWQ Twa0rp6szLxfuTxQgH3oPGKuQ9f/zHJ+ZgXzf5gTUDlIxhvY2TCoKTNKbEaobDSW pCRoBKYogpqeJ7UBC9uTwZlWvI6flbgb7riFYUa2sOFbwCid0rvlo/TeqR8OTuWj NkYI6jfjRWD9qbriW+B9xPW2tgb+jMQGlUKDbDcaF9TRK4XEhLmHiQWudnUXbdSR LuJgBu7+T0CRwiUymp3IMeNK8Qxcv/2MdqYHZjIwX2S4Ftv2u+JbRBViUROOsEQX Rd8LztrLtyyRiqS4Jchc29XPDAEiiWIkJhbdJW5k3Kffk2ADAQznQSgSYhQ7kdzB nAKhGOstCITUnec9nQuS/hzT7wnpOkpBjRCiZfdKV66Rp2b32rDcNskwvUaRu1oV lclzHJWnGQRtTNQ2AQBE4t4Cl+79UopO1r5Y4F4q4VM5zTcp4VttLJdt4NQIq6Mk mgSC8U9aa4YmB+wWthTIaASXI2ml4xj/DA75QdBbIgVNNvyJPiaFQvBsJW1jQ5E9 ZzScu9nju3SjOezDtEZLk3aLRrE8D8bB9lWYveim7m3HsmVFTsYBqrr8uWJrlwma kzqPOlLSzVgEomM7mRC/OgjVg70ds6krDR+sDhYC3y0w0Xdgx9nwIKFDGBLBO0QQ p0225H4AGA== =RKN2 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfUa6EACgkQYKtH/8kJ UieFAhAAyE7m6jdNTkJStfCQjIXHbxdi6yKogmkduUpZzcIm0Wb5yShey6Sv6Boc HLLI8QG56o81pKshhn4yJSfphT7M0gSauhvEBl8xAgli6ysZ9MGhRaL+OqM2xvPO 6x2csEpWEvKSLjtrFWOUg9F0szParJh29DwjzM9xapjjLG2UB2+pLgNYOCAy4xt8 2cRUbTCIHM2AwfNL1wRIJG07Ji68QLCQAiPnuLBzUnvm4xvDxk6QXNcS1+kHLalS /AdPGsOPrcnll2b5uuvcysmSmRdN2urUCLMWx1dBed3JqmsSwXVGW7IdV0i0c4da cwPDkwu6IVM+fAV225DSwQ7TDUK+mVblyx84vW2SeVY5QZy60zlIJz2wx7cX0+yd rkVAIRmucXcwDd4YT5gZiCfPXph0C0GRIHlefalSOG1dyJmH7NaO1YezdfSqtFcQ ksCBFB+VUUZlslxd3hd9fj9Hj4sDoaqH8U2v4/6uT1nuD+ujoP4nKKgf+tapn1Zu JhEzApiv+Yr22n8DhZMiBs8F7toldlUmN4lIDEkq2PqnXxYYTZ7FpNLKRofXlxAE NKVKm4RWGMjWLl4i9svKOyKwh9VzktxwOxlZBVqYMWDmV/LLm0+394VIRcbAA6Ij IOqjJzWxidSTDHjF9wM9aCT/BfnqynBULRpqStyjEZZyBg51ei8= =tdEq -----END PGP SIGNATURE----- Merge tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.15 1. Google GS101: - Disable GSA core pinctrl because its registers are not available for normal world. - Add APM (Active Power Management) mailbox and the ACPM firmware nodes. - Add new boards: Google Pixel 6 Pro (Raven). - Enable framebuffer and reboot-mode. 2. Exynos990: - Add PERIS clock controller, MCT timer 3. Exynos8895: - Define all remaining serial engine (USI) and syscon nodes, add MMC. - Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte). 4. ExynosAutov920: Add UFS and CPU cache information. 5. Various cleanups. This includes two topic branches with DT bindings, which might be shared with other trees depending on needs: 1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller header constants. 2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines header constants rework. * tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits) arm64: dts: tesla: Change labels to lower-case arm64: dts: exynos: gs101: Change labels to lower-case arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC arm64: dts: exynosautov920: add CPU cache information arm64: dts: exynos: gs101: add ACPM protocol node arm64: dts: exynos: gs101: add AP to APM mailbox node arm64: dts: exynos: gs101: add SRAM node arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0) arm64: dts: exynos: gs101: align poweroff writes with downstream arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes arm64: dts: exynos8895: Rename PMU nodes to fixup sorting arm64: dts: exynos8895-dreamlte: enable support for the touchscreen arm64: dts: exynos8895-dreamlte: enable support for microSD storage arm64: dts: exynos8895: add a node for mmc arm64: dts: exynos8895: define all usi nodes arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1 arm64: dts: exynos990: Rename and sort PMU nodes arm64: dts: exynos990: Add CMU_PERIS and MCT nodes dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi dt-bindings: clock: exynos990: Add CMU_PERIS block ... Link: https://lore.kernel.org/r/20250309185601.10616-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-03-14 18:47:13 +01:00
Arnd Bergmann	d1221aeb5a	New boards: MNT-Reform2 laptop (rk3588), OrangePi5-Ultra (rk3588), Radxa Rock 4D (rk3576), Firefly ROC-RK3576-PC, Photonicat (rk3568) New overlays: Video-adapters for Theobroma boards and one adapter used in hw test scenarios. Interesting bigger changes contain clock support for rk3528; support for the hdmi1 controller as well as hdmi-audio support on both controllers on rk3588; the hdmi-receiver of the rk3588 landed, and rk3576 got basic graphics support and can now do hdmi output. Another big block is that we're now doing overlays way better and are including build-testing for applied overlays to the base dtb - similar to how other arches already do this. Of cours a big list of more controllers for rk3576 (nvmem, sfc), rk3588 (rng, spdif, regulator for gpu power-domain) and rk3528 (saradc, pinctrl) And a huge number of board-level improvements and additions. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmfMhrcQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgS+yCACGOX4BatsdndoOWcr+SeySPVq8CWGONLyk WPPFC/2JA/a+oFr1YurPZW3+mVfL1ZVauqO7NZluE+6CJOc8+FqobkMOIvJJv15J jqhGGFLy83IUVwErgGpaxtwQNNPoQahSJuEDmv161knThRaTIjW1w/nrVcEMhSWp YX73mKQcV2jUbQC/wfJzcryhAA5WJP4NGkPhO34PEyASiSbxsCpHIrWaZb1/EfBP 4nI6mSr1FpQgNsByUQPlSTbN5Yja9/BBWRZ42MIIyPlKKw/TqnMcW4eeHqhA5DS8 nNbZpHnc0Oz6SPAgSSQj0RYRf2UhubxH46ileWBuMf7IG049Sl/J =yF4g -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfUas0ACgkQYKtH/8kJ UicarRAAuLrdhmWzSJCLo+Cot4LUzh8+l9DRpsmr++wkUyHDpDY/n6y78xqPpPE/ 6Xq2PiVRypr7A/4wQn+7zYFjujlMYTceyMGGoyMwh3iQXD/u4OrEtHlOir1YEPS9 zEf7c7Lk6e0WgA1S4tTbKkH7OK7+M8S9fiFW9UCXTvK9+Xp1CjXSKuDlHqvXqDOs HQtZ587868iYj05hBgLavD0Wucedo+ntuYGMnF0a3zPf2m2q4dc5irdoAAVpwMyJ LhCt59rSR0ZfqviW/pgOg1d5B86cVDzi4CCB6b81MQnE0T0/B19lt68nwB8b+Yu0 MqKoIGt3WWN0SJH4taTt0VGwSwKqtymqyVl1bemCwNwxT5cNmRqcQCxaglTKInQg RBkPuxK//HnknD1nHtWBi47iBpCQW88waG91WivY2iaJCa317C3B+m76iMdBIDGR ZkjymDjtrEHekJuyJH4ksDqyR0FI/WPWotO9Xpa0yscm92N3Ld/ghqtUw7guDy97 cdSLl4HYSl5cM3eWlBuyeq4pvFnWQ8IXObO4UdoNYNBS/cE9rV/OYqiXxoRAEVey i3gUsgHtcmyfVnnqGuFC/6obC9LGWJq4xnyccsPERI6dEDERhjCx9xNjUuxblfT5 kNzxBK8a8FpSoQjJ47nJat/xMIwPoWBlOsGp7joKcRYBXmgGChs= =EFnK -----END PGP SIGNATURE----- Merge tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: MNT-Reform2 laptop (rk3588), OrangePi5-Ultra (rk3588), Radxa Rock 4D (rk3576), Firefly ROC-RK3576-PC, Photonicat (rk3568) New overlays: Video-adapters for Theobroma boards and one adapter used in hw test scenarios. Interesting bigger changes contain clock support for rk3528; support for the hdmi1 controller as well as hdmi-audio support on both controllers on rk3588; the hdmi-receiver of the rk3588 landed, and rk3576 got basic graphics support and can now do hdmi output. Another big block is that we're now doing overlays way better and are including build-testing for applied overlays to the base dtb - similar to how other arches already do this. Of cours a big list of more controllers for rk3576 (nvmem, sfc), rk3588 (rng, spdif, regulator for gpu power-domain) and rk3528 (saradc, pinctrl) And a huge number of board-level improvements and additions. * tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (89 commits) arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D arm64: dts: rockchip: Add SFC nodes for rk3576 arm64: dts: rockchip: Add maskrom button to Radxa E20C arm64: dts: rockchip: Add SARADC node for RK3528 arm64: dts: rockchip: Add user button to Radxa E20C arm64: dts: rockchip: Add leds node to Radxa E20C arm64: dts: rockchip: Add HDMI support for rock-4d arm64: dts: rockchip: enable SCMI clk for RK3528 SoC arm64: dts: rockchip: Enable HDMI receiver on rock-5b arm64: dts: rockchip: Add device tree support for HDMI RX Controller arm64: dts: rockchip: Add rk3528 QoS register node dt-bindings: mfd: syscon: Add rk3528 QoS register compatible arm64: dts: rockchip: add MNT Reform 2 laptop dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE) dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10 arm64: dts: rockchip: Enable hdmi display on sige5 arm64: dts: rockchip: Add hdmi for rk3576 arm64: dts: rockchip: Add vop for rk3576 ... Link: https://lore.kernel.org/r/13791512.uLZWGnKmhe@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-03-14 18:43:41 +01:00
Wolfram Sang	86484e08d8	dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles The driver support more SoCs. Add the missing ones. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250213092728.11659-2-wsa+renesas@sang-engineering.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-03-13 18:01:58 -07:00
Taniya Das	c16e576b8a	dt-bindings: clock: qcom: Add compatible for QCM6490 boards On the QCM6490 boards, the LPASS firmware controls the complete clock controller functionalities and associated power domains. However, only the LPASS resets required to be controlled by the high level OS. Thus, add the new QCM6490 compatible to support the reset functionality for Low Power Audio subsystem. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250221-lpass_qcm6490_resets-v5-1-6be0c0949a83@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-03-13 16:45:22 -05:00
Andreas Kemnade	944b074ff1	dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema Convert the TI clkctrl clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. reg property is used mostly with one item, in am3xxx also with an arbitrary number of items, so divert from the original binding specifying two (probably meaning one address and one size). The consumer part of the example is left out because the full consumer node would be needed. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250311180215.173634-1-andreas@kemnade.info Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-03-13 13:16:31 -07:00
Andre Przywara	52dbf84857	dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for the main and the PRCM R-CCU. The source clock list differs in some annoying details, and folding this into the existing Allwinner CCU clock binding document gets quite unwieldy, so create a new document for these CCUs. Add the new compatible string, along with the required input clock lists. This conditionally describes the input clock lists, to make adding support for the other two CCUs easier. Also add the DT binding headers, listing all the clocks with their ID numbers. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>	2025-03-12 11:58:09 +08:00
Vladimir Zapolskiy	53fc6fe160	dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover Qualcomm x1e80100-camcc was moved to its own dt bindings description file, however a small leftover was left, remove it. Fixes: `7ec95ff9ab` ("dt-bindings: clock: move qcom,x1e80100-camcc to its own file") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20250303223936.1780441-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-03-03 22:29:18 -06:00
Ahmad Fatoum	d5992f1af1	dt-bindings: clock: imx8m: document nominal/overdrive properties The imx8m-clock.yaml binding covers the clock controller inside all of the i.MX8M Q/M/N/P SoCs. All of them have in common that they support two operating modes: nominal and overdrive mode. While the overdrive mode allows for higher frequencies for many IPs, the nominal mode needs a lower SoC voltage, thereby reducing heat generation and power usage. As increasing clock rates beyond the maximum permitted by the supplied SoC voltage can lead to difficult to debug issues, device tree consumers would benefit from knowing what mode is active to enforce the clock rate limits that come with it. To facilitate this, extend the clock controller bindings with an optional fsl,operating-mode property. This intentionally allows the absence of the property, because there is no default suitable for all boards: For i.MX8M Mini and Nano, the kernel SoC DTSIs has assigned-clock-rates that are all achievable in nominal mode. For i.MX8MP, there are some rates only validated for overdrive mode. But even for the i.MX8M Mini/Nano boards, we don't know what rates they may configure at runtime, so it has not been possible so far to infer from just the device tree what the mode is. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.kernel.org/r/20250218-imx8m-clk-v4-1-b7697dc2dcd0@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2025-03-03 19:02:06 +02:00

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2370 Commits