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dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain

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To configure the video PLLs and enable the video GDSCs on SM8450,
SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
with MMCX. Therefore, update the videocc bindings to include
the MXC power domain on these platforms.

Fixes: 1e910b2ba0 ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Jagadeesh Kona 2025-05-30 18:50:46 +05:30 committed by Bjorn Andersson
parent 19272b37aa
commit 1a42f4d4bb
1 changed files with 12 additions and 6 deletions
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18
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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@ -32,14 +32,18 @@ properties:
- description: Video AHB clock from GCC
power-domains:
maxItems: 1
description:
MMCX power domain.
Power domains required for the clock controller to operate
items:
- description: MMCX power domain
- description: MXC power domain
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
OPP nodes that describe required performance points on power domains
items:
- description: MMCX performance point
- description: MXC performance point
required:
- compatible
@ -72,8 +76,10 @@ examples:
reg = <0x0aaf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;