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dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

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Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC.  The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2025-06-09 21:36:51 +01:00 committed by Geert Uytterhoeven
parent b59b3f6882
commit 292bf6c5b8
2 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View File

@ -53,6 +53,7 @@ properties:
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
- renesas,r9a09g077-cpg-mssr # RZ/T2H
- renesas,r9a09g087-cpg-mssr # RZ/N2H
reg:
minItems: 1
@ -112,7 +113,9 @@ allOf:
properties:
compatible:
contains:
const: renesas,r9a09g077-cpg-mssr
enum:
- renesas,r9a09g077-cpg-mssr
- renesas,r9a09g087-cpg-mssr
then:
properties:
reg:

28
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A09G087 CPG Core Clocks */
#define R9A09G087_CLK_CA55C0 0
#define R9A09G087_CLK_CA55C1 1
#define R9A09G087_CLK_CA55C2 2
#define R9A09G087_CLK_CA55C3 3
#define R9A09G087_CLK_CA55S 4
#define R9A09G087_CLK_CR52_CPU0 5
#define R9A09G087_CLK_CR52_CPU1 6
#define R9A09G087_CLK_CKIO 7
#define R9A09G087_CLK_PCLKAH 8
#define R9A09G087_CLK_PCLKAM 9
#define R9A09G087_CLK_PCLKAL 10
#define R9A09G087_CLK_PCLKGPTL 11
#define R9A09G087_CLK_PCLKH 12
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */