github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-26 16:12:59 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Samsung DTS ARM64 changes for v6.15

Browse Source 
1. Google GS101:
  - Disable GSA core pinctrl because its registers are not available for
    normal world.
  - Add APM (Active Power Management) mailbox and the ACPM firmware nodes.
  - Add new boards: Google Pixel 6 Pro (Raven).
  - Enable framebuffer and reboot-mode.
 
 2. Exynos990:
  - Add PERIS clock controller, MCT timer
 
 3. Exynos8895:
  - Define all remaining serial engine (USI) and syscon nodes, add MMC.
  - Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte).
 
 4. ExynosAutov920: Add UFS and CPU cache information.
 
 5. Various cleanups.
 
 This includes two topic branches with DT bindings, which might be shared
 with other trees depending on needs:
 1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller
    header constants.
 2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines
    header constants rework.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmfN4bEQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD1wy7EACAh54/LUmLUP2RDSVPAXsYXkyiL+xbvdWQ
 Twa0rp6szLxfuTxQgH3oPGKuQ9f/zHJ+ZgXzf5gTUDlIxhvY2TCoKTNKbEaobDSW
 pCRoBKYogpqeJ7UBC9uTwZlWvI6flbgb7riFYUa2sOFbwCid0rvlo/TeqR8OTuWj
 NkYI6jfjRWD9qbriW+B9xPW2tgb+jMQGlUKDbDcaF9TRK4XEhLmHiQWudnUXbdSR
 LuJgBu7+T0CRwiUymp3IMeNK8Qxcv/2MdqYHZjIwX2S4Ftv2u+JbRBViUROOsEQX
 Rd8LztrLtyyRiqS4Jchc29XPDAEiiWIkJhbdJW5k3Kffk2ADAQznQSgSYhQ7kdzB
 nAKhGOstCITUnec9nQuS/hzT7wnpOkpBjRCiZfdKV66Rp2b32rDcNskwvUaRu1oV
 lclzHJWnGQRtTNQ2AQBE4t4Cl+79UopO1r5Y4F4q4VM5zTcp4VttLJdt4NQIq6Mk
 mgSC8U9aa4YmB+wWthTIaASXI2ml4xj/DA75QdBbIgVNNvyJPiaFQvBsJW1jQ5E9
 ZzScu9nju3SjOezDtEZLk3aLRrE8D8bB9lWYveim7m3HsmVFTsYBqrr8uWJrlwma
 kzqPOlLSzVgEomM7mRC/OgjVg70ds6krDR+sDhYC3y0w0Xdgx9nwIKFDGBLBO0QQ
 p0225H4AGA==
 =RKN2
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfUa6EACgkQYKtH/8kJ
 UieFAhAAyE7m6jdNTkJStfCQjIXHbxdi6yKogmkduUpZzcIm0Wb5yShey6Sv6Boc
 HLLI8QG56o81pKshhn4yJSfphT7M0gSauhvEBl8xAgli6ysZ9MGhRaL+OqM2xvPO
 6x2csEpWEvKSLjtrFWOUg9F0szParJh29DwjzM9xapjjLG2UB2+pLgNYOCAy4xt8
 2cRUbTCIHM2AwfNL1wRIJG07Ji68QLCQAiPnuLBzUnvm4xvDxk6QXNcS1+kHLalS
 /AdPGsOPrcnll2b5uuvcysmSmRdN2urUCLMWx1dBed3JqmsSwXVGW7IdV0i0c4da
 cwPDkwu6IVM+fAV225DSwQ7TDUK+mVblyx84vW2SeVY5QZy60zlIJz2wx7cX0+yd
 rkVAIRmucXcwDd4YT5gZiCfPXph0C0GRIHlefalSOG1dyJmH7NaO1YezdfSqtFcQ
 ksCBFB+VUUZlslxd3hd9fj9Hj4sDoaqH8U2v4/6uT1nuD+ujoP4nKKgf+tapn1Zu
 JhEzApiv+Yr22n8DhZMiBs8F7toldlUmN4lIDEkq2PqnXxYYTZ7FpNLKRofXlxAE
 NKVKm4RWGMjWLl4i9svKOyKwh9VzktxwOxlZBVqYMWDmV/LLm0+394VIRcbAA6Ij
 IOqjJzWxidSTDHjF9wM9aCT/BfnqynBULRpqStyjEZZyBg51ei8=
 =tdEq
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v6.15

1. Google GS101:
 - Disable GSA core pinctrl because its registers are not available for
   normal world.
 - Add APM (Active Power Management) mailbox and the ACPM firmware nodes.
 - Add new boards: Google Pixel 6 Pro (Raven).
 - Enable framebuffer and reboot-mode.

2. Exynos990:
 - Add PERIS clock controller, MCT timer

3. Exynos8895:
 - Define all remaining serial engine (USI) and syscon nodes, add MMC.
 - Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte).

4. ExynosAutov920: Add UFS and CPU cache information.

5. Various cleanups.

This includes two topic branches with DT bindings, which might be shared
with other trees depending on needs:
1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller
   header constants.
2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines
   header constants rework.

* tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits)
  arm64: dts: tesla: Change labels to lower-case
  arm64: dts: exynos: gs101: Change labels to lower-case
  arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC
  arm64: dts: exynosautov920: add CPU cache information
  arm64: dts: exynos: gs101: add ACPM protocol node
  arm64: dts: exynos: gs101: add AP to APM mailbox node
  arm64: dts: exynos: gs101: add SRAM node
  arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
  arm64: dts: exynos: gs101: align poweroff writes with downstream
  arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes
  arm64: dts: exynos8895: Rename PMU nodes to fixup sorting
  arm64: dts: exynos8895-dreamlte: enable support for the touchscreen
  arm64: dts: exynos8895-dreamlte: enable support for microSD storage
  arm64: dts: exynos8895: add a node for mmc
  arm64: dts: exynos8895: define all usi nodes
  arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1
  arm64: dts: exynos990: Rename and sort PMU nodes
  arm64: dts: exynos990: Add CMU_PERIS and MCT nodes
  dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi
  dt-bindings: clock: exynos990: Add CMU_PERIS block
  ...

Link: https://lore.kernel.org/r/20250309185601.10616-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-14 18:47:08 +01:00
commit 56beaf1444
15 changed files with 1721 additions and 379 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/arm/google.yaml
View File

@ -34,10 +34,11 @@ properties:
const: '/'
compatible:
oneOf:
- description: Google Pixel 6 / Oriole
- description: Google Pixel 6 or 6 Pro (Oriole or Raven)
items:
- enum:
- google,gs101-oriole
- google,gs101-raven
- const: google,gs101
# Bootloader requires empty ect node to be present

19
Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
View File

@ -31,6 +31,7 @@ properties:
compatible:
enum:
- samsung,exynos990-cmu-hsi0
- samsung,exynos990-cmu-peris
- samsung,exynos990-cmu-top
clocks:
@ -79,6 +80,24 @@ allOf:
- const: usbdp_debug
- const: dpgtc
- if:
properties:
compatible:
contains:
const: samsung,exynos990-cmu-peris
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIS BUS clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- if:
properties:
compatible:

99
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
View File

@ -11,11 +11,21 @@ maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
USI shares almost all internal circuits within each protocol, so only one
protocol can be chosen at a time. USI is modeled as a node with zero or more
child nodes, each representing a serial sub-node device. The mode setting
selects which particular function will be used.
The USI IP-core provides configurable support for serial protocols, enabling
different serial communication modes depending on the version.
In USIv1, configurations are available to enable either one or two protocols
simultaneously in select combinations - High-Speed I2C0, High-Speed
I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed
I2C1 and UART.
In USIv2, only one protocol can be active at a time, either UART, SPI, or
High-Speed I2C.
The USI core shares internal circuits across protocols, meaning only the
selected configuration is active at any given time. USI is modeled as a node
with zero or more child nodes, each representing a serial sub-node device. The
mode setting selects which particular function will be used.
properties:
$nodename:
@ -31,6 +41,7 @@ properties:
- const: samsung,exynos850-usi
- enum:
- samsung,exynos850-usi
- samsung,exynos8895-usi
reg:
maxItems: 1
@ -64,7 +75,7 @@ properties:
samsung,mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
enum: [0, 1, 2, 3, 4, 5, 6]
description:
Selects USI function (which serial protocol to use). Refer to
<include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
@ -101,37 +112,59 @@ required:
- samsung,sysreg
- samsung,mode
if:
properties:
compatible:
contains:
enum:
- samsung,exynos850-usi
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos850-usi
then:
properties:
reg:
maxItems: 1
then:
properties:
reg:
maxItems: 1
clocks:
items:
- description: Bus (APB) clock
- description: Operating clock for UART/SPI/I2C protocol
clocks:
items:
- description: Bus (APB) clock
- description: Operating clock for UART/SPI/I2C protocol
clock-names:
maxItems: 2
clock-names:
maxItems: 2
required:
- reg
- clocks
- clock-names
samsung,mode:
enum: [0, 1, 2, 3]
else:
properties:
reg: false
clocks: false
clock-names: false
samsung,clkreq-on: false
required:
- reg
- clocks
- clock-names
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos8895-usi
then:
properties:
reg: false
clocks:
items:
- description: Bus (APB) clock
- description: Operating clock for UART/SPI protocol
clock-names:
maxItems: 2
samsung,clkreq-on: false
required:
- clocks
- clock-names
additionalProperties: false
@ -144,7 +177,7 @@ examples:
compatible = "samsung,exynos850-usi";
reg = <0x138200c0 0x20>;
samsung,sysreg = <&sysreg_peri 0x1010>;
samsung,mode = <USI_V2_UART>;
samsung,mode = <USI_MODE_UART>;
samsung,clkreq-on; /* needed for UART mode */
#address-cells = <1>;
#size-cells = <1>;

72
arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts
View File

@ -10,12 +10,17 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>
/ {
model = "Samsung Galaxy S8 (SM-G950F)";
compatible = "samsung,dreamlte", "samsung,exynos8895";
chassis-type = "handset";
aliases {
mmc0 = &mmc;
};
chosen {
#address-cells = <2>;
#size-cells = <1>;
@ -89,12 +94,60 @@ wink-key {
wakeup-source;
};
};
/* TODO: Remove once PMIC is implemented */
reg_placeholder: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "reg-placeholder";
};
};
&hsi2c_23 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
touchscreen@48 {
compatible = "samsung,s6sy761";
reg = <0x48>;
/* TODO: Update once PMIC is implemented */
avdd-supply = <&reg_placeholder>;
vdd-supply = <&reg_placeholder>;
interrupt-parent = <&gpa1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&ts_int>;
pinctrl-names = "default";
};
};
&oscclk {
clock-frequency = <26000000>;
};
&mmc {
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &sd2_cd>;
pinctrl-names = "default";
bus-width = <4>;
card-detect-delay = <200>;
cd-gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
clock-frequency = <800000000>;
disable-wp;
sd-uhs-sdr50;
sd-uhs-sdr104;
/* TODO: Add regulators once PMIC is implemented */
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-ddr-timing = <1 2>;
samsung,dw-mshc-sdr-timing = <0 3>;
status = "okay";
};
&pinctrl_alive {
key_power: key-power-pins {
samsung,pins = "gpa2-4";
@ -123,4 +176,23 @@ key_wink: key-wink-pins {
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
};
sd2_cd: sd2-cd-pins {
samsung,pins = "gpa1-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
};
ts_int: ts-int-pins {
samsung,pins = "gpa1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
};
};
&usi9 {
samsung,mode = <USI_MODE_I2C0_1>;
status = "okay";
};

956
arch/arm64/boot/dts/exynos/exynos8895.dtsi
View File

File diff suppressed because it is too large Load Diff

92
arch/arm64/boot/dts/exynos/exynos990.dtsi
View File

@ -25,37 +25,6 @@ aliases {
pinctrl6 = &pinctrl_vts;
};
arm-a55-pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
arm-a76-pmu {
compatible = "arm,cortex-a76-pmu";
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>,
<&cpu5>;
};
mongoose-m5-pmu {
compatible = "samsung,mongoose-pmu";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu6>,
<&cpu7>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -163,6 +132,37 @@ oscclk: clock-osc {
clock-output-names = "oscclk";
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>,
<&cpu5>;
};
pmu-mongoose-m5 {
compatible = "samsung,mongoose-pmu";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu6>,
<&cpu7>;
};
psci {
compatible = "arm,psci-0.2";
method = "hvc";
@ -181,6 +181,36 @@ chipid@10000000 {
reg = <0x10000000 0x100>;
};
cmu_peris: clock-controller@10020000 {
compatible = "samsung,exynos990-cmu-peris";
reg = <0x10020000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
clock-names = "oscclk", "bus";
};
timer@10040000 {
compatible = "samsung,exynos990-mct",
"samsung,exynos4210-mct";
reg = <0x10040000 0x800>;
clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10101000 {
compatible = "arm,gic-400";
reg = <0x10101000 0x1000>,

138
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
View File

@ -89,6 +89,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x0>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl0>;
};
cpu1: cpu@100 {
@ -96,6 +103,13 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x100>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl0>;
};
cpu2: cpu@200 {
@ -103,6 +117,13 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x200>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl0>;
};
cpu3: cpu@300 {
@ -110,6 +131,13 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x300>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl0>;
};
cpu4: cpu@10000 {
@ -117,6 +145,13 @@ cpu4: cpu@10000 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10000>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl1>;
};
cpu5: cpu@10100 {
@ -124,6 +159,13 @@ cpu5: cpu@10100 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10100>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl1>;
};
cpu6: cpu@10200 {
@ -131,6 +173,13 @@ cpu6: cpu@10200 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10200>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl1>;
};
cpu7: cpu@10300 {
@ -138,6 +187,13 @@ cpu7: cpu@10300 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10300>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl1>;
};
cpu8: cpu@20000 {
@ -145,6 +201,13 @@ cpu8: cpu@20000 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x20000>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl2>;
};
cpu9: cpu@20100 {
@ -152,6 +215,70 @@ cpu9: cpu@20100 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x20100>;
enable-method = "psci";
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_cl2>;
};
l2_cache_cl0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache_cl0>;
};
l2_cache_cl1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache_cl1>;
};
l2_cache_cl2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache_cl2>;
};
l3_cache_cl0: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
cache-line-size = <64>;
cache-sets = <2048>;
};
l3_cache_cl1: l3-cache1 {
compatible = "cache";
cache-level = <3>;
cache-unified;
cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
cache-line-size = <64>;
cache-sets = <2048>;
};
l3_cache_cl2: l3-cache2 {
compatible = "cache";
cache-level = <3>;
cache-unified;
cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
cache-line-size = <64>;
cache-sets = <1365>;
};
};
@ -440,6 +567,17 @@ pinctrl_hsi2ufs: pinctrl@16d20000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
};
ufs_0_phy: phy@16e04000 {
compatible = "samsung,exynosautov920-ufs-phy";
reg = <0x16e04000 0x4000>;
reg-names = "phy-pma";
clocks = <&xtcxo>;
clock-names = "ref_clk";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <0>;
status = "disabled";
};
pinctrl_aud: pinctrl@1a460000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x1a460000 0x10000>;

1
arch/arm64/boot/dts/exynos/google/Makefile
View File

@ -2,3 +2,4 @@
dtb-$(CONFIG_ARCH_EXYNOS) += \
gs101-oriole.dtb \
gs101-raven.dtb

267
arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
View File

@ -8,273 +8,22 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/usb/pd.h>
#include "gs101-pinctrl.h"
#include "gs101.dtsi"
#include "gs101-pixel-common.dtsi"
/ {
model = "Oriole";
compatible = "google,gs101-oriole", "google,gs101";
aliases {
serial0 = &serial_0;
};
chosen {
/* Bootloader expects bootargs specified otherwise it crashes */
bootargs = "";
stdout-path = &serial_0;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>;
pinctrl-names = "default";
button-vol-down {
label = "KEY_VOLUMEDOWN";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-vol-up {
label = "KEY_VOLUMEUP";
linux,code = <KEY_VOLUMEUP>;
gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-power {
label = "KEY_POWER";
linux,code = <KEY_POWER>;
gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
/* TODO: Remove this once PMIC is implemented */
reg_placeholder: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "placeholder_reg";
};
/* TODO: Remove this once S2MPG11 slave PMIC is implemented */
ufs_0_fixed_vcc_reg: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "ufs-vcc";
gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
enable-active-high;
};
};
&ext_24_5m {
clock-frequency = <24576000>;
};
&ext_200m {
clock-frequency = <200000000>;
};
&hsi2c_8 {
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&hsi2c_12 {
status = "okay";
/* TODO: add the devices once drivers exist */
usb-typec@25 {
compatible = "maxim,max77759-tcpci", "maxim,max33359";
reg = <0x25>;
interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&typec_int>;
pinctrl-names = "default";
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
self-powered;
try-power-role = "sink";
op-sink-microwatt = <2600000>;
slow-charger-loop;
/*
* max77759 operating in reverse boost mode (0xA) can
* source up to 1.5A while extboost can only do ~1A.
* Since extboost is the primary path, advertise 900mA.
*/
source-pdos = <PDO_FIXED(5000, 900,
(PDO_FIXED_SUSPEND
| PDO_FIXED_USB_COMM
| PDO_FIXED_DATA_SWAP
| PDO_FIXED_DUAL_ROLE))>;
sink-pdos = <PDO_FIXED(5000, 3000,
(PDO_FIXED_DATA_SWAP
| PDO_FIXED_USB_COMM
| PDO_FIXED_HIGHER_CAP
| PDO_FIXED_DUAL_ROLE))
PDO_FIXED(9000, 2200, 0)
PDO_PPS_APDO(5000, 11000, 3000)>;
sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
IDH_PTYPE_DFP_HOST, 2, 0x18d1)
VDO_CERT(0x0)
VDO_PRODUCT(0x4ee1, 0x0)
VDO_UFP(UFP_VDO_VER1_2,
(DEV_USB2_CAPABLE
| DEV_USB3_CAPABLE),
UFP_RECEPTACLE, 0,
AMA_VCONN_NOT_REQ, 0,
UFP_ALTMODE_NOT_SUPP,
UFP_USB32_GEN1)
/* padding */ 0
VDO_DFP(DFP_VDO_VER1_1,
(HOST_USB2_CAPABLE
| HOST_USB3_CAPABLE),
DFP_RECEPTACLE, 0)>;
sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
0, 0, 0x18d1)
VDO_CERT(0x0)
VDO_PRODUCT(0x4ee1, 0x0)>;
/*
* Until bootloader is updated to set those two when
* console is enabled, we disable PD here.
*/
pd-disable;
typec-power-opmode = "default";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdrd31_phy_orien_switch>;
};
};
port@1 {
reg = <1>;
usbc0_role_sw: endpoint {
remote-endpoint = <&usbdrd31_dwc3_role_switch>;
};
};
};
};
};
};
&pinctrl_far_alive {
key_voldown: key-voldown-pins {
samsung,pins = "gpa7-3";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
key_volup: key-volup-pins {
samsung,pins = "gpa8-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
typec_int: typec-int-pins {
samsung,pins = "gpa8-2";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_UP>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
};
&pinctrl_gpio_alive {
key_power: key-power-pins {
samsung,pins = "gpa10-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
};
&serial_0 {
&cont_splash_mem {
reg = <0x0 0xfac00000 (1080 * 2400 * 4)>;
status = "okay";
};
&ufs_0 {
status = "okay";
vcc-supply = <&ufs_0_fixed_vcc_reg>;
};
&ufs_0_phy {
status = "okay";
};
&usbdrd31 {
vdd10-supply = <&reg_placeholder>;
vdd33-supply = <&reg_placeholder>;
status = "okay";
};
&usbdrd31_dwc3 {
dr_mode = "otg";
usb-role-switch;
role-switch-default-mode = "peripheral";
maximum-speed = "super-speed-plus";
status = "okay";
port {
usbdrd31_dwc3_role_switch: endpoint {
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd31_phy {
orientation-switch;
/* TODO: Update these once PMIC is implemented */
pll-supply = <&reg_placeholder>;
dvdd-usb20-supply = <&reg_placeholder>;
vddh-usb20-supply = <&reg_placeholder>;
vdd33-usb20-supply = <&reg_placeholder>;
vdda-usbdp-supply = <&reg_placeholder>;
vddh-usbdp-supply = <&reg_placeholder>;
status = "okay";
port {
usbdrd31_phy_orien_switch: endpoint {
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
};
&usi8 {
samsung,mode = <USI_V2_I2C>;
status = "okay";
};
&usi12 {
samsung,mode = <USI_V2_I2C>;
status = "okay";
};
&watchdog_cl0 {
timeout-sec = <30>;
&framebuffer0 {
width = <1080>;
height = <2400>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
status = "okay";
};

294
arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi Normal file
View File

@ -0,0 +1,294 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree nodes common for all GS101-based Pixel
*
* Copyright 2021-2023 Google LLC
* Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/usb/pd.h>
#include "gs101-pinctrl.h"
#include "gs101.dtsi"
/ {
aliases {
serial0 = &serial_0;
};
chosen {
/* Bootloader expects bootargs specified otherwise it crashes */
bootargs = "";
stdout-path = &serial_0;
/* Use display framebuffer as setup by bootloader */
framebuffer0: framebuffer-0 {
compatible = "simple-framebuffer";
memory-region = <&cont_splash_mem>;
/* format properties to be added by actual board */
status = "disabled";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>;
pinctrl-names = "default";
button-vol-down {
label = "KEY_VOLUMEDOWN";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-vol-up {
label = "KEY_VOLUMEUP";
linux,code = <KEY_VOLUMEUP>;
gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-power {
label = "KEY_POWER";
linux,code = <KEY_POWER>;
gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
/* TODO: Remove this once PMIC is implemented */
reg_placeholder: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "placeholder_reg";
};
/* TODO: Remove this once S2MPG11 slave PMIC is implemented */
ufs_0_fixed_vcc_reg: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "ufs-vcc";
gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
enable-active-high;
};
reserved-memory {
cont_splash_mem: splash@fac00000 {
/* size to be updated by actual board */
reg = <0x0 0xfac00000 0x0>;
no-map;
status = "disabled";
};
};
};
&ext_24_5m {
clock-frequency = <24576000>;
};
&ext_200m {
clock-frequency = <200000000>;
};
&hsi2c_8 {
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&hsi2c_12 {
status = "okay";
/* TODO: add the devices once drivers exist */
usb-typec@25 {
compatible = "maxim,max77759-tcpci", "maxim,max33359";
reg = <0x25>;
interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&typec_int>;
pinctrl-names = "default";
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
self-powered;
try-power-role = "sink";
op-sink-microwatt = <2600000>;
slow-charger-loop;
/*
* max77759 operating in reverse boost mode (0xA) can
* source up to 1.5A while extboost can only do ~1A.
* Since extboost is the primary path, advertise 900mA.
*/
source-pdos = <PDO_FIXED(5000, 900,
(PDO_FIXED_SUSPEND
| PDO_FIXED_USB_COMM
| PDO_FIXED_DATA_SWAP
| PDO_FIXED_DUAL_ROLE))>;
sink-pdos = <PDO_FIXED(5000, 3000,
(PDO_FIXED_DATA_SWAP
| PDO_FIXED_USB_COMM
| PDO_FIXED_HIGHER_CAP
| PDO_FIXED_DUAL_ROLE))
PDO_FIXED(9000, 2200, 0)
PDO_PPS_APDO(5000, 11000, 3000)>;
sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
IDH_PTYPE_DFP_HOST, 2, 0x18d1)
VDO_CERT(0x0)
VDO_PRODUCT(0x4ee1, 0x0)
VDO_UFP(UFP_VDO_VER1_2,
(DEV_USB2_CAPABLE
| DEV_USB3_CAPABLE),
UFP_RECEPTACLE, 0,
AMA_VCONN_NOT_REQ, 0,
UFP_ALTMODE_NOT_SUPP,
UFP_USB32_GEN1)
/* padding */ 0
VDO_DFP(DFP_VDO_VER1_1,
(HOST_USB2_CAPABLE
| HOST_USB3_CAPABLE),
DFP_RECEPTACLE, 0)>;
sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
0, 0, 0x18d1)
VDO_CERT(0x0)
VDO_PRODUCT(0x4ee1, 0x0)>;
/*
* Until bootloader is updated to set those two when
* console is enabled, we disable PD here.
*/
pd-disable;
typec-power-opmode = "default";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdrd31_phy_orien_switch>;
};
};
port@1 {
reg = <1>;
usbc0_role_sw: endpoint {
remote-endpoint = <&usbdrd31_dwc3_role_switch>;
};
};
};
};
};
};
&pinctrl_far_alive {
key_voldown: key-voldown-pins {
samsung,pins = "gpa7-3";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
key_volup: key-volup-pins {
samsung,pins = "gpa8-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
typec_int: typec-int-pins {
samsung,pins = "gpa8-2";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_UP>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
};
&pinctrl_gpio_alive {
key_power: key-power-pins {
samsung,pins = "gpa10-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
};
&serial_0 {
status = "okay";
};
&ufs_0 {
status = "okay";
vcc-supply = <&ufs_0_fixed_vcc_reg>;
};
&ufs_0_phy {
status = "okay";
};
&usbdrd31 {
vdd10-supply = <&reg_placeholder>;
vdd33-supply = <&reg_placeholder>;
status = "okay";
};
&usbdrd31_dwc3 {
dr_mode = "otg";
usb-role-switch;
role-switch-default-mode = "peripheral";
maximum-speed = "super-speed-plus";
status = "okay";
port {
usbdrd31_dwc3_role_switch: endpoint {
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd31_phy {
orientation-switch;
/* TODO: Update these once PMIC is implemented */
pll-supply = <&reg_placeholder>;
dvdd-usb20-supply = <&reg_placeholder>;
vddh-usb20-supply = <&reg_placeholder>;
vdd33-usb20-supply = <&reg_placeholder>;
vdda-usbdp-supply = <&reg_placeholder>;
vddh-usbdp-supply = <&reg_placeholder>;
status = "okay";
port {
usbdrd31_phy_orien_switch: endpoint {
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
};
&usi8 {
samsung,mode = <USI_V2_I2C>;
status = "okay";
};
&usi12 {
samsung,mode = <USI_V2_I2C>;
status = "okay";
};
&watchdog_cl0 {
timeout-sec = <30>;
status = "okay";
};

29
arch/arm64/boot/dts/exynos/google/gs101-raven.dts Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Raven Device Tree
*
* Copyright 2021-2023 Google LLC
* Copyright 2023-2025 Linaro Ltd
*/
/dts-v1/;
#include "gs101-pixel-common.dtsi"
/ {
model = "Raven";
compatible = "google,gs101-raven", "google,gs101";
};
&cont_splash_mem {
reg = <0x0 0xfac00000 (1440 * 3120 * 4)>;
status = "okay";
};
&framebuffer0 {
width = <1440>;
height = <3120>;
stride = <(1440 * 4)>;
format = "a8r8g8b8";
status = "okay";
};

66
arch/arm64/boot/dts/exynos/google/gs101.dtsi
View File

@ -73,7 +73,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0000>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
@ -83,7 +83,7 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x0100>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
@ -93,7 +93,7 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x0200>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
@ -103,7 +103,7 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x0300>;
enable-method = "psci";
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
cpu-idle-states = <&ananke_cpu_sleep>;
capacity-dmips-mhz = <250>;
dynamic-power-coefficient = <70>;
};
@ -113,7 +113,7 @@ cpu4: cpu@400 {
compatible = "arm,cortex-a76";
reg = <0x0400>;
enable-method = "psci";
cpu-idle-states = <&ENYO_CPU_SLEEP>;
cpu-idle-states = <&enyo_cpu_sleep>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
};
@ -123,7 +123,7 @@ cpu5: cpu@500 {
compatible = "arm,cortex-a76";
reg = <0x0500>;
enable-method = "psci";
cpu-idle-states = <&ENYO_CPU_SLEEP>;
cpu-idle-states = <&enyo_cpu_sleep>;
capacity-dmips-mhz = <620>;
dynamic-power-coefficient = <284>;
};
@ -133,7 +133,7 @@ cpu6: cpu@600 {
compatible = "arm,cortex-x1";
reg = <0x0600>;
enable-method = "psci";
cpu-idle-states = <&HERA_CPU_SLEEP>;
cpu-idle-states = <&hera_cpu_sleep>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
};
@ -143,7 +143,7 @@ cpu7: cpu@700 {
compatible = "arm,cortex-x1";
reg = <0x0700>;
enable-method = "psci";
cpu-idle-states = <&HERA_CPU_SLEEP>;
cpu-idle-states = <&hera_cpu_sleep>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <650>;
};
@ -151,7 +151,7 @@ cpu7: cpu@700 {
idle-states {
entry-method = "psci";
ANANKE_CPU_SLEEP: cpu-ananke-sleep {
ananke_cpu_sleep: cpu-ananke-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
@ -160,7 +160,7 @@ ANANKE_CPU_SLEEP: cpu-ananke-sleep {
min-residency-us = <2000>;
};
ENYO_CPU_SLEEP: cpu-enyo-sleep {
enyo_cpu_sleep: cpu-enyo-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
@ -169,7 +169,7 @@ ENYO_CPU_SLEEP: cpu-enyo-sleep {
min-residency-us = <2500>;
};
HERA_CPU_SLEEP: cpu-hera-sleep {
hera_cpu_sleep: cpu-hera-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
@ -196,6 +196,14 @@ ext_200m: clock-2 {
clock-output-names = "ext-200m";
};
firmware {
acpm_ipc: power-management {
compatible = "google,gs101-acpm-ipc";
mboxes = <&ap2apm_mailbox>;
shmem = <&apm_sram>;
};
};
pmu-0 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
@ -1400,18 +1408,30 @@ pmu_system_controller: system-controller@17460000 {
poweroff: syscon-poweroff {
compatible = "syscon-poweroff";
regmap = <&pmu_system_controller>;
offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */
mask = <0x100>; /* reset value */
mask = <0x00000100>;
value = <0x0>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pmu_system_controller>;
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
mask = <0x2>; /* SWRESET_SYSTEM */
value = <0x2>; /* reset value */
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */
mode-bootloader = <0xfc>;
mode-charge = <0x0a>;
mode-fastboot = <0xfa>;
mode-reboot-ab-update = <0x52>;
mode-recovery = <0xff>;
mode-rescue = <0xf9>;
mode-shutdown-thermal = <0x51>;
mode-shutdown-thermal-battery = <0x51>;
};
};
pinctrl_gpio_alive: pinctrl@174d0000 {
@ -1440,6 +1460,15 @@ wakeup-interrupt-controller {
};
};
ap2apm_mailbox: mailbox@17610000 {
compatible = "google,gs101-mbox";
reg = <0x17610000 0x1000>;
clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
clock-names = "pclk";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <0>;
};
pinctrl_gsactrl: pinctrl@17940000 {
compatible = "google,gs101-pinctrl";
reg = <0x17940000 0x00001000>;
@ -1454,6 +1483,7 @@ pinctrl_gsacore: pinctrl@17a80000 {
/* TODO: update once support for this CMU exists */
clocks = <0>;
clock-names = "pclk";
status = "disabled";
};
cmu_top: clock-controller@1e080000 {
@ -1466,6 +1496,14 @@ cmu_top: clock-controller@1e080000 {
};
};
apm_sram: sram@2039000 {
compatible = "mmio-sram";
reg = <0x0 0x2039000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x2039000 0x40000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts =

26
arch/arm64/boot/dts/tesla/fsd.dtsi
View File

@ -92,7 +92,7 @@ cpucl0_0: cpu@0 {
reg = <0x0 0x000>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -108,7 +108,7 @@ cpucl0_1: cpu@1 {
reg = <0x0 0x001>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -124,7 +124,7 @@ cpucl0_2: cpu@2 {
reg = <0x0 0x002>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -139,7 +139,7 @@ cpucl0_3: cpu@3 {
compatible = "arm,cortex-a72";
reg = <0x0 0x003>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -156,7 +156,7 @@ cpucl1_0: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -172,7 +172,7 @@ cpucl1_1: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -188,7 +188,7 @@ cpucl1_2: cpu@102 {
reg = <0x0 0x102>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -204,7 +204,7 @@ cpucl1_3: cpu@103 {
reg = <0x0 0x103>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -221,7 +221,7 @@ cpucl2_0: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -237,7 +237,7 @@ cpucl2_1: cpu@201 {
reg = <0x0 0x201>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -253,7 +253,7 @@ cpucl2_2: cpu@202 {
reg = <0x0 0x202>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -269,7 +269,7 @@ cpucl2_3: cpu@203 {
reg = <0x0 0x203>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
cpu-idle-states = <&cpu_sleep>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@ -291,7 +291,7 @@ cpucl_l2: l2-cache0 {
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
cpu_sleep: cpu-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
local-timer-stop;

21
include/dt-bindings/clock/samsung,exynos990.h
View File

@ -233,4 +233,25 @@
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2
#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3
#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4
#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5
#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6
#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7
#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8
#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10
#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11
#define CLK_GOUT_PERIS_GIC_CLK 12
#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13
#define CLK_GOUT_PERIS_MCT_PCLK 14
#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15
#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16
#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17
#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18
#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19
#endif

17
include/dt-bindings/soc/samsung,exynos-usi.h
View File

@ -9,9 +9,18 @@
#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
#define USI_V2_NONE 0
#define USI_V2_UART 1
#define USI_V2_SPI 2
#define USI_V2_I2C 3
#define USI_MODE_NONE 0
#define USI_MODE_UART 1
#define USI_MODE_SPI 2
#define USI_MODE_I2C 3
#define USI_MODE_I2C1 4
#define USI_MODE_I2C0_1 5
#define USI_MODE_UART_I2C1 6
/* Deprecated */
#define USI_V2_NONE USI_MODE_NONE
#define USI_V2_UART USI_MODE_UART
#define USI_V2_SPI USI_MODE_SPI
#define USI_V2_I2C USI_MODE_I2C
#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */