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dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions

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Add cpucl1 and cpucl2 clock definitions.

CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2,
which provide clock support for the CPUs on Exynosauto V920 SoC.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250428113517.426987-2-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Shin Son 2025-04-28 20:35:14 +09:00 committed by Krzysztof Kozlowski
parent e2642509e3
commit 3c50137aa4
2 changed files with 76 additions and 0 deletions
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44
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
View File

@ -34,6 +34,8 @@ properties:
enum:
- samsung,exynosautov920-cmu-top
- samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-cpucl1
- samsung,exynosautov920-cmu-cpucl2
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-misc
@ -94,6 +96,48 @@ allOf:
- const: cluster
- const: dbg
- if:
properties:
compatible:
contains:
enum:
- samsung,exynosautov920-cmu-cpucl1
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
- description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: switch
- const: cluster
- if:
properties:
compatible:
contains:
enum:
- samsung,exynosautov920-cmu-cpucl2
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
- description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: switch
- const: cluster
- if:
properties:
compatible:

32
include/dt-bindings/clock/samsung,exynosautov920.h
View File

@ -181,6 +181,38 @@
#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14
#define CLK_DOUT_CPUCL0_NOCP 15
/* CMU_CPUCL1 */
#define CLK_FOUT_CPUCL1_PLL 1
#define CLK_MOUT_PLL_CPUCL1 2
#define CLK_MOUT_CPUCL1_CLUSTER_USER 3
#define CLK_MOUT_CPUCL1_SWITCH_USER 4
#define CLK_MOUT_CPUCL1_CLUSTER 5
#define CLK_MOUT_CPUCL1_CORE 6
#define CLK_DOUT_CLUSTER1_ACLK 7
#define CLK_DOUT_CLUSTER1_ATCLK 8
#define CLK_DOUT_CLUSTER1_MPCLK 9
#define CLK_DOUT_CLUSTER1_PCLK 10
#define CLK_DOUT_CLUSTER1_PERIPHCLK 11
#define CLK_DOUT_CPUCL1_NOCP 12
/* CMU_CPUCL2 */
#define CLK_FOUT_CPUCL2_PLL 1
#define CLK_MOUT_PLL_CPUCL2 2
#define CLK_MOUT_CPUCL2_CLUSTER_USER 3
#define CLK_MOUT_CPUCL2_SWITCH_USER 4
#define CLK_MOUT_CPUCL2_CLUSTER 5
#define CLK_MOUT_CPUCL2_CORE 6
#define CLK_DOUT_CLUSTER2_ACLK 7
#define CLK_DOUT_CLUSTER2_ATCLK 8
#define CLK_DOUT_CLUSTER2_MPCLK 9
#define CLK_DOUT_CLUSTER2_PCLK 10
#define CLK_DOUT_CLUSTER2_PERIPHCLK 11
#define CLK_DOUT_CPUCL2_NOCP 12
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_IP_USER 1
#define CLK_MOUT_PERIC0_NOC_USER 2