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dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains

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To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475,
SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX.
Therefore, update the camcc bindings to include the MXC power domain on
these platforms.

Fixes: 9cbc64745f ("dt-bindings: clock: qcom: Add SM8550 camera clock controller")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Vladimir Zapolskiy 2025-05-30 18:50:47 +05:30 committed by Bjorn Andersson
parent 1a42f4d4bb
commit a02a8f8cb7
1 changed files with 12 additions and 6 deletions
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18
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
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@ -37,14 +37,18 @@ properties:
- description: Sleep clock source
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
Power domains required for the clock controller to operate
items:
- description: MMCX power domain
- description: MXC power domain
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
OPP nodes that describe required performance points on power domains
items:
- description: MMCX performance point
- description: MXC performance point
reg:
maxItems: 1
@ -82,8 +86,10 @@ examples:
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;