The clk_hw pointer can only be treated as a clk_regmap if the clk_hw is
known to be embedded within a clk_regmap structure. So first check that
before casting and accessing its data members.
Change-Id: Icad375b036ffa44c441ef16c45307bd2c0603de0
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Add set_flags op in clk_regmap_ops and update the
set_flags op for branch's clk_regmap_ops.
Update qcom_clk_set_flags to use clk_regmap_ops
for invoking the set_flags op.
Change-Id: I82b699e04854e5d9dcc0e82caccf33fe3dd85315
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Usually xo_pad and bi_tcxo frequencies are identical. However, some chips
include an extra clock divider between xo_pad and bi_tcxo to provide
reference clocks to chip peripherals (PHY's).
Add support for fixed-factor clocks to capture this extra divide factor.
Change-Id: I3d32a4b708f1dd1ee37ca4e7557094e77a6db808
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
The Lucid OLE PLL has an additional test control register which
is required to be programmed, thus introduce the register.
Change-Id: Ied541ef266e8423c0f4f67b3b816159044a17f2c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Some clks are critical and required to be on during probe to sync-state,
and also later needs to controlled by consumers. Add QCOM_CLK_BOOT_CRITICAL
flag to achieve turning on clk during probe and also register wih clk
framework so consumers can control after boot.
Change-Id: I7465828ede6cea5614cada6b49f428f84780e995
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
We currently set best_parent_rate to the ideal frequency wanted by the
RCG. This doesn't always align to the exact frequency the parent can
provide. If they differ, then clk_calc_new_rates() will return the
parent as top, even if the rounded parent frequency isn't changing.
This causes clk_propagate_rate_change() to return before being called
for its children, which means children aren't notified of the
PRE_RATE_CHANGE events.
Set best_parent_rate to the rounded rate so that we don't unnecessarily
try to change the parent.
Change-Id: Ic976db7a13dfbc63cb66b032a45060565ca90b43
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add support for odd and even configuration for PLL and also clean up few
issues with the post div mask.
Change-Id: Idd4ca99d7812d3328beadbebae45faa77111a4ff
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
The Legacy FSM Mode is required to be set when the Fabia PLL needs to be
used in non-FSM mode, thus add support for same.
Change-Id: I23d491cb33391dce1eb21d9ced298001da9ef907
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for WARN_CLK to dump the clock registers and
calltrace in case of failure in the kernel message.
Change-Id: If7452aaa02cc50deafd6f3721921f66cad9ab932
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
There are a couple circumstances where divider registers can be accessed
without first resuming their provider device. This can result in bus
errors due to necessary resources being disabled.
Call clk_runtime_get_regmap() from these places to ensure the device is
resumed and any necessary resources are enabled before touching the
registers.
Change-Id: I61e2c1b78fd47891ecc5b2e8ced54124d40b69e4
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add clk_list_rates debugfs support for divider clocks to get all
the rates supported on divider clock.
Change-Id: Iebb18cfad4fded9a2704549a2b6429e06c2de36c
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Update QCOM clock debugfs to support the below functionalities.
- Display the register contents of all the clocks which support
this operation.
- Display the frequency to voltage mapping of a clock.
- Display the list of clock frequencies supported by the root
clocks.
- Display the clk_rate_max associated with enabled clocks list.
Also add the clock list_rate_vdd_level operation, which is required
for the "clk_enabled_list" and "trace_clocks" debugfs nodes to print
the current voltage.
Change-Id: I3b4cf83e776750d993d53331142223109bf0862e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
qcom_regmap_list can get corrupted if multiple clock controllers
probe at same time. Add mutex lock to avoid list corruption.
Change-Id: I693d74a20807450008235e6ef6bfe6fa7061f781
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Some of the determine_rate callbacks rely on the clock parent to
determine the rate. This isn't possible if the clock is orphaned without
a parent. So return an error in this case instead of dereferencing NULL.
Change-Id: Ifaa8f2a85a8f8d4e37895c0b130e4eaefb0374cb
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Return correct corner voltage for qcom_clk_get_voltage api for
a clock which supports multiple vdd class.
Change-Id: Ic2faa12ae85730aa1025ed342effa3052adc1062
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Add clk_get_vdd_corner as some clocks have requirement to vote on
multiple clk_vdd_class for clock operations.
Change-Id: I03da2134f9a8439a734f7638b61479269a9cec89
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Some clocks are critical only on specific boards, i.e. clocks used to
interface with external PMICs over I2C. Which clocks are critical depend
on which I2C bus is chosen to connect the PMICs. To support this, add
properties to set QCOM_CLK_IS_CRITICAL on a per-board basis.
The qcom,critical-clocks property can be used to set
QCOM_CLK_IS_CRITICAL on individual clocks.
The qcom,critical-devices property can be used to set
QCOM_CLK_IS_CRITICAL on all clocks used by specified devices.
Change-Id: I42d61ec13225026ba7d0b78079cf7a2ab67339f2
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add QCOM_CLK_IS_CRITICAL, which can be used to enable a clock by default
in HW and to skip registering it with the framework.
Change-Id: I803a447fae742ca2e20973046090d2b8331ab598
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
The existing clk_hw_get_name() only works after the clock has been
registered with the framework since it relies on hw->core->name and
hw->core is NULL pre-registration. hw->init->name can be used
pre-registration, but this doesn't work post-registration since the
framework sets hw->init to NULL.
Provide qcom_clk_hw_get_name(), which can be called in both pre and
post-registration contexts.
Change-Id: I334e545f5112961b7ab6879daca55c70236338d6
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Some clocks have requirement to vote on multiple clk_vdd_class for clock
operations. So add the support to pass multiple vdd_class within the clock
structure to support this functionality. A new clk_vdd_classes list is
added in clk_vdd_class_data structure to pass clk_vdd_class as an array
to support voting on multiple rail.
Change-Id: I11732a39ef99fdbcb7874e1042776e7007bed35f
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Normally clk_vote_vdd_level() and clk_unvote_vdd_level() are called
while holding the clock framework's prepare_lock since they are called
in the prepare paths. However, we're also calling clk_unvote_vdd_level()
from qcom_cc_sync_state() when removing proxy votes. This happens
outside of the clock framework, so the prepare_lock isn't protecting
this case. If the sync_state callback fires while another thread is
voting/unvoting voltage from a normal clock call, then there's a race
condition that can result in regulators being set to the incorrect
voltage or being pre-maturely disabled.
Add a mutex to protect this case.
Change-Id: Ib979e2edaaa5824dc80f7d4f065d72ca0b1a4444
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add helper functions to suspend or resume the device associated with a
clk_regmap.
Change-Id: Ie4e47fce64e2052ffacdc3a8cd56fc69758d70fb
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add common runtime_pm initialization and callback functions to allow
clock providers to vote clocks, interconnects, and regulators in
runtime_suspend and runtime_resume.
Change-Id: I97588feae47016b8375849c5926495c1d73f792d
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Clock consumers gets deferred due to their dependencies during device
boot/probes, and can not put essential vdd vote before clock late init
clk_disable_unused() un-votes them. This behavior breaks functionality of
keeping clocks/feature continuously enabled from boot to HLOS. Putting
proxy vdd votes will ensure that votes are hold till consumer sync states
and it gives chance to consumers act on necessary votes when it's ready.
Also clock controller can not rely on consumers to vote vdd votes during
boot/probe sequence in all paths of clk provided consumed APIs. Putting
proxy votes makes sure that clk driver can access it's provided register
access.
Change-Id: I79301ff354b3ab53cc7c05db5e1dc75223228de6
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
To clean up clock controllers probe function, move to common regulator
handle initialization.
Also add common multiple regulator initialization support within
single clk_vdd_class.
Change-Id: I999966d3bc877e0e8bcbb54839c0dd86f41869bd
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Some clock driver clients need the frequency to voltage
mapping to be exposed. Add support to load and expose
these values through OPP tables associating to a device.
Change-Id: Iab3e34f53cab1db07fb2e78b378ed18a4dd8d90b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This ops is used to force off a clock when clk_disable() is called. CLK_DIS
bit can be used to force off respective clock.
Change-Id: Iec4204fe3bf24965d1603d0f86e74cc2818e3d1c
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
In the cases where the branch clocks requires to vote on a voltage rail
add the clock ops callbacks for the same.
Change-Id: If7ffbc4fdda1fb71c1d097f56a5eb762859eb2c4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The qcom_clk_set_flags API would be used to set/clear the memory
flags for the desired branches.
Change-Id: I58b2347f63d382168b61dd04ead57ad114559eb2
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add new API for clients to query corner voltage required by a
given frequency.
Change-Id: Ic469c36e016899d882ca084f74e0d2cb2020476c
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Providers adds ops for list rate and print reg debug nodes
to print necessary debug information, these nodes
can not be added to clk framework and is moved down to provider level.
Since provider does not have complete knowledge on clks owned
at clk framework, providers can not blindly typecast clks owned
by clk framework to call its list/print ops.
A separate qcom_regmap_list is maintained during qcom clk
registration with clk framework. So as when debug list/print
calls are called, provider have knowledge of qcom clks
and only call respective ops on qcom clks maintained
in clk_regmap_list.
Providers can use this API to know if clk is qcom regmaped clk.
Change-Id: I3e4d8280c8fa0c692f855c0d6659dd14f95008df
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
When set_rate is called on unprepared clocks new vdd_level
requirement is not cached, which leads to incorrect votes
when later clk_prepare is called. Clocks may not be prepared
when clk pre change rate is called for set_rate change request,
thus cache vdd level and only apply vote during clk prepare.
Change-Id: I54d9a3c75034cd9e67e683c3f71088f2c7cd3db1
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Specify prepare, unprepare, pre_change_rate, post_change_rate callbacks
for alpha-pll clk_ops. This ensures that supply regulator requirements
are managed properly at runtime.
Change-Id: I578b81c2ab77a8d7e2332098bd737b0646cf577d
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Some rpmh clocks aren't present on all boards, so allow marking some as
optional.
Change-Id: I6d2165a84f7e06febc7ea2694c1fb4a2ef9309d5
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add generic sync_state function that can be used by qcom clock providers
(qcom_cc_sync_state). Currently this is just a simple wrapper around
clk_sync_state from the framework, but ultimately will contain
additional qcom-specific logic.
Change-Id: I936daafdd19cc7676daa4b9fbe712d9b3181395f
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Specify prepare, unprepare and pre/post rate change callbacks for all
clk-rcg2 clk_ops. This ensures that supply regulator requirements are
managed properly at runtime.
Change-Id: I6d7e31983e99c2ef9f546771d7046e8f0111debc
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add support for prepare, unprepare, pre and post rate change regmap
clk_ops callback functions for regmap clocks to handle regulator
requirements.
Change-Id: If4657adcc047e1ca005d3d4f7ab88146dba85ee0
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Add support to manage voltage supply regulators via the
vdd-class voting interface. Provide functions that can be
easily used to implement clk_ops callbacks used for voltage
voting.
Change-Id: I891b5944ed8075074c11f139d9e6951d796c7f90
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
