clk: qcom: clk-debug: Add snapshot from msm-5.15

Add clk-debug snapshot from msm-5.15 commit 123f6f081248 ("Merge "spi:
spi-msm-geni: clear qn_err flag before transfer"").

Change-Id: I64896c4b92424366e7ecb600126f4510ab5c63ad
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>

drivers/clk/qcom/Makefile

@@ -16,6 +16,7 @@ clk-qcom-y += clk-regmap-mux-div.o
 clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
 clk-qcom-y += clk-hfpll.o
 clk-qcom-y += reset.o
+clk-qcom-y += clk-debug.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-dummy.o
 

drivers/clk/qcom/clk-debug.h

@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2016, 2019-2021, The Linux Foundation. All rights reserved. */
+
+#ifndef __QCOM_CLK_DEBUG_H__
+#define __QCOM_CLK_DEBUG_H__
+
+#include <linux/platform_device.h>
+#include "../clk.h"
+
+/**
+ * struct mux_regmap_names - Structure of mux regmap mapping
+ * @mux:		pointer to a clock debug mux
+ * @regmap_name:	corresponding regmap name used to match a debug mux to
+			its regmap
+ */
+struct mux_regmap_names {
+	struct clk_debug_mux *mux;
+	const char *regmap_name;
+};
+
+/* Debugfs Measure Clocks */
+
+/**
+ * struct measure_clk_data - Structure of clk measure
+ *
+ * @cxo:		XO clock.
+ * @xo_div4_cbcr:	offset of debug XO/4 div register.
+ * @ctl_reg:		offset of debug control register.
+ * @status_reg:		offset of debug status register.
+ * @cbcr_offset:	branch register to turn on debug mux.
+ */
+struct measure_clk_data {
+	struct clk *cxo;
+	u32 ctl_reg;
+	u32 status_reg;
+	u32 xo_div4_cbcr;
+};
+
+/**
+ * struct clk_debug_mux - Structure of clock debug mux
+ *
+ * @mux_sels:		indicates the debug mux index at recursive debug mux.
+ * @pre_div_val:	optional divider values for clocks that were pre-divided
+			before feeding into the debug muxes
+ * @num_parents:	number of parents
+ * @regmap:		regmaps of debug mux
+ * @priv:		private measure_clk_data to be used by debug mux
+ * @en_mask:		indicates the enable bit mask at global clock
+ *			controller debug mux.
+ * @debug_offset:	debug mux offset.
+ * @post_div_offset:	register with post-divider settings for the debug mux.
+ * @cbcr_offset:	branch register to turn on debug mux.
+ * @src_sel_mask:	indicates the mask to be used for src selection in
+			primary mux.
+ * @src_sel_shift:	indicates the shift required for source selection in
+			primary mux.
+ * @post_div_mask:	indicates the post div mask to be used for the primary
+			mux.
+ * @post_div_shift:	indicates the shift required for post divider
+			selection in primary mux.
+ * @period_offset:	offset of the period register used to read to determine
+			the mc clock period
+ * @hw:			handle between common and hardware-specific interfaces.
+ */
+struct clk_debug_mux {
+	int *mux_sels;
+	int num_mux_sels;
+	int *pre_div_vals;
+	int num_parents;
+	struct regmap *regmap;
+	void *priv;
+	u32 en_mask;
+	u32 debug_offset;
+	u32 cbcr_offset;
+	u32 src_sel_mask;
+	u32 src_sel_shift;
+	u32 post_div_offset;
+	u32 post_div_mask;
+	u32 post_div_shift;
+	u32 post_div_val;
+	u32 period_offset;
+	struct clk_hw hw;
+	struct list_head list;
+};
+
+#define to_clk_measure(_hw) container_of((_hw), struct clk_debug_mux, hw)
+
+extern const struct clk_ops clk_debug_mux_ops;
+
+int clk_debug_measure_register(struct clk_hw *hw);
+int devm_clk_register_debug_mux(struct device *pdev, struct clk_debug_mux *mux);
+void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);
+int map_debug_bases(struct platform_device *pdev, const char *base,
+		    struct clk_debug_mux *mux);
+
+void clk_common_debug_init(struct clk_hw *hw, struct dentry *dentry);
+
+/* hw debug registration */
+int clk_hw_debug_register(struct device *dev, struct clk_hw *clk_hw);
+int clk_debug_init(void);
+void clk_debug_exit(void);
+extern void clk_debug_print_hw(struct clk_hw *hw, struct seq_file *f);
+
+#define WARN_CLK(hw, cond, fmt, ...)						\
+	do {									\
+		clk_debug_print_hw(hw, NULL);					\
+		WARN(cond, "%s: " fmt, qcom_clk_hw_get_name(hw), ##__VA_ARGS__);	\
+	} while (0)
+
+#define clock_debug_output(m, fmt, ...)			\
+	do {							\
+		if (m)						\
+			seq_printf(m, fmt, ##__VA_ARGS__);	\
+		else						\
+			pr_info(fmt, ##__VA_ARGS__);		\
+	} while (0)
+
+#define clock_debug_output_cont(s, fmt, ...)			\
+	do {							\
+		if (s)						\
+			seq_printf(s, fmt, ##__VA_ARGS__);	\
+		else						\
+			pr_cont(fmt, ##__VA_ARGS__);		\
+	} while (0)
+
+#endif

drivers/clk/qcom/common.c

@@ -24,6 +24,7 @@
 #include "reset.h"
 #include "gdsc.h"
 #include "vdd-level.h"
+#include "clk-debug.h"
 
 struct qcom_cc {
 	struct qcom_reset_controller reset;
@@ -563,4 +564,17 @@ int qcom_cc_runtime_suspend(struct device *dev)
 }
 EXPORT_SYMBOL(qcom_cc_runtime_suspend);
 
+static int __init qcom_clk_init(void)
+{
+	return clk_debug_init();
+}
+subsys_initcall(qcom_clk_init);
+
+static void __exit qcom_clk_exit(void)
+{
+	clk_debug_exit();
+}
+module_exit(qcom_clk_exit);
+
+MODULE_DESCRIPTION("Common QCOM clock control library");
 MODULE_LICENSE("GPL v2");

drivers/clk/qcom/trace.h

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM clk_qcom
+
+#if !defined(_TRACE_CLOCK_QCOM_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_CLOCK_QCOM
+
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(clk_state_dump,
+
+	TP_PROTO(const char *name, unsigned int prepare_count,
+	unsigned int enable_count, unsigned long rate, unsigned int vdd_level),
+
+	TP_ARGS(name, prepare_count, enable_count, rate, vdd_level),
+
+	TP_STRUCT__entry(
+		__string(name,			name)
+		__field(unsigned int,		prepare_count)
+		__field(unsigned int,		enable_count)
+		__field(unsigned long,		rate)
+		__field(unsigned int,		vdd_level)
+	),
+
+	TP_fast_assign(
+		__assign_str(name, name);
+		__entry->prepare_count = prepare_count;
+		__entry->enable_count = enable_count;
+		__entry->rate = rate;
+		__entry->vdd_level = vdd_level;
+	),
+
+	TP_printk("%s\tprepare:enable cnt [%u:%u]\trate: vdd_level [%lu:%u]",
+		__get_str(name), __entry->prepare_count, __entry->enable_count,
+		__entry->rate, __entry->vdd_level)
+);
+
+DEFINE_EVENT(clk_state_dump, clk_state,
+
+	TP_PROTO(const char *name, unsigned int prepare_count,
+	unsigned int enable_count, unsigned long rate, unsigned int vdd_level),
+
+	TP_ARGS(name, prepare_count, enable_count, rate, vdd_level)
+);
+
+#endif /* _TRACE_CLOCK_QCOM */
+
+/* This part must be outside protection */
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE trace
+
+#include <trace/define_trace.h>