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clk: qcom: clk-alpha-pll: Add rivian_evo snapshot from msm-5.15

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Add rivian_evo snapshot from msm-5.15 commit 123f6f081248 ("Merge "spi:
spi-msm-geni: clear qn_err flag before transfer"").

Change-Id: Ie55a247e3ca6b7167c29f3ac74262c18dc1d99ce
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
This commit is contained in:
Mike Tipton 2022-03-29 10:27:40 -07:00
parent a537a3a2aa
commit b2062dc9f4
2 changed files with 155 additions and 0 deletions
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149
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -184,6 +184,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x14,
[PLL_OFF_USER_CTL_U] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1c,
[PLL_OFF_CONFIG_CTL_U] = 0x20,
[PLL_OFF_CONFIG_CTL_U1] = 0x24,
[PLL_OFF_TEST_CTL] = 0x28,
[PLL_OFF_TEST_CTL_U] = 0x2c,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@ -3386,3 +3398,140 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
.init = clk_lucid_evo_pll_init,
};
EXPORT_SYMBOL(clk_alpha_pll_lucid_evo_ops);
int clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll,
struct regmap *regmap, const struct alpha_pll_config *config)
{
u32 mask;
int ret;
ret = trion_pll_is_enabled(pll, regmap);
if (ret)
return ret;
if (config->config_ctl_val)
ret |= regmap_write(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
if (config->config_ctl_hi_val)
ret |= regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
if (config->config_ctl_hi1_val)
ret |= regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
config->config_ctl_hi1_val);
if (config->test_ctl_val)
ret |= regmap_write(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
if (config->test_ctl_hi_val)
ret |= regmap_write(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
if (config->l)
ret |= regmap_write(regmap, PLL_L_VAL(pll), config->l);
if (config->user_ctl_val)
ret |= regmap_write(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
if (config->user_ctl_hi_val)
ret |= regmap_write(regmap, PLL_USER_CTL_U(pll),
config->user_ctl_hi_val);
/* pll_opmode to STANDBY */
ret |= regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
mask = PLL_RESET_N | PLL_BYPASSNL;
ret |= regmap_update_bits(regmap, PLL_MODE(pll), mask, mask);
return ret ? -EIO : 0;
}
EXPORT_SYMBOL(clk_rivian_evo_pll_configure);
static unsigned long
clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l;
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
return parent_rate * l;
}
static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l;
u64 a;
unsigned long min_freq, max_freq;
rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
}
static void clk_rivian_evo_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
int size, i, val;
static struct clk_register_data data[] = {
{"PLL_MODE", PLL_OFF_MODE},
{"PLL_OPMODE", PLL_OFF_OPMODE},
{"PLL_STATUS", PLL_OFF_STATUS},
{"PLL_L_VAL", PLL_OFF_L_VAL},
{"PLL_USER_CTL", PLL_OFF_USER_CTL},
{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},
{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
};
size = ARRAY_SIZE(data);
for (i = 0; i < size; i++) {
regmap_read(pll->clkr.regmap, pll->offset +
pll->regs[data[i].offset], &val);
clock_debug_output(f, "%20s: 0x%.8x\n", data[i].name, val);
}
}
static struct clk_regmap_ops clk_rivian_evo_pll_regmap_ops = {
.list_registers = &clk_rivian_evo_pll_list_registers,
};
static int clk_rivian_evo_pll_init(struct clk_hw *hw)
{
struct clk_regmap *rclk = to_clk_regmap(hw);
if (!rclk->ops)
rclk->ops = &clk_rivian_evo_pll_regmap_ops;
return 0;
}
const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
.prepare = clk_prepare_regmap,
.unprepare = clk_unprepare_regmap,
.pre_rate_change = clk_pre_change_regmap,
.post_rate_change = clk_post_change_regmap,
.enable = alpha_pll_lucid_5lpe_enable,
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_rivian_evo_pll_recalc_rate,
.round_rate = clk_rivian_evo_pll_round_rate,
.debug_init = clk_common_debug_init,
.init = clk_rivian_evo_pll_init,
};
EXPORT_SYMBOL(clk_alpha_pll_rivian_evo_ops);

6
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -20,6 +20,7 @@ enum {
CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,
CLK_ALPHA_PLL_TYPE_REGERA,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_MAX,
};
@ -169,6 +170,8 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@ -190,4 +193,7 @@ int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,
struct regmap *regmap,
const struct alpha_pll_config *config);
int clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll,
struct regmap *regmap,
const struct alpha_pll_config *config);
#endif