mirror of
https://github.com/torvalds/linux.git
synced 2026-07-31 19:47:08 +02:00
clk: qcom: clk-alpha-pll: Add lucid_evo snapshot from msm-5.15
Add lucid_evo snapshot from msm-5.15 commit 123f6f081248 ("Merge "spi:
spi-msm-geni: clear qn_err flag before transfer"").
Change-Id: I494357d26a31ad0509da3a1112a324151acf4993
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
This commit is contained in:
Mike Tipton
parent
fc35036bbb
commit
a537a3a2aa
|
|
@ -170,6 +170,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
|||
[PLL_OFF_OPMODE] = 0x28,
|
||||
[PLL_OFF_STATUS] = 0x38,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
|
||||
[PLL_OFF_OPMODE] = 0x04,
|
||||
[PLL_OFF_STATUS] = 0x0c,
|
||||
[PLL_OFF_L_VAL] = 0x10,
|
||||
[PLL_OFF_ALPHA_VAL] = 0x14,
|
||||
[PLL_OFF_USER_CTL] = 0x18,
|
||||
[PLL_OFF_USER_CTL_U] = 0x1c,
|
||||
[PLL_OFF_CONFIG_CTL] = 0x20,
|
||||
[PLL_OFF_CONFIG_CTL_U] = 0x24,
|
||||
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
|
||||
[PLL_OFF_TEST_CTL] = 0x2c,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x30,
|
||||
[PLL_OFF_TEST_CTL_U1] = 0x34,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
||||
|
||||
|
|
@ -205,6 +219,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
|||
#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
|
||||
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
|
||||
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
|
||||
#define LUCID_EVO_PCAL_NOT_DONE BIT(8)
|
||||
#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
|
||||
#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
|
||||
#define LUCID_EVO_PLL_CAL_L_VAL_MASK GENMASK(31, 16)
|
||||
#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
|
||||
|
||||
/* ZONDA PLL specific */
|
||||
#define ZONDA_PLL_OUT_MASK 0xf
|
||||
|
|
@ -2932,3 +2951,438 @@ const struct clk_ops clk_regera_pll_ops = {
|
|||
.init = clk_regera_pll_init,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_regera_pll_ops);
|
||||
|
||||
int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,
|
||||
struct regmap *regmap, const struct alpha_pll_config *config)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = trion_pll_is_enabled(pll, regmap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (config->l)
|
||||
ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
|
||||
LUCID_EVO_PLL_L_VAL_MASK, config->l);
|
||||
|
||||
if (config->cal_l)
|
||||
ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
|
||||
LUCID_EVO_PLL_CAL_L_VAL_MASK,
|
||||
config->cal_l << LUCID_EVO_PLL_CAL_L_VAL_SHIFT);
|
||||
else
|
||||
ret |= regmap_update_bits(regmap, PLL_L_VAL(pll),
|
||||
LUCID_EVO_PLL_CAL_L_VAL_MASK,
|
||||
TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT);
|
||||
|
||||
if (config->alpha)
|
||||
ret |= regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
|
||||
|
||||
if (config->config_ctl_val)
|
||||
ret |= regmap_write(regmap, PLL_CONFIG_CTL(pll),
|
||||
config->config_ctl_val);
|
||||
|
||||
if (config->config_ctl_hi_val)
|
||||
ret |= regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
|
||||
config->config_ctl_hi_val);
|
||||
|
||||
if (config->config_ctl_hi1_val)
|
||||
ret |= regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
|
||||
config->config_ctl_hi1_val);
|
||||
|
||||
if (config->user_ctl_val)
|
||||
ret |= regmap_write(regmap, PLL_USER_CTL(pll),
|
||||
config->user_ctl_val);
|
||||
|
||||
if (config->user_ctl_hi_val)
|
||||
ret |= regmap_write(regmap, PLL_USER_CTL_U(pll),
|
||||
config->user_ctl_hi_val);
|
||||
|
||||
if (config->test_ctl_val)
|
||||
ret |= regmap_write(regmap, PLL_TEST_CTL(pll),
|
||||
config->test_ctl_val);
|
||||
|
||||
if (config->test_ctl_hi_val)
|
||||
ret |= regmap_write(regmap, PLL_TEST_CTL_U(pll),
|
||||
config->test_ctl_hi_val);
|
||||
|
||||
if (config->test_ctl_hi1_val)
|
||||
ret |= regmap_write(regmap, PLL_TEST_CTL_U1(pll),
|
||||
config->test_ctl_hi1_val);
|
||||
|
||||
/* Disable PLL output */
|
||||
ret |= regmap_update_bits(regmap, PLL_MODE(pll),
|
||||
PLL_OUTCTRL, 0);
|
||||
|
||||
/* Set operation mode to STANDBY */
|
||||
ret |= regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
|
||||
/* PLL should be in OFF mode before continuing */
|
||||
wmb();
|
||||
|
||||
/* Place the PLL in STANDBY mode */
|
||||
ret |= regmap_update_bits(regmap, PLL_MODE(pll),
|
||||
PLL_RESET_N, PLL_RESET_N);
|
||||
|
||||
return ret ? -EIO : 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_lucid_evo_pll_configure);
|
||||
|
||||
static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* If in FSM mode, just vote for it */
|
||||
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
|
||||
ret = clk_enable_regmap(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
return wait_for_pll_enable_lock(pll);
|
||||
}
|
||||
|
||||
/* Check if PLL is already enabled */
|
||||
ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
else if (ret) {
|
||||
pr_warn("%s PLL is already enabled\n",
|
||||
clk_hw_get_name(&pll->clkr.hw));
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
PLL_RESET_N, PLL_RESET_N);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set operation mode to RUN */
|
||||
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
|
||||
|
||||
ret = wait_for_pll_enable_lock(pll);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable the PLL outputs */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
|
||||
PLL_OUT_MASK, PLL_OUT_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable the global PLL outputs */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
PLL_OUTCTRL, PLL_OUTCTRL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Ensure that the write above goes through before returning. */
|
||||
mb();
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* If in FSM mode, just unvote it */
|
||||
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
|
||||
clk_disable_regmap(hw);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Disable the global PLL output */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
PLL_OUTCTRL, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Disable the PLL outputs */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
|
||||
PLL_OUT_MASK, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Place the PLL mode in STANDBY */
|
||||
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll),
|
||||
PLL_STANDBY);
|
||||
|
||||
if (pll->flags & DISABLE_TO_OFF)
|
||||
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
PLL_RESET_N, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* The Lucid PLL requires a power-on self-calibration which happens when the
|
||||
* PLL comes out of reset. The calibration is performed at an output frequency
|
||||
* of ~1300 MHz which means that SW will have to vote on a voltage that's
|
||||
* equal to or greater than SVS_L1 on the corresponding rail. Since this is not
|
||||
* feasable to do in the atomic enable path, temporarily bring up the PLL here,
|
||||
* let it calibrate, and place it in standby before returning.
|
||||
*/
|
||||
static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
struct clk_hw *p;
|
||||
u32 regval;
|
||||
unsigned long prate;
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_regmap(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Return early if calibration is not needed. */
|
||||
regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
|
||||
if (!(regval & LUCID_EVO_PCAL_NOT_DONE))
|
||||
return 0;
|
||||
|
||||
if (pll->config) {
|
||||
/*
|
||||
* Reconfigure the PLL if CAL_L_VAL is 0 (which implies that all
|
||||
* clock controller registers have been reset).
|
||||
*/
|
||||
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), ®val);
|
||||
regval &= LUCID_EVO_PLL_CAL_L_VAL_MASK;
|
||||
if (!regval) {
|
||||
pr_debug("reconfiguring %s after it was reset\n",
|
||||
clk_hw_get_name(hw));
|
||||
ret = clk_lucid_evo_pll_configure(pll,
|
||||
pll->clkr.regmap, pll->config);
|
||||
if (ret) {
|
||||
pr_err("pll configuration failed: %u\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
p = clk_hw_get_parent(hw);
|
||||
if (!p)
|
||||
return -EINVAL;
|
||||
|
||||
prate = clk_hw_get_rate(p);
|
||||
if (!prate)
|
||||
return -EINVAL;
|
||||
|
||||
ret = alpha_pll_lucid_evo_enable(hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
alpha_pll_lucid_evo_disable(hw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 l, frac;
|
||||
|
||||
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
|
||||
l &= LUCID_EVO_PLL_L_VAL_MASK;
|
||||
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
|
||||
|
||||
return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_REG_16BIT_WIDTH);
|
||||
}
|
||||
|
||||
static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
|
||||
int i, val = 0, div, ret;
|
||||
|
||||
/*
|
||||
* If the PLL is in FSM mode, then treat set_rate callback as a
|
||||
* no-operation.
|
||||
*/
|
||||
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val & LUCID_EVO_ENABLE_VOTE_RUN)
|
||||
return 0;
|
||||
|
||||
if (!pll->post_div_table) {
|
||||
pr_err("Missing the post_div_table for the PLL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
|
||||
for (i = 0; i < pll->num_post_div; i++) {
|
||||
if (pll->post_div_table[i].div == div) {
|
||||
val = pll->post_div_table[i].val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
|
||||
(BIT(pll->width) - 1) << pll->post_div_shift,
|
||||
val << pll->post_div_shift);
|
||||
}
|
||||
|
||||
static int alpha_pll_lucid_evo_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
unsigned long rrate;
|
||||
u32 regval, l;
|
||||
u64 a;
|
||||
int ret;
|
||||
|
||||
rrate = alpha_pll_round_rate(rate, prate, &l, &a,
|
||||
ALPHA_REG_16BIT_WIDTH);
|
||||
/*
|
||||
* Due to a limited number of bits for fractional rate programming, the
|
||||
* rounded up rate could be marginally higher than the requested rate.
|
||||
*/
|
||||
if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
|
||||
pr_err("Call set rate on the PLL with rounded rates!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll),
|
||||
LUCID_EVO_PLL_L_VAL_MASK, l);
|
||||
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
|
||||
|
||||
/*
|
||||
* Latch the new L and ALPHA values. This is only necessary when the
|
||||
* PLL is in RUN or STANDBY. If the PLL is in RESET, then the latch
|
||||
* interface is disabled and the ACK won't assert. The PLL will
|
||||
* automatically latch the values when transitioning out of RESET.
|
||||
*/
|
||||
regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
|
||||
if (regval & PLL_RESET_N) {
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Wait for 2 reference cycles before checking the ACK bit. */
|
||||
udelay(1);
|
||||
regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
|
||||
if (!(regval & LUCID_5LPE_ALPHA_PLL_ACK_LATCH)) {
|
||||
WARN_CLK(&pll->clkr.hw, 1,
|
||||
"PLL latch failed. Output may be unstable!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Return the latch input to 0 */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
LUCID_5LPE_PLL_LATCH_INPUT, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (clk_hw_is_enabled(hw)) {
|
||||
ret = wait_for_pll_enable_lock(pll);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lucid_evo_pll_list_registers(struct seq_file *f,
|
||||
struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
int size, i, val;
|
||||
|
||||
static struct clk_register_data data[] = {
|
||||
{"PLL_MODE", PLL_OFF_MODE},
|
||||
{"PLL_OPMODE", PLL_OFF_OPMODE},
|
||||
{"PLL_STATUS", PLL_OFF_STATUS},
|
||||
{"PLL_L_VAL", PLL_OFF_L_VAL},
|
||||
{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
|
||||
{"PLL_USER_CTL", PLL_OFF_USER_CTL},
|
||||
{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
|
||||
{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
|
||||
{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
|
||||
{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},
|
||||
{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
|
||||
{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
|
||||
{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
|
||||
};
|
||||
|
||||
static struct clk_register_data data1[] = {
|
||||
{"APSS_PLL_VOTE", 0x0},
|
||||
};
|
||||
|
||||
size = ARRAY_SIZE(data);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
regmap_read(pll->clkr.regmap, pll->offset +
|
||||
pll->regs[data[i].offset], &val);
|
||||
clock_debug_output(f, "%20s: 0x%.8x\n", data[i].name, val);
|
||||
}
|
||||
|
||||
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
|
||||
|
||||
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
|
||||
regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
|
||||
data1[0].offset, &val);
|
||||
clock_debug_output(f, "%20s: 0x%.8x\n", data[0].name, val);
|
||||
}
|
||||
}
|
||||
|
||||
static struct clk_regmap_ops clk_lucid_evo_pll_regmap_ops = {
|
||||
.list_registers = &lucid_evo_pll_list_registers,
|
||||
};
|
||||
|
||||
static int clk_lucid_evo_pll_init(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *rclk = to_clk_regmap(hw);
|
||||
|
||||
if (!rclk->ops)
|
||||
rclk->ops = &clk_lucid_evo_pll_regmap_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
|
||||
.prepare = clk_prepare_regmap,
|
||||
.unprepare = clk_unprepare_regmap,
|
||||
.pre_rate_change = clk_pre_change_regmap,
|
||||
.post_rate_change = clk_post_change_regmap,
|
||||
.enable = alpha_pll_lucid_evo_enable,
|
||||
.disable = alpha_pll_lucid_evo_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.debug_init = clk_common_debug_init,
|
||||
.init = clk_lucid_evo_pll_init,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_evo_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
|
||||
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
|
||||
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_evo_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
|
||||
.prepare = alpha_pll_lucid_evo_prepare,
|
||||
.unprepare = clk_unprepare_regmap,
|
||||
.pre_rate_change = clk_pre_change_regmap,
|
||||
.post_rate_change = clk_post_change_regmap,
|
||||
.enable = alpha_pll_lucid_evo_enable,
|
||||
.disable = alpha_pll_lucid_evo_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.set_rate = alpha_pll_lucid_evo_set_rate,
|
||||
.debug_init = clk_common_debug_init,
|
||||
.init = clk_lucid_evo_pll_init,
|
||||
};
|
||||
EXPORT_SYMBOL(clk_alpha_pll_lucid_evo_ops);
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ enum {
|
|||
CLK_ALPHA_PLL_TYPE_ZONDA,
|
||||
CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,
|
||||
CLK_ALPHA_PLL_TYPE_REGERA,
|
||||
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
|
||||
CLK_ALPHA_PLL_TYPE_MAX,
|
||||
};
|
||||
|
||||
|
|
@ -78,6 +79,7 @@ struct clk_alpha_pll {
|
|||
#define SUPPORTS_FSM_MODE BIT(2)
|
||||
#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
|
||||
#define SUPPORTS_FSM_LEGACY_MODE BIT(4)
|
||||
#define DISABLE_TO_OFF BIT(5)
|
||||
u8 flags;
|
||||
|
||||
struct clk_regmap clkr;
|
||||
|
|
@ -163,6 +165,10 @@ extern const struct clk_ops clk_alpha_pll_zonda_5lpe_ops;
|
|||
|
||||
extern const struct clk_ops clk_regera_pll_ops;
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
|
||||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
|
|
@ -181,4 +187,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
|||
int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
||||
int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,
|
||||
struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user