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clk: qcom: clk-alpha-pll: Update the Lucid OLE PLL registers

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The Lucid OLE PLL has an additional test control register which
is required to be programmed, thus introduce the register.

Change-Id: Ied541ef266e8423c0f4f67b3b816159044a17f2c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2021-10-04 12:40:45 +05:30 committed by Mike Tipton
parent cc59dbb6d2
commit a1dca775aa
2 changed files with 25 additions and 1 deletions
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21
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -55,6 +55,7 @@
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
@ -196,6 +197,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x28,
[PLL_OFF_TEST_CTL_U] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATE] = 0x08,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
[PLL_OFF_TEST_CTL] = 0x2c,
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U2] = 0x38,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@ -3033,6 +3050,10 @@ int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll,
ret |= regmap_write(regmap, PLL_TEST_CTL_U1(pll),
config->test_ctl_hi1_val);
if (config->test_ctl_hi2_val)
ret |= regmap_write(regmap, PLL_TEST_CTL_U2(pll),
config->test_ctl_hi2_val);
/* Disable PLL output */
ret |= regmap_update_bits(regmap, PLL_MODE(pll),
PLL_OUTCTRL, 0);

5
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -20,7 +20,7 @@ enum {
CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,
CLK_ALPHA_PLL_TYPE_REGERA,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE = CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_RIVIAN_OLE = CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_MAX,
@ -41,6 +41,8 @@ enum {
PLL_OFF_TEST_CTL,
PLL_OFF_TEST_CTL_U,
PLL_OFF_TEST_CTL_U1,
PLL_OFF_TEST_CTL_U2,
PLL_OFF_STATE,
PLL_OFF_STATUS,
PLL_OFF_OPMODE,
PLL_OFF_FRAC,
@ -125,6 +127,7 @@ struct alpha_pll_config {
u32 test_ctl_val;
u32 test_ctl_hi_val;
u32 test_ctl_hi1_val;
u32 test_ctl_hi2_val;
u32 main_output_mask;
u32 aux_output_mask;
u32 aux2_output_mask;