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clk: qcom: alpha-pll: Add odd/even support for Trion PLL

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Add support for odd and even configuration for PLL and also clean up few
issues with the post div mask.

Change-Id: Idd4ca99d7812d3328beadbebae45faa77111a4ff
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
This commit is contained in:
Taniya Das 2020-05-12 15:25:19 +05:30 committed by Mike Tipton
parent 51389014be
commit 38dc424af0
1 changed files with 13 additions and 3 deletions
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16
drivers/clk/qcom/clk-alpha-pll.c
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@ -40,7 +40,7 @@
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
# define PLL_POST_DIV_SHIFT 8
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
# define PLL_ALPHA_EN BIT(24)
# define PLL_ALPHA_MODE BIT(25)
# define PLL_VCO_SHIFT 20
@ -1600,6 +1600,11 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
struct regmap *regmap = pll->clkr.regmap;
u32 i, div = 1, val;
if (!pll->post_div_table) {
pr_err("Missing the post_div_table for the PLL\n");
return -EINVAL;
}
regmap_read(regmap, PLL_USER_CTL(pll), &val);
val >>= pll->post_div_shift;
@ -1633,6 +1638,11 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
struct regmap *regmap = pll->clkr.regmap;
int i, val = 0, div;
if (!pll->post_div_table) {
pr_err("Missing the post_div_table for the PLL\n");
return -EINVAL;
}
div = DIV_ROUND_UP_ULL(parent_rate, rate);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].div == div) {
@ -1642,8 +1652,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
}
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
val << PLL_POST_DIV_SHIFT);
PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
val << pll->post_div_shift);
}
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {