When the irq-mux and its interrupt-map were added to the mpfs
devicetree, the gpio interrupts became fixed at the SoC level rather
than dependant on the design - the interrupt-map is now what varies.
The beaglev-fire should have had its dts copy of the interrupts removed
but did not. As a result, the mcp3564 driver does not probe, because
even though it doesn't use the interrupt at present, the SPI core still
looks it up. This lookup fails because the second copy of the interrupts
property doesn't resolve to something valid when passed via the
interrupt-map. Remove the second/incorrect set of interrupts properties.
Fixes: b0258f69f1 ("riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC")
CC: stable@vger.kernel.org
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Sophgo:
The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCanKEvQAKCRCHG95Quc97
dn44AP9HHp2ut8rY0UnmS/s+rCAbWX/2YkhGWdWPPk1o4VkSdQEArt9F9RpXg/Mp
RfmT/LEx81g7zR7wqpGlpy1a5F+TBw4=
=SAg0
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp57JAACgkQmmx57+YA
GNla7xAAqMRFdMgCOH74zaNtohonnSgbmJi4dL6RakzJHCjZO+VWMnxavg/A8qTb
DrSugeW0SV1pe/NbOKaJbqZ6xa/gJJitivPNJIgn8uM3WauetzE55isGPb+smR1r
soqTG/3AYocT88fy7FgLL3GmvY9yd1dAOHA/CFdTpmBdrqfV5fSSmed08wM0lVQe
O1EgjHe7eNk+v3DYo80buRxwljiW0gpbhFFsz84hbdFoL/Cf/GAXWP1xhZjCTKo1
9/Zex3J7SsdNAaZjDzMyF0S0eolyAPJW0SzToDkMniE/tSYc2lkjW7R1I55iuQvi
BJ+kKK1k2/TrSbmvjuvqCEnwfOh9BzXPf4UWuLrUrEVTpdEBtpe0otFGRBqzg0lO
RkgUPdHWR8uhL57Oos8HM4WH2VN4s0jqP0FN1sUp46fnnQFCEi/nO4vRTnOt+ppy
HxNjJyQRrP97OH7s7zpUTyCVVJBZPL3EF3NuNCzioooXK3LHI4MSApTtDIt9bPBi
yS5U1SaUaNm4RwCaFH9QZSQHXdoEXKe0DPX/P9cROr62T6eSyDhZnIIcucveMw+6
tJie38mJChficq8mCo3/S1P3gMELy5lmBw68XCg/UMBcdV76Mq4AgFq6o5Ow+oXp
KS/sO+RkxZPD7ImnGLKrSuurJnIsMpOR/69lLFBkZ0LBtdZY9W4=
=CrHg
-----END PGP SIGNATURE-----
Merge tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v7.3
Sophgo:
The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
* tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux:
riscv: dts: sophgo: Add Milk-V Duo 256M board support
riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
dt-bindings: soc: sophgo: add Milk-V Duo 256M board
riscv64: dts: sophgo: add initial Milk-V Duo S board support
riscv64: dts: sophgo: add SG2000 dtsi
riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmpupawbFIAAAAAABAAO
bWFudTIsMi41KzEuMTIsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z
Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz
REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtuDgP/0+IIPDo/U7U0IhT+dAx
Mxr1fWX1M4h5nEmirD8Zsx8TSfvZrpZr5MvazjrHxZ5U2U4ntkqrcoByhIqEy6Dn
wz3A8arOEe3BU1zXf4UAPAW0CZA3Bp9rEDgwbgsTfyelSLyeDqaMX8l/8XQLU8Sl
f28L5p+5AQota4Cutl36yE/KP6cK+7SBSgXA2Rnb9SXzvwC9cQGuOUq71zUsS7jI
FdpYcvyCbLFmUiq2XoeFAdGB04nYs28VWiFnHg7FNdrCqWH6pgi/zxd3QtlTxjd6
oIrp/NsBnx9WAyx9GDhckpqOLt+sA49BjMTArBHmytVBI0ku2kbueQXJIS2J2OEq
Cj4jkMD36Mbk21UP/3OOohARxPYWDDsRQ6NzvAMqNnmFdGa2lTCGA2pBsXF6pzYA
cgFoSQq3s37ArNWaFxeCgnAnzyUWtEUEA3wcp+04xh4s9a90khxuU/rpF+GuyZwp
5Bfppy9L9dI6BogmfAcMsVHcLd0UhDoC6nokx8QLCtrVKEnpvWHfAtWProzEINfX
k9K+f+fLtvL4aWGevKfZZfbMwFRrDaARI03HqW/flUjLBVggoC2FFo63WOfEmvZr
ldCmIWM2iDgr7gBTSy8FSX+3FNROyc2xDFhM189crVvK0+LCCMyqGhHFNnk6NYbU
NRf7S+rwIN9yrBSUgrX6GCXs
=WKqT
-----END PGP SIGNATURE-----
Merge tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into soc/dt
RISC-V SpacemiT DT changes for 7.3
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
* tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: (33 commits)
riscv: dts: spacemit: Add cpu scaling for Milk-V Jupiter
riscv: dts: spacemit: k1-bananapi-cm6: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-r2s: fix maximum CPU core voltage
riscv: dts: spacemit: k1-musepi-pro: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-rv2: fix maximum CPU core voltage
riscv: dts: spacemit: k1-milkv-jupiter: fix maximum CPU core voltage
riscv: dts: spacemit: k1-bananapi-f3: fix maximum CPU core voltage
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 com260 board
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 pico-itx board
riscv: dts: spacemit: k3: add i2s0-i2s5 nodes
riscv: dts: spacemit: k3: add USB controller and USB phy support
riscv: dts: spacemit: enable PCIe on OrangePi R2S
riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1
riscv: dts: spacemit: k3-com260: add eeprom on i2c2
riscv: dts: spacemit: add SPI controllers for K3
riscv: dts: spacemit: add K3 PDMA request numbers
riscv: dts: spacemit: Fix phy id check for the phy on com260 board
riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board
riscv: dts: spacemit: Add enough deassert time for the PHY on com260 board
riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Milk-V Duo 256M is a small form factor development board based on
the Sophgo SG2002 SoC.
This patch adds basic device tree support for the board, including:
- UART console
- SD/MMC controller
- USB host
- Onboard blue status LED (connected to PWR_GPIO[2] / porte 2)
Tested on actual Milk-V Duo 256M hardware, verified boot to shell and
heartbeat LED functionality.
Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com>
Link: https://patch.msgid.link/20260725175346.139173-4-chenyou910331@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
The CV180x/CV181x family has an additional DesignWare APB GPIO
controller (PWR_GPIO) located in the always-on power domain at
0x5021000. Add the node so that boards can reference GPIOs in this
bank, such as status LEDs.
Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com>
Link: https://patch.msgid.link/20260725175346.139173-3-chenyou910331@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
Change the DMA controller compatible to the sophgo,cv1800b-axi-dma,
which supports setting DMA channel number in DMA phandle args.
This dts change does not break backward compatibility as a fallback
compatiable string is added.
Fixes: 514951a81a ("riscv: dts: sophgo: cv18xx: add DMA controller")
Reported-by: Anton D. Stavinskii <stavinsky@gmail.com>
Closes: https://github.com/sophgo/linux/issues/9
Tested-by: Anton D. Stavinskii <stavinsky@gmail.com>
Link: https://patch.msgid.link/20260511063818.463877-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
Enable CPU DVFS on Milk-V Jupiter by including the OPP tables and wiring the
CPU nodes to the CPU regulator supply.
Reviewed-by: Yixun Lan <dlan@kernel.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Link: https://patch.msgid.link/20260729160749.1621415-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Banana Pi BPI-CM6 module, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 46a8c01700 ("riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-7-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the OrangePi R2S board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 793cc54475 ("riscv: dts: spacemit: enable PMIC on OrangePi R2S")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-6-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the MusePi Pro board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: e2dac7c7a3 ("riscv: dts: spacemit: k1-musepi-pro: add PMIC and power infrastructure")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-5-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the OrangePi RV2 board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: c02c047b92 ("riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-4-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Milk-V Jupiter board, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 7d307daa12 ("riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-3-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Banana Pi BPI-F3 board, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 09a412d397 ("riscv: dts: spacemit: define regulator constraints")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
There is just one set of changes that the remaining IO expansion chips
on the TH1520-based LicheePi 4a board.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQSy8G7QpEpV9aCf6Lbb7CzD2SixDAUCamfmlAAKCRDb7CzD2Six
DDehAQChtA/two2PhKC3UEHpwNYI0WGGenAJxWrmL4Pp5IKVYgD/azDUxAEJ7duG
ejz2YONec+NvXG+AZoKxmbKgPzOErgk=
=uG96
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpqAaEACgkQmmx57+YA
GNkJzBAAw6jegV/2venCdwmOJt42vs4+FcDr2Veeyxs90xxZoQ98wTeI9+EUXtjl
uwXshVXtZbvjYecCLSeLAp+sLFHbItofRnAs0CrGrWNn/nwZG0tEW09XUXZVCqcd
YI3jqxCzlXJHeh6IfboTujlniYAePHR5BKqZWymmutyR5dG0+mJWERYqrRl9Gk47
6aCQvFLrLprmMWB4imzHwFpvb3yLdtODm5gdbBi2lZqCa/XRpZsHflyVzp5HAkkM
8xg5lXbzFg/QX9hEXtQkhE3bQGoqa6xF61glZRiU4aqedRENp1GAQ2jQfYMz16k6
W0euAJ/6ks3+fzzbn2QDPTVkWpV2zUxOmtJFWqgm9Q5b2Lrm6rvD+1HTXc7R/EP4
i7qmvqP9Jt8YSGk7+0KEo7nYZgE0sSIHPsBzfIYaOcaxKEwa7X4sXfBY7eH56b3u
UlC/7uxQyyCgU1NqZmF0M5Ya/arqaUSHYHgNbc5WzsRILiDcVX8MmTQMxfYLs40z
dLzgLMQu1XRIvr2s8dkP6VW72HmtvIJG/X1ObRGYMheIZJV8uuQaaQpdimqMd1Ve
qFWroZBj1wqWEA2IX0RousstrwdFPGyYKiK6H0uH0itF42Nm0H4M/Jm9pVaxrJX7
iwL95v7pEwtAz1IiR/KcUwo/FGlAFXzmwy63VojLv+yxmqoGLLE=
=c8kz
-----END PGP SIGNATURE-----
Merge tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
T-HEAD device tree changes for v7.3
There is just one set of changes that the remaining IO expansion chips
on the TH1520-based LicheePi 4a board.
* tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions
riscv: dts: thead: Add IO labels for the IO expansion on I2C1
riscv: dts: thead: lpi4a: sort nodes
riscv: dts: thead: Add TH1520 I2C nodes
riscv: dts: thead: th1520: remove pclk for I2C1
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since the previous commit does not change the phy node name,
the dtschema can not recognize the type of the ethernet phy,
so the following error is produced:
/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$'
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', '
reset-deassert-us', 'reset-gpios' were unexpected)
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
Change the nodename to make the dtschema can recognize the right
PHY type.
Fixes: 9db839d52c ("riscv: dts: spacemit: Fix phy id check for the phy on com260 board")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729012418.154652-2-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Since the previous commit does not change the phy node name,
the dtschema can not recognize the type of the ethernet phy,
so the following error is produced:
/arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$'
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
/arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', 're
set-deassert-us', 'reset-gpios' were unexpected)
from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml
Change the nodename to make the dtschema can recognize the right
PHY type.
Fixes: 6d6536c880 ("riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729012418.154652-1-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add the six SSPA-based I2S controller nodes for the K3 SoC.
i2s0 and i2s2-i2s5 each have a dedicated per-controller sysclk
divider, so they use the published 7-clock layout (sysclk, bclk, bus,
func, sysclk_div, c_sysclk, c_bclk).
i2s1 uses 6 clocks (sysclk, bclk, bus, func, c_sysclk, c_bclk) because
its sysclk is driven directly by a DDN (ISCCR0) and has no separate
divider stage.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260721-kx-i2s-dts-v1-3-d22cb6cfaab5@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Enable the two RTL8125 network controllers and corresponding
PHYs connected via the PCIe controllers on the OrangePi R2S.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260602100000.2402784-1-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>
Enable i2c1 for k3-com260-ifx and use it for a 24c02 eeprom. This
eeprom, unlike the one connected to i2c2, is part of the carrier board.
Some boards do not have any data programmed on this eeprom from factory.
Signed-off-by: Jennifer Berringer <jberring@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260722202848.1817988-3-jberring@redhat.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Enable i2c2 on the K3 CoM260 compute module and use it for a 24c02
eeprom. This eeprom stores the product name, a MAC address, and a serial
number.
Signed-off-by: Jennifer Berringer <jberring@redhat.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260722202848.1817988-2-jberring@redhat.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add a local DTS header that gives symbolic names to the SpacemiT K3
PDMA request lines of the non-secure peripherals. Device trees can use
these K3_PDMA_* macros instead of hard-coded request numbers when wiring
a peripheral "dmas" property.
Signed-off-by: liyeshan <yeshan.li@spacemit.com>
Signed-off-by: Guodong Xu <docular.xu@gmail.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-1-969a1b0f783f@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Current phy framework can not re-initialize the phy correctly, as it will
assert the phy reset GPIO so the phy id can not be read. Setting the
phy id of board com260 manually so the phy id dectection can be skipped.
Fixes: cfe5c91cb7 ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260725233351.55004-3-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Current phy framework can not re-initialize the phy correctly, as it will
assert the phy reset GPIO so the phy id can not be read. Setting the
phy id of board pico-itx manually so the phy id detection can be skipped.
Fixes: 74657a3769 ("riscv: dts: spacemit: Add ethernet device for K3")
Reported-by: E Shattow <e@freeshell.de>
Reported-by: Inochi Amaoto <inochiama@gmail.com>
Closes: https://lore.kernel.org/netdev/20260712045233.800748-1-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: E Shattow <e@freeshell.de>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260725233351.55004-2-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
RTL8211F require at least 50ms deassert to guarantee the register
access, 10ms is only enough for the PHY reset.
Fixes: cfe5c91cb7 ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://patch.msgid.link/20260710063314.1030249-2-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
RTL8211F require at least 50ms deassert to guarantee the register
access, 10ms is only enough for the PHY reset.
Fixes: 74657a3769 ("riscv: dts: spacemit: Add ethernet device for K3")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Tested-by: E Shattow <e@freeshell.de>
Link: https://patch.msgid.link/20260710063314.1030249-1-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Canaan:
Support for the k230 SoC that was too late for the 7.2 window.
Consists of some bindings not taken by the various subsystem
maintainers, the original dts patches from Yangyu back in 2024
and the more recent clock, reset and pinctrl additions from various
contributors.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCalE3fgAKCRB4tDGHoIJi
0tjdAQDTii/S9gka/j8cHfv3GGIEdMzGO6U+Y+c8IKp5W2S6BQEA/b62Eo2jBJUf
D6hJ6K5POTzqoB6bw/VaKxVN2ssVSw4=
=6yLO
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpjksAACgkQmmx57+YA
GNkjQg//b8WU1gJgM/n65o8ejebUaRER5sugfa7wqGpXL7MP/xXog+ij1+h8mVrS
6KWjfvkzFfYKrGIxWEqOH52swcDQqRwyIC6YGJ9y+qARtDNqHpk/GskashVaerE4
JuQQUF+Akq9ULoFWPFzdtibFTe+Abee7IP9fs0atmnMY/aToJdQRIpEKL1QnKM/i
n8iO/+zNSIjD99Bi5CB4l89MnRAetbjKge8/havd533qEs91WqhnAtPUdehbZFJA
5upjsN8dzSnuqj7mf2tmL80hXx84ijkgkS7cxCyqTLYIh31yywtnvzExObMXn507
1Dy2WmKNaCPkvYFMb4Y5LkMBmGWAQaknCq4xQdMnPjCwcXjE/kJRFU4D9mTc2kNI
Zom6K6WFQp4SAoYkaZXqk6UOjN0Chd5B1lW3dMbdMbeeCxx7tIjsI9+FN0eN26f1
94GRmn+E/Qm0973sfyJMZc7F9UDcV4Dm7cD5yn8oTCztaoRZSj09gYSDohAnt6CG
8K1vr93g6FotF0ANU2zljVtfQqXMJfPsemccK1GYcZzx3nuuT1cygK9lDYEzIxJC
PytIi7K7hx1zRXN5/cLGKB0gXdmd0Onpj0MIUvOGphNjpfYRdc2J59xJ8jMvxXFl
CYbd8m4RkMGAHZyOhkQwNtH0cE+zR+areE2TI3cETbL+HteP588=
=ZTqc
-----END PGP SIGNATURE-----
Merge tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V devicetrees for v7.3 - early k230 material
Canaan:
Support for the k230 SoC that was too late for the 7.2 window.
Consists of some bindings not taken by the various subsystem
maintainers, the original dts patches from Yangyu back in 2024
and the more recent clock, reset and pinctrl additions from various
contributors.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: canaan: Add clock definition for K230
riscv: dts: canaan: add reset controller for K230
riscv: dts: canaan: k230: Add "b" ISA extension
riscv: dts: canaan: Add k230's pinctrl node
riscv: dts: canaan: Correct the formatting issues about k230 dts
riscv: dts: add initial canmv-k230 and k230-evb dts
dt-bindings: interrupt-controller: Add Canaan K230 PLIC
dt-bindings: timer: Add Canaan K230 CLINT
dt-bindings: add Canaan K230 boards compatible strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the
I2C0/1/3 busses. The I2C1 one is already added to the device tree, but
the I2C0/3 ones are not yet added.
Add device tree nodes for them.
Link: https://lore.kernel.org/r/20260714074515.1959352-6-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[Icenowy: added commit description, enable SoC pull-up, remove I2C1 and
aliases]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Add labels for GPIOs on the IO expansion chip on the I2C1 bus.
Link: https://lore.kernel.org/r/20260714074515.1959352-5-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[Icenowy: Splitted off the patch adding all 3 IO expansions]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
[fustini: align ioexp2 gpio-line-names with schematic]
Signed-off-by: Drew Fustini <fustini@kernel.org>
Although "D", "H" and "I" are earlier in the alphabet than "P", the DPU,
HDMI and I2C1 nodes were added after PADCTRL nodes in the Lichee Pi 4A
device tree; in addition the PADCTRL1 node is placed before the
PADCTRL0 one.
Sort the nodes in this device tree.
Link: https://lore.kernel.org/r/20260714074515.1959352-4-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Add nodes for the remaining five I2C controllers on the T-Head TH1520
RISCV SoC.
Link: https://lore.kernel.org/r/20260714074515.1959352-3-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
[Icenowy: rebase and reword commit message to exclude I2C1]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Signed-off-by: Drew Fustini <fustini@kernel.org>
The I2C1 node added previously to the th1520.dtsi file has two clocks
set -- one "ref" clock (CLK_I2C1) and one "pclk" (CLK_PERI_APB_PCLK).
However, the CLK_I2C1 clock is just a clock gate with the
CLK_PERI_APB_PCLK clock as its input. In addition, when it's gated,
reading registers from the I2C controller returns fixed value (the last
read value) for all registers. These facts indicate that the CLK_I2C1
clock is the true APB clock fed into the I2C controller instead of a
dedicated reference clock.
Leave only the CLK_I2C1 clock as the `clocks` property of the I2C1
device node and remove `clock-names` property, which represents the I2C
controller only takes a single clock both as the APB clock and the
reference clock.
Fixes: 2f60e35163 ("riscv: dts: thead: Add TH1520 I2C1 controller")
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Link: https://lore.kernel.org/r/20260714074515.1959352-2-zhengxingda@iscas.ac.cn
Signed-off-by: Drew Fustini <fustini@kernel.org>
The Banana Pi BPI-CM6 IO board combines the BPI-CM6 compute module with
an IO carrier board. The core module integrates the SpacemiT K1 SoC,
PMIC, DDR, eMMC, the eth0 PHY, and wireless connectivity. The companion
IO carrier board extends it by providing the eth1 PHY and exposing
standard interfaces, including dual Gigabit Ethernet, MicroSD, two USB-A
ports, a USB Type-C port, two PCIe M.2 slots, and a serial console.
The board also has two I2C EEPROMs. One is on the core module, which
stores factory manufacturing data and is marked read-only. The other is
on the carrier board, which is shipped unprogrammed and left writable
for evaluation purposes.
Add initial support for UART console, eMMC, SD card, I2C, EEPROMs,
PCIe, USB, and dual Ethernet interfaces.
Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6
Reviewed-by: Michael Opdenacker <michael.opdenacker@rootcommit.com>
Tested-by: Michael Opdenacker <michael.opdenacker@rootcommit.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260712-bpi-cm6-v3-3-8d1e2045179d@pigmoral.tech
Signed-off-by: Yixun Lan <dlan@kernel.org>
The gmac_clk_ref signal is optional for the GMAC controller and is not
strictly required for all hardware designs. The pins for gmac0_clk_ref
(GPIO 45) and gmac1_clk_ref (GPIO 46) may also be used as GPIOs for
other functions even when the Ethernet controller is active.
Split the refclk pins into independent pinctrl groups so boards can
request them only when the reference clock path is actually needed.
Among the already mainlined boards, BPI-F3, Jupiter and MusePi Pro have
optional hardware paths for the GMAC refclk pins. BPI-F3 and Jupiter
route both GMAC refclk pins to the PHYs through NC/0R option resistors,
while MusePi Pro only does so for GMAC0. Keep referencing the new
clk-ref pinctrl groups on these boards so the optional hardware paths
remain usable if the option resistors are populated.
OrangePi R2S has no publicly available schematic, so also keep the
clk-ref groups there to preserve the previous pinmux behavior.
Fixes: 60775f28cf ("riscv: dts: spacemit: Add Ethernet support for K1")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260712-bpi-cm6-v3-2-8d1e2045179d@pigmoral.tech
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add CPU clock properties and OPP tables for the two CPU clusters in the
SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU
supply is shared by both clusters.
Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and
wiring the CPU nodes to the CPU regulator supply.
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
Tested-by: Andre Heider <a.heider@gmail.com> # k1-musepi-pro
Reviewed-by: Yixun Lan <dlan@kernel.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Tested-by: Gong Shuai <gsh517025@gmail.com> # OrangePi-RV2
Link: https://patch.msgid.link/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
Enable QSPI with proper pinmux on the Pico-ITX board, and describe the
NOR flash wired to it.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
Vendor kernel enabled ALDPS (Advanced Link Down Power Saving) on the
RTL8211F PHY to save power when link down.
Vendor kernel also disabled the 125MHz clkout clock signal, and indeed
the schematics confirms that it only goes to a test point (TP14), so
let's do the same.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Yixun Lan <dlan@kernel.org>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-6-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add i2c aliases for i2c2 and i2c8 on K3 Pico-ITX board. This is useful
to keep a stable number for the /dev entries after loading the i2c-dev
module.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-5-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
The K3 Pico-ITX board includes a 24c02 eeprom, that stores the product
name, the part name, the MAC address of the network interfaces and the
board's serial number. These values are also exposed via an
onie,tlv-layout nvmem layout.
The eeprom is marked as read-only since its contents are not supposed to
be modified.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-4-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Define I2C2 pinctrl properties, and enable it on the K3 Pico-ITX board.
It will be used by the 24c02 eeprom.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-3-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Because the default console's baud rate is not set, defconfig kernels do
not have any serial output on this platform. Set the baud rate to
115200, matching what is used by U-Boot etc on this platform.
Fixes: 7a61318049 ("riscv: dts: spacemit: add K3 Pico-ITX board support")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Guodong Xu <docular.xu@gmail.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260623204431.498700-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
Add the device tree node of SDHCI-0 controller which found on CoM260-IFX
board, it's currenty used for Micro SD card slot, and one GPIO pin is
configured as card insertion/removal detection pin, the slot use 4-bit
data bus, and up support to SDR104 speed mode.
Link: https://patch.msgid.link/20260610-07-k3-enable-sd-v1-1-196ae29bd091@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
There are fewer devicetree updates this time that the last few ones, with
five SoC types getting added:
- Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using
four Cortex-A55 and one Cortex-A78 core, which is a significant
upgrade from older generations
- ZTE zx297520v3 is an older low-end wireless SoC using a single
Cortex-A53 core, which so far can only run 32-bit kernels. This brings
back the ZX family of chips that was removed in 2021 after support
for the original zx296702 and zx296718 chips was never completed.
- Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N (R8A77965)
automotive SoC.
- Apple t8122 (M3) is the 2023 generation of their laptop SoCs,
which has now been reverse-engineered to the point of having initial
kernel support for five laptop models.
- ASPEED AST27xx is their first baseboard managment controller using
a 64-bit core, the Cortex-A35, following earlier generations using
ARMv5/v6/v7 CPUs.
These all come with one or more initial boards, and in total there
are 39 new boards getting added across SoC families, including:
- Two NAS boxes using the old Cortina Systems Gemini SoC based on
an ARMv4 FA526 CPU core
- 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A
SoCs from Variscite, Toradex and SolidRun, plus a number of
overlays for combinations with additional boards
- One new carrier board and SoM using TI K3 AM62x, in addition to
new overlays for older SoMs
- Two new boards using Spacemit K3 (no relation with TI) RISC-V
SoCs.
- Three phones from Google, Nothing and Motorola, all using Qualcomm
Snapdragon SoCs
- AST26xx BMC support for two server boards
While there is still a significant number of patches improving hardware
support for the existing boards across vendors (NXP, Qualcomm, Renesas,
Rockchips, Mediatek, ...), a much smaller number of cleanups and warning
fixes have made it in this time.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmovyQ0ACgkQmmx57+YA
GNmE2hAAk4UguDtXr6fCYcIiBGqEtKhPmuvD98edmRyemg1x3ZbHIZn52rUqKFoz
HDi1BL7NkKdDuIWJ5DvqyHGLMg6kCEbiYSsjdkjN2Hcsx+I8NtokCR0hRtteNPQ9
f6kgDj9+VsWvXTsYKFU87qkK1bC5nVrLS7xxIuuCIYxULvSEX5GGJbHQ93qxNUam
6GrFcDHnozh9OfETSBw9bME16FiMxapgghPxMaAmVzuB+iGr4xyrEHmyu9gThsuJ
O2P04LIhu9j9CZOjaJ54+v41AtMIVE7xG1+MUC5JcWBc7OMVLE30uGgsW9jBKaii
Wsxa3D08+m1JYeFbhJR6tWAf4HbIEpudEoJmlSdwRhvYte15kU90f917aTNFYBow
sBf6G09t4ZLsDr9NzCx+cWUnoVLdlYv4auRGNxoWsxe4ed9G6c+yiZN2pBaFNXuT
wNJqrFstS9mszBaPItgt4e5Tck+IB0uKNqhbSWa3rFyKrXQ9SpZOKVN6cPlwFjhT
wWYZcAzUL8n2Sz71l/U/QqjN6hqnZWFghe9B3wr81/XQ4sPjWHWoTeRfnees+vFM
LtE77TGPW2KdZpRI38qfyKWWH3PwKaTtZ07ne8NOvh60zmhK+uUFGzzWAhKlO/Z2
a3tX8evXRTOb5NrvWzGlwpPwtE0R71oRIwxG1MlmFdlJzddI4Xc=
=EhYX
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are fewer devicetree updates this time that the last few ones,
with five SoC types getting added:
- Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using
four Cortex-A55 and one Cortex-A78 core, which is a significant
upgrade from older generations
- ZTE zx297520v3 is an older low-end wireless SoC using a single
Cortex-A53 core, which so far can only run 32-bit kernels. This
brings back the ZX family of chips that was removed in 2021 after
support for the original zx296702 and zx296718 chips was never
completed.
- Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N
(R8A77965) automotive SoC.
- Apple t8122 (M3) is the 2023 generation of their laptop SoCs, which
has now been reverse-engineered to the point of having initial
kernel support for five laptop models.
- ASPEED AST27xx is their first baseboard managment controller using
a 64-bit core, the Cortex-A35, following earlier generations using
ARMv5/v6/v7 CPUs.
These all come with one or more initial boards, and in total there are
39 new boards getting added across SoC families, including:
- Two NAS boxes using the old Cortina Systems Gemini SoC based on an
ARMv4 FA526 CPU core
- 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A SoCs
from Variscite, Toradex and SolidRun, plus a number of overlays for
combinations with additional boards
- One new carrier board and SoM using TI K3 AM62x, in addition to new
overlays for older SoMs
- Two new boards using Spacemit K3 (no relation with TI) RISC-V SoCs.
- Three phones from Google, Nothing and Motorola, all using Qualcomm
Snapdragon SoCs
- AST26xx BMC support for two server boards
While there is still a significant number of patches improving
hardware support for the existing boards across vendors (NXP,
Qualcomm, Renesas, Rockchips, Mediatek, ...), a much smaller number
of cleanups and warning fixes have made it in this time"
* tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (665 commits)
arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme
arm64: dts: bst: enable eMMC controller in C1200
dt-bindings: display/lvds-codec: add ti,sn65lvds93
arm64: dts: allwinner: a523: Add missing GPIO interrupt
arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap
arm64: dts: aspeed: Add initial AST27xx SoC device tree
arm64: Kconfig: Add ASPEED SoC family Kconfig support
dt-bindings: arm: aspeed: Add AST2700 board compatible
arm64: dts: allwinner: a523: add gpadc node
arm64: dts: allwinner: Add EL2 virtual timer interrupt
ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties
dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties
arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays
arm64: dts: imx93-var-som-symphony: enable ADC
arm64: dts: imx93-var-som-symphony: enable TPM3 PWM
arm64: dts: imx93-var-som-symphony: keep RGB_SEL low
arm64: dts: imx93-var-som-symphony: enable UART7
arm64: dts: imx93-var-som-symphony: add TPM support
arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling
...
