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0016763663
Update the register definition for GRBM_SOFT_RESET to match what was in the old radeon driver and use these bits in the soft reset implementation. For the soft reset, use basically the same implementation as GFX7-8, the main difference being the GRBM_SOFT_RESET bit fields and the fact that GFX6 doesn't have MQD/HQD. Reset every block using the GRBM, then proceed to reset the GRBM and SEM blocks using the SRBM. The soft reset also calls the clock and powergating functions of the IP block. This is necessary for correct operation, otherwise the GPU might fall off the PCIe bus. Add a gfx_v6_0_late_init() function for consistency with other GPU generations. This function will later serve the same purpose as it does on GFX7+ when we get around to enable more IRQs on GFX6. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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| athub | ||
| bif | ||
| clk | ||
| dce | ||
| dcn | ||
| df | ||
| dpcs | ||
| gc | ||
| gca | ||
| gmc | ||
| hdp | ||
| lsdma | ||
| mmhub | ||
| mp | ||
| nbif | ||
| nbio | ||
| oss | ||
| pcie | ||
| pwr | ||
| rsmu | ||
| sdma | ||
| sdma0 | ||
| sdma1 | ||
| sdma2 | ||
| sdma3 | ||
| sdma4 | ||
| sdma5 | ||
| sdma6 | ||
| sdma7 | ||
| smu | ||
| smuio | ||
| thm | ||
| umc | ||
| uvd | ||
| vce | ||
| vcn | ||
| vpe | ||
| wafl | ||
| xgmi | ||