Francis Marlou Pacaro 2ac2fe765e drm/amd/display: fix MALL hysteresis timer underflow at high refresh rates ... dcn30_apply_idle_power_optimizations() derives the MALL frame cache hysteresis timer with tmr_delay = (uint32_t)(div_u64(..., denom) - 64LL); div_u64() returns a u64, so when the quotient is smaller than 64 the subtraction wraps instead of going negative and tmr_delay ends up huge. The loop that follows tries to squeeze it into the 6 bit register field by doubling denom, but that only makes the quotient smaller, so tmr_delay can never converge. tmr_scale is bumped past 3 and the function gives up with /* Delay exceeds range of hysteresis timer */ ASSERT(false); even though the requested delay is too *short* to encode, not too long. With mall_additional_timer_percent left at its default of 0, the quotient drops below 64 once the refresh rate used for the calculation goes above ~243 Hz. Every DCN 3.0 display above that loses MALL static screen entirely and splats a WARN once per boot. Reproduced on Navi 23 (RX 6600) driving 1920x1080, resetting /sys/kernel/debug/clear_warn_once between modes: refresh MALL ASSERT 144 Hz enabled no 240 Hz enabled no 280 Hz skipped yes 360 Hz skipped yes Commit 3bb68cec4d ("drm/amd/display: Add Overflow check to skip MALL") already covered the other end of the range, where a large stutter period makes the delay too long to encode. Cover the short end by clamping to 0, which selects the shortest hysteresis the register can express, 65.28us * 64 = ~4.18ms. That is marginally longer than what the formula asks for at these refresh rates, and erring long is the safe direction: it only delays MALL entry, it can never enter early. The numerator does not change between iterations, only denom does, so compute it once and keep both call sites inside 100 columns. The genuinely out of range case at very low refresh rates still reaches the ASSERT, which is where it belongs. Fixes: 52f2e83e2f ("drm/amdgpu/display: add MALL support (v2)") Signed-off-by: Francis Marlou Pacaro <pacaro.francis.marlou.n@gmail.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 387550e53e1405f1f960b62b22f8783db17c8e1d)		2026-09-17 11:59:24 -04:00
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acp
amdgpu	drm/amdgpu: fix rmmio iounmap skipped on device removal	2026-09-17 11:58:48 -04:00
amdkfd	drm/amdkfd: Avoid integer underflow in EOP ring size calculation.	2026-09-17 11:56:45 -04:00
amdxcp	drm/amdxcp: Add more checks to amdxcp	2026-06-17 16:21:58 -04:00
display	drm/amd/display: fix MALL hysteresis timer underflow at high refresh rates	2026-09-17 11:59:24 -04:00
include	drm/amdgpu/gfx6: Add IP block soft reset implementation	2026-08-06 12:47:46 -04:00
pm	drm/amd/pm: report energy accumulator for smu 14.0.3	2026-09-17 11:51:15 -04:00
ras	treewide: refresh kmalloc_obj() conversions	2026-09-04 21:37:00 -07:00