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drm/amd: Add register header files for DCN42B

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[Why & How]
Add register headers for:

- clk 15.0.5
- dcn 4.2.1
- dpcs 4.0.1
- nbio 7.15.5

v2: add in missing license (Alex)

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart 2026-05-18 18:12:26 -04:00 committed by Alex Deucher
parent 7d44737067
commit 1a1751507e
6 changed files with 77537 additions and 0 deletions
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42
drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_offset.h Normal file
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _clk_15_0_5_OFFSET_HEADER
#define _clk_15_0_5_OFFSET_HEADER
// addressBlock: clk_clk5_0_SmuClkDec
// base address: 0x6c800
#define regCLK5_CLK0_DS_CNTL 0x4604
#define regCLK5_CLK0_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK0_BYPASS_CNTL 0x460a
#define regCLK5_CLK0_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK1_DS_CNTL 0x460c
#define regCLK5_CLK1_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK1_BYPASS_CNTL 0x4612
#define regCLK5_CLK1_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK2_DS_CNTL 0x4614
#define regCLK5_CLK2_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK2_BYPASS_CNTL 0x461a
#define regCLK5_CLK2_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK3_DS_CNTL 0x461c
#define regCLK5_CLK3_DS_CNTL_BASE_IDX 0
#define regCLK5_CLK3_BYPASS_CNTL 0x4622
#define regCLK5_CLK3_BYPASS_CNTL_BASE_IDX 0
#define regCLK5_CLK_TICK_CNT_CONFIG_REG 0x4629
#define regCLK5_CLK_TICK_CNT_CONFIG_REG_BASE_IDX 0
#define regCLK5_CLK_TICK_CNT_STATUS 0x462a
#define regCLK5_CLK_TICK_CNT_STATUS_BASE_IDX 0
#define regCLK5_CLK0_CURRENT_CNT 0x462b
#define regCLK5_CLK0_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK1_CURRENT_CNT 0x462c
#define regCLK5_CLK1_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK2_CURRENT_CNT 0x462d
#define regCLK5_CLK2_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK3_CURRENT_CNT 0x462e
#define regCLK5_CLK3_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK4_CURRENT_CNT 0x462f
#define regCLK5_CLK4_CURRENT_CNT_BASE_IDX 0
#define regCLK5_CLK5_CURRENT_CNT 0x4630
#define regCLK5_CLK5_CURRENT_CNT_BASE_IDX 0
#endif

45
drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h Normal file
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _clk_15_0_5_SH_MASK_HEADER
#define _clk_15_0_5_SH_MASK_HEADER
// addressBlock: clk_clk5_0_SmuClkDec
//CLK5_CLK_TICK_CNT_CONFIG_REG
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT 0x0
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK 0x00FFFFFFL
//CLK5_CLK0_BYPASS_CNTL
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK1_BYPASS_CNTL
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK2_BYPASS_CNTL
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK3_BYPASS_CNTL
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L
//CLK5_CLK0_DS_CNTL
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK 0x00000010L
//CLK5_CLK1_DS_CNTL
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK 0x00000010L
//CLK5_CLK2_DS_CNTL
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK 0x00000010L
//CLK5_CLK3_DS_CNTL
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x0000000FL
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT 0x4
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK 0x00000010L
#endif

16305
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_1_offset.h Normal file
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60623
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_1_sh_mask.h Normal file
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109
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_offset.h Normal file
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _dpcs_4_0_1_OFFSET_HEADER
#define _dpcs_4_0_1_OFFSET_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
// base address: 0x0
#define regDC_GENERICA 0x2868
#define regDC_GENERICA_BASE_IDX 2
#define regDC_GENERICB 0x2869
#define regDC_GENERICB_BASE_IDX 2
#define regDCIO_CLOCK_CNTL 0x286a
#define regDCIO_CLOCK_CNTL_BASE_IDX 2
#define regDC_REF_CLK_CNTL 0x286b
#define regDC_REF_CLK_CNTL_BASE_IDX 2
#define regUNIPHYA_LINK_CNTL 0x286d
#define regUNIPHYA_LINK_CNTL_BASE_IDX 2
#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYB_LINK_CNTL 0x286f
#define regUNIPHYB_LINK_CNTL_BASE_IDX 2
#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYC_LINK_CNTL 0x2871
#define regUNIPHYC_LINK_CNTL_BASE_IDX 2
#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYD_LINK_CNTL 0x2873
#define regUNIPHYD_LINK_CNTL_BASE_IDX 2
#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYE_LINK_CNTL 0x2875
#define regUNIPHYE_LINK_CNTL_BASE_IDX 2
#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regDCIO_WRCMD_DELAY 0x287e
#define regDCIO_WRCMD_DELAY_BASE_IDX 2
#define regDC_PINSTRAPS 0x2880
#define regDC_PINSTRAPS_BASE_IDX 2
#define regDCIO_SPARE 0x2882
#define regDCIO_SPARE_BASE_IDX 2
#define regINTERCEPT_STATE 0x2884
#define regINTERCEPT_STATE_BASE_IDX 2
#define regDCIO_PATTERN_GEN_PAT 0x2886
#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2
#define regDCIO_PATTERN_GEN_EN 0x2887
#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2
#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define regDPCS_DCIO_TEST_CLK_SRC 0x2890
#define regDPCS_DCIO_TEST_CLK_SRC_BASE_IDX 2
#define regDCIO_DEBUG 0x2897
#define regDCIO_DEBUG_BASE_IDX 2
#define regDCIO_TEST_DEBUG_INDEX 0x2899
#define regDCIO_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDCIO_TEST_DEBUG_DATA 0x289a
#define regDCIO_TEST_DEBUG_DATA_BASE_IDX 2
#define regDBG_OUT_CNTL 0x289c
#define regDBG_OUT_CNTL_BASE_IDX 2
#define regDCIO_DEBUG_CONFIG 0x289d
#define regDCIO_DEBUG_CONFIG_BASE_IDX 2
#define regDCIO_SOFT_RESET 0x289e
#define regDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_DDC1_MASK 0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX 2
#define regDC_GPIO_DDC2_MASK 0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX 2
#define regDC_GPIO_DDC3_MASK 0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_MASK 0x28e8
#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_A 0x28e9
#define regDC_GPIO_DDCVGA_A_BASE_IDX 2
#define regDC_GPIO_DDCVGA_EN 0x28ea
#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define regDC_GPIO_DDCVGA_Y 0x28eb
#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define regDC_GPIO_PWRSEQ0_EN 0x28fa
#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2
#define regDC_GPIO_PAD_STRENGTH_1 0x28fc
#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define regPHY_AUX_CNTL 0x28ff
#define regPHY_AUX_CNTL_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_0 0x2916
#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_1 0x2917
#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_3 0x291b
#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_4 0x291c
#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_5 0x291d
#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define regAUXI2C_PAD_ALL_PWR_OK 0x291e
#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
#endif

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drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_sh_mask.h Normal file
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// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _dpcs_4_0_1_SH_MASK_HEADER
#define _dpcs_4_0_1_SH_MASK_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
//DC_GENERICA
#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
//DC_GENERICB
#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
//DCIO_CLOCK_CNTL
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
//DC_REF_CLK_CNTL
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
//UNIPHYA_LINK_CNTL
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYA_CHANNEL_XBAR_CNTL
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYB_LINK_CNTL
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYB_CHANNEL_XBAR_CNTL
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYC_LINK_CNTL
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYC_CHANNEL_XBAR_CNTL
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYD_LINK_CNTL
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYD_CHANNEL_XBAR_CNTL
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//UNIPHYE_LINK_CNTL
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
//UNIPHYE_CHANNEL_XBAR_CNTL
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L
//DCIO_WRCMD_DELAY
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L
//DC_PINSTRAPS
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L
//DCIO_SPARE
#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0
#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL
//INTERCEPT_STATE
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0
#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT 0x2
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8
#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE__SHIFT 0x10
#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE__SHIFT 0x11
#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE__SHIFT 0x12
#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE__SHIFT 0x13
#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE__SHIFT 0x14
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L
#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK 0x00000004L
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L
#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE_MASK 0x00010000L
#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE_MASK 0x00020000L
#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE_MASK 0x00040000L
#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE_MASK 0x00080000L
#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE_MASK 0x00100000L
//DCIO_PATTERN_GEN_PAT
#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0
#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL
//DCIO_PATTERN_GEN_EN
#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0
#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L
//DCIO_BL_PWM_FRAME_START_DISP_SEL
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L
//DCIO_GSL_GENLK_PAD_CNTL
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
//DCIO_GSL_SWAPLOCK_PAD_CNTL
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
//DPCS_DCIO_TEST_CLK_SRC
#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL__SHIFT 0x0
#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL_MASK 0x00000007L
//DCIO_TEST_DEBUG_INDEX
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000FFL
//DCIO_TEST_DEBUG_DATA
#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
//DBG_OUT_CNTL
#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL__SHIFT 0x0
#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL__SHIFT 0x5
#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA__SHIFT 0xc
#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL_MASK 0x00000003L
#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL_MASK 0x000000E0L
#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA_MASK 0x00FFF000L
//DCIO_DEBUG_CONFIG
#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x00000001L
//DCIO_SOFT_RESET
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10
#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT 0x14
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L
#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK 0x00100000L
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
//DC_GPIO_DDC1_MASK
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
//DC_GPIO_DDC2_MASK
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
//DC_GPIO_DDC3_MASK
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
//DC_GPIO_DDCVGA_MASK
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
//DC_GPIO_DDCVGA_A
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
//DC_GPIO_DDCVGA_EN
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
//DC_GPIO_DDCVGA_Y
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
//DC_GPIO_PWRSEQ0_EN
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L
//DC_GPIO_PAD_STRENGTH_1
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
//PHY_AUX_CNTL
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L
//DC_GPIO_AUX_CTRL_0
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L
//DC_GPIO_AUX_CTRL_1
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L
//DC_GPIO_AUX_CTRL_3
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L
//DC_GPIO_AUX_CTRL_4
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L
//DC_GPIO_AUX_CTRL_5
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L
//AUXI2C_PAD_ALL_PWR_OK
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L
#endif