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drm/amd: Add DCN6 register headers

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Add new headers for:
- dcn 6.0.0
- dpcs 6.0.0
- mmhub 5.0.1

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2026-07-22 14:44:37 -04:00 committed by Alex Deucher
parent 7f48fa2cf6
commit fe219bd7d9
6 changed files with 74491 additions and 0 deletions
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15799
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_6_0_0_offset.h Normal file
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58556
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_6_0_0_sh_mask.h Normal file
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47
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_6_0_0_offset.h Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
*/
#ifndef _dpcs_6_0_0_OFFSET_HEADER
#define _dpcs_6_0_0_OFFSET_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
// base address: 0x0
#define regHPD_CTRL 0x286c
#define regHPD_CTRL_BASE_IDX 2
#define regDC_PINSTRAPS 0x2880
#define regDC_PINSTRAPS_BASE_IDX 2
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_DDC1_MASK 0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX 2
#define regDC_GPIO_DDC2_MASK 0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX 2
#define regDC_GPIO_DDC3_MASK 0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX 2
#define regDC_GPIO_DDC4_MASK 0x28dc
#define regDC_GPIO_DDC4_MASK_BASE_IDX 2
#define regPHY_AUX_CNTL 0x28ff
#define regPHY_AUX_CNTL_BASE_IDX 2
#define regDC_GPIO_AUX_CTRL_5 0x291d
#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2
// addressBlock: dpcssys_dcio_i3c_pad_control_ddc1_dc_i3c_dispdec
// base address: 0x0
#define regDC_I3C0_DC_I3CPAD_CONTROL0 0x2f6c
#define regDC_I3C0_DC_I3CPAD_CONTROL0_BASE_IDX 2
#define regDC_I3C0_DC_I3CPAD_CONTROL1 0x2f6d
#define regDC_I3C0_DC_I3CPAD_CONTROL1_BASE_IDX 2
// addressBlock: dpcssys_dcio_i3c_pad_control_ddc2_dc_i3c_dispdec
// base address: 0x8
#define regDC_I3C1_DC_I3CPAD_CONTROL0 0x2f6e
#define regDC_I3C1_DC_I3CPAD_CONTROL0_BASE_IDX 2
#define regDC_I3C1_DC_I3CPAD_CONTROL1 0x2f6f
#define regDC_I3C1_DC_I3CPAD_CONTROL1_BASE_IDX 2
#endif

55
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_6_0_0_sh_mask.h Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
*/
#ifndef _dpcs_6_0_0_SH_MASK_HEADER
#define _dpcs_6_0_0_SH_MASK_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
//HPD_CTRL
#define HPD_CTRL__HPD1_Y_POL_INVERT__SHIFT 0x0
#define HPD_CTRL__HPD2_Y_POL_INVERT__SHIFT 0x1
#define HPD_CTRL__HPD3_Y_POL_INVERT__SHIFT 0x2
#define HPD_CTRL__HPD4_Y_POL_INVERT__SHIFT 0x3
#define HPD_CTRL__HPD1_Y_POL_INVERT_MASK 0x00000001L
#define HPD_CTRL__HPD2_Y_POL_INVERT_MASK 0x00000002L
#define HPD_CTRL__HPD3_Y_POL_INVERT_MASK 0x00000004L
#define HPD_CTRL__HPD4_Y_POL_INVERT_MASK 0x00000008L
//DC_PINSTRAPS
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
//DC_GPIO_DDC1_MASK
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
// addressBlock: dpcssys_dcio_i3c_pad_control_ddc1_dc_i3c_dispdec
//DC_I3C0_DC_I3CPAD_CONTROL0
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DDCCLK_MASK__SHIFT 0x0
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DDCDATA_MASK__SHIFT 0x1
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_PD_EN__SHIFT 0x3
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_CLK_A__SHIFT 0x5
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DATA_A__SHIFT 0x8
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_CLK_EN__SHIFT 0xc
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DATA_EN__SHIFT 0x10
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_CLK_Y__SHIFT 0x14
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DATA_Y__SHIFT 0x18
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DDCCLK_MASK_MASK 0x00000001L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DDCDATA_MASK_MASK 0x00000002L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_PD_EN_MASK 0x00000018L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_CLK_A_MASK 0x00000020L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DATA_A_MASK 0x00000100L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_CLK_EN_MASK 0x00001000L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DATA_EN_MASK 0x00010000L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_CLK_Y_MASK 0x00100000L
#define DC_I3C0_DC_I3CPAD_CONTROL0__DC_I3CPAD_DATA_Y_MASK 0x01000000L
//DC_I3C0_DC_I3CPAD_CONTROL1
#define DC_I3C0_DC_I3CPAD_CONTROL1__DC_I3CPAD_STR__SHIFT 0x0
#define DC_I3C0_DC_I3CPAD_CONTROL1__DC_I3CPAD_RXSEL__SHIFT 0x6
#define DC_I3C0_DC_I3CPAD_CONTROL1__DC_I3CPAD_STR_MASK 0x0000000FL
#define DC_I3C0_DC_I3CPAD_CONTROL1__DC_I3CPAD_RXSEL_MASK 0x000000C0L
#endif

17
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_offset.h Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
*/
#ifndef _mmhub_5_0_1_OFFSET_HEADER
#define _mmhub_5_0_1_OFFSET_HEADER
// addressBlock: mmhub_mmhubdec
#define regMMMC_VM_FB_LOCATION_BASE 0x05d0
#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1
#define regMMMC_VM_FB_OFFSET 0x0803
#define regMMMC_VM_FB_OFFSET_BASE_IDX 1
#endif

17
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_5_0_1_sh_mask.h Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
*/
#ifndef _mmhub_5_0_1_SH_MASK_HEADER
#define _mmhub_5_0_1_SH_MASK_HEADER
//MMMC_VM_FB_LOCATION_BASE
#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
//MMMC_VM_FB_OFFSET
#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
#endif