qcom_regmap_list can get corrupted if multiple clock controllers
probe at same time. Add mutex lock to avoid list corruption.
Change-Id: I693d74a20807450008235e6ef6bfe6fa7061f781
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Some of the determine_rate callbacks rely on the clock parent to
determine the rate. This isn't possible if the clock is orphaned without
a parent. So return an error in this case instead of dereferencing NULL.
Change-Id: Ifaa8f2a85a8f8d4e37895c0b130e4eaefb0374cb
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Return correct corner voltage for qcom_clk_get_voltage api for
a clock which supports multiple vdd class.
Change-Id: Ic2faa12ae85730aa1025ed342effa3052adc1062
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Add clk_get_vdd_corner as some clocks have requirement to vote on
multiple clk_vdd_class for clock operations.
Change-Id: I03da2134f9a8439a734f7638b61479269a9cec89
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Some clocks are critical only on specific boards, i.e. clocks used to
interface with external PMICs over I2C. Which clocks are critical depend
on which I2C bus is chosen to connect the PMICs. To support this, add
properties to set QCOM_CLK_IS_CRITICAL on a per-board basis.
The qcom,critical-clocks property can be used to set
QCOM_CLK_IS_CRITICAL on individual clocks.
The qcom,critical-devices property can be used to set
QCOM_CLK_IS_CRITICAL on all clocks used by specified devices.
Change-Id: I42d61ec13225026ba7d0b78079cf7a2ab67339f2
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add QCOM_CLK_IS_CRITICAL, which can be used to enable a clock by default
in HW and to skip registering it with the framework.
Change-Id: I803a447fae742ca2e20973046090d2b8331ab598
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
The existing clk_hw_get_name() only works after the clock has been
registered with the framework since it relies on hw->core->name and
hw->core is NULL pre-registration. hw->init->name can be used
pre-registration, but this doesn't work post-registration since the
framework sets hw->init to NULL.
Provide qcom_clk_hw_get_name(), which can be called in both pre and
post-registration contexts.
Change-Id: I334e545f5112961b7ab6879daca55c70236338d6
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Some clocks have requirement to vote on multiple clk_vdd_class for clock
operations. So add the support to pass multiple vdd_class within the clock
structure to support this functionality. A new clk_vdd_classes list is
added in clk_vdd_class_data structure to pass clk_vdd_class as an array
to support voting on multiple rail.
Change-Id: I11732a39ef99fdbcb7874e1042776e7007bed35f
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Normally clk_vote_vdd_level() and clk_unvote_vdd_level() are called
while holding the clock framework's prepare_lock since they are called
in the prepare paths. However, we're also calling clk_unvote_vdd_level()
from qcom_cc_sync_state() when removing proxy votes. This happens
outside of the clock framework, so the prepare_lock isn't protecting
this case. If the sync_state callback fires while another thread is
voting/unvoting voltage from a normal clock call, then there's a race
condition that can result in regulators being set to the incorrect
voltage or being pre-maturely disabled.
Add a mutex to protect this case.
Change-Id: Ib979e2edaaa5824dc80f7d4f065d72ca0b1a4444
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add helper functions to suspend or resume the device associated with a
clk_regmap.
Change-Id: Ie4e47fce64e2052ffacdc3a8cd56fc69758d70fb
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add common runtime_pm initialization and callback functions to allow
clock providers to vote clocks, interconnects, and regulators in
runtime_suspend and runtime_resume.
Change-Id: I97588feae47016b8375849c5926495c1d73f792d
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Clock consumers gets deferred due to their dependencies during device
boot/probes, and can not put essential vdd vote before clock late init
clk_disable_unused() un-votes them. This behavior breaks functionality of
keeping clocks/feature continuously enabled from boot to HLOS. Putting
proxy vdd votes will ensure that votes are hold till consumer sync states
and it gives chance to consumers act on necessary votes when it's ready.
Also clock controller can not rely on consumers to vote vdd votes during
boot/probe sequence in all paths of clk provided consumed APIs. Putting
proxy votes makes sure that clk driver can access it's provided register
access.
Change-Id: I79301ff354b3ab53cc7c05db5e1dc75223228de6
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
To clean up clock controllers probe function, move to common regulator
handle initialization.
Also add common multiple regulator initialization support within
single clk_vdd_class.
Change-Id: I999966d3bc877e0e8bcbb54839c0dd86f41869bd
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Some clock driver clients need the frequency to voltage
mapping to be exposed. Add support to load and expose
these values through OPP tables associating to a device.
Change-Id: Iab3e34f53cab1db07fb2e78b378ed18a4dd8d90b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This ops is used to force off a clock when clk_disable() is called. CLK_DIS
bit can be used to force off respective clock.
Change-Id: Iec4204fe3bf24965d1603d0f86e74cc2818e3d1c
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
In the cases where the branch clocks requires to vote on a voltage rail
add the clock ops callbacks for the same.
Change-Id: If7ffbc4fdda1fb71c1d097f56a5eb762859eb2c4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The qcom_clk_set_flags API would be used to set/clear the memory
flags for the desired branches.
Change-Id: I58b2347f63d382168b61dd04ead57ad114559eb2
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add new API for clients to query corner voltage required by a
given frequency.
Change-Id: Ic469c36e016899d882ca084f74e0d2cb2020476c
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Providers adds ops for list rate and print reg debug nodes
to print necessary debug information, these nodes
can not be added to clk framework and is moved down to provider level.
Since provider does not have complete knowledge on clks owned
at clk framework, providers can not blindly typecast clks owned
by clk framework to call its list/print ops.
A separate qcom_regmap_list is maintained during qcom clk
registration with clk framework. So as when debug list/print
calls are called, provider have knowledge of qcom clks
and only call respective ops on qcom clks maintained
in clk_regmap_list.
Providers can use this API to know if clk is qcom regmaped clk.
Change-Id: I3e4d8280c8fa0c692f855c0d6659dd14f95008df
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
When set_rate is called on unprepared clocks new vdd_level
requirement is not cached, which leads to incorrect votes
when later clk_prepare is called. Clocks may not be prepared
when clk pre change rate is called for set_rate change request,
thus cache vdd level and only apply vote during clk prepare.
Change-Id: I54d9a3c75034cd9e67e683c3f71088f2c7cd3db1
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Specify prepare, unprepare, pre_change_rate, post_change_rate callbacks
for alpha-pll clk_ops. This ensures that supply regulator requirements
are managed properly at runtime.
Change-Id: I578b81c2ab77a8d7e2332098bd737b0646cf577d
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Some rpmh clocks aren't present on all boards, so allow marking some as
optional.
Change-Id: I6d2165a84f7e06febc7ea2694c1fb4a2ef9309d5
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add generic sync_state function that can be used by qcom clock providers
(qcom_cc_sync_state). Currently this is just a simple wrapper around
clk_sync_state from the framework, but ultimately will contain
additional qcom-specific logic.
Change-Id: I936daafdd19cc7676daa4b9fbe712d9b3181395f
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Specify prepare, unprepare and pre/post rate change callbacks for all
clk-rcg2 clk_ops. This ensures that supply regulator requirements are
managed properly at runtime.
Change-Id: I6d7e31983e99c2ef9f546771d7046e8f0111debc
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add support for prepare, unprepare, pre and post rate change regmap
clk_ops callback functions for regmap clocks to handle regulator
requirements.
Change-Id: If4657adcc047e1ca005d3d4f7ab88146dba85ee0
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Add support to manage voltage supply regulators via the
vdd-class voting interface. Provide functions that can be
easily used to implement clk_ops callbacks used for voltage
voting.
Change-Id: I891b5944ed8075074c11f139d9e6951d796c7f90
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Define a vdd_levels enum and vdd_corner[] mapping table which can
be used by clock controller drivers to configure the vdd_class
associated with their clocks.
Change-Id: Ia0c2ed35f7c87cc3dc9947844625a463745e2ac5
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add a condition check to ensure that a reset controller is only
registered for a given clock controller inside of the
qcom_cc_really_probe() function if more than 0 resets are
defined for it.
Change-Id: Iffdfce1f7609ccab184a61c4a448a7edc15bb4ab
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for device tree consumers to utilize clocks which
are registered via clk_hws in struct qcom_cc_desc.
This modification is effectively
commit 84196373f39d ("clk: qcom: Support to add hardware clocks
to of_clk_hw_provider")
reconciled with
commit 760be6586f ("clk: qcom: Make common clk_hw
registrations").
Change-Id: I1e0bdeecd2d4092bff3110168438211493f4feda
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Currently, if clk_set_rate() is called on a disabled clock that
has flags = FORCE_ENABLE_RCG, the rate is neither physically set
nor properly cached in software. This means that when the clock
is later enabled, its rate will not be what was previously
requested.
Change the handling of FORCE_ENABLE_RCG so that all clk_set_rate()
calls are respected regardless of a clock's enable state. In
doing so, ensure that FORCE_ENABLE_RCG and enable_safe_config are
supported both individually and together.
Implement the following behavior:
enable_safe_config == true:
enable - configure the RCG according to the cached current_freq
disable - configure the RCG for CXO (safe) source
set_rate - (if prepared) configure the RCG for the requested rate
(if not prepared) cache the rate in current_freq
flags | FORCE_ENABLE_RCG:
enable - set ROOT_EN=1 to force the RCG to be enabled
disable - set ROOT_EN=0
set_rate - configure the RCG for the requested rate;
if disabled, then set ROOT_EN=1 before the
configuration is changed and ROOT_EN=0 after
enable_safe_config && (flags | FORCE_ENABLE_RCG):
enable - set ROOT_EN=1 and configure the RCG according to the
cached current_freq
disable - configure the RCG for CXO source and set ROOT_EN=0
set_rate - (if prepared) configure the RCG for the requested rate
(if not prepared) cache the rate in current_freq
Change-Id: Ib7442e4a4b572ae7c567929044410e09a9886c76
Signed-off-by: David Collins <collinsd@codeaurora.org>
The commit eb325c3d2a90 ("clk: qcom: clk-rcg2: Read RCG source before
calculating clk rate")' had introduced a function to update the src map,
but there could be a race where a set_rate for a clock from a particular
CC on a CPU could override the global cxo_f which was set by clock
enable/disable for a clock from another CC.
Change-Id: Id86818895e226a387e7fd1a09e2034eee18fd361
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add null pointer checks for the parent clock pointers returned
by clk_hw_get_parent() and clk_hw_get_parent_by_index() in
several qcom clock drivers.
Change-Id: I869c9e35b7ec083b34bcc70d18601aec64c3ac97
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support to configure cal_l fields for PLLs.
Change-Id: Ib5a7a74aecd8d9885e0a3034f097c13cda4d2268
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Add a check of the cxo_hz value to ensure that it is greater than
0. That way, there is no chance of division by zero when using
cxo_hz to calculate cxo_period_ns.
Change-Id: I5498b7a08e4cb3be45469041a973d045f2ec2bdb
Signed-off-by: David Collins <collinsd@codeaurora.org>
Some boards utilize several PMICs which contain clock divider
peripherals. Add support for the clock-output-names property
so that unique names can be specified for each divider clock.
If clock-output-names is not specified, then the clock names
will be div_clkN where N=1 to qcom,num-clkdivs.
Change-Id: I66b5fcd0a3890886fe1e8cd85b15ada8a55ecb0f
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a flag to indicate to support and enable hardware control mode
of an RCG.
Change-Id: I21194a463441ea13b7575a4174b1f96504b42b1e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
If the clock rate is set previously to hlos and enable
safe config is true. In that case we need to check the
rcg source to make sure recalc will return correct rate.
Rate calculation is done based on selected source rather
than 19.2 MHZ. Also, we are setting correct src value for
XO based on the parent map of a particular clock.
Change-Id: Id6d2923136a0848d55cff37fb5ef2e3b092af27a
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
There could be cases where a simultaneous clk_disable and clk_set_rate on
the same rcg could result in a wrong recalc rate. So for shared rcgs
get the pre_div value based on the current frequency from the frequency
table.
Change-Id: Ia5730e43965b2d0ba19da05fca47825514f98865
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Alpha BW for Fabia PLL is 16 bit and the calculated hw rate has
additional KHz of frequency. Due to this additional frequency, the
source is wrongly selected. Truncate the additional KHz using the
DIV_ROUND_CLOSEST_ULL.
Change-Id: Ic9c523c87277c4813b676cf8a52a1207e8f1ecc2
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Some RCGs could have sources with dynamic frequencies and fixed sources
where if the RCG has the flag of CLK_SET_RATE_PARENT set, it would try to
propagate the clock rate to the fixed source PLLs too. To identify sources
of the RCGs where the rate should propagate to parent PLL, add a member in
freq_tbl to represent source frequency. This would be used by the
_freq_tbl_determine_rate to set its parent frequency on the PLL.
Change-Id: I7f1c0d9d84607821893a1e5d17934dae5acef5f4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, it is desirable for an RCG to be turned on
explicitly instead of just relying on the enable signal from
its branch clock(s). Add support for this.
Change-Id: I2b0b81bddfe7cc7543c313e4ed13a332fb1a0fcb
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, an RCG might be prone to being enabled even
though the overlying software thinks that it disabled the RCG.
In order to avoid letting the RCG go into an invalid state, support
parking it at a safe frequency during clk_disable() and deferring
all the RCG configuration updates to be done during clk_enable(),
if a scaling request comes in whilst the clock is disabled.
Change-Id: I55f1d1d346182a2b480127c57d6659fc9a63331b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
The clk-divider module in the clock framework provides support
for different kinds of dividers such as power-of-two and discrete
table based dividers. clk-regmap-divider module which adds regmap
support to the clk-divider doesn't handle the flags and table
parameters in the clk-divider that enables these divider types.
This change adds those two parameters to the clk-regmap-divider
struct and passes them to the clk-divider appropriately.
Change-Id: I0f9a923a62786b19264c45bbcf2400292ed7e61f
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Add new ops to allow clock clients to enable/disable hardware
dynamic gating of the clock branch.
Change-Id: I14abed3827de8cefc31f3deb3c1e589136c32b8d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add the clk-qcom module, which is required by clk-dummy for measure
support and for future cc modules such as gcc.
Change-Id: I14fabfc40ab51b7d21858c4dafb2c87abac3889a
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
