github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-08-01 03:59:40 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

clk: qcom: add null pointer checks for parent clocks

Browse Source 
Add null pointer checks for the parent clock pointers returned
by clk_hw_get_parent() and clk_hw_get_parent_by_index() in
several qcom clock drivers.

Change-Id: I869c9e35b7ec083b34bcc70d18601aec64c3ac97
Signed-off-by: David Collins <collinsd@codeaurora.org>
This commit is contained in:
David Collins 2019-03-27 15:46:41 -07:00 committed by Mike Tipton
parent 6e0b4c6522
commit 0980686087
3 changed files with 21 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2015, 2018-2019, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@ -1002,6 +1002,7 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
struct clk_hw *parent_hw;
u32 ctl, div;
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
@ -1010,8 +1011,13 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
ctl &= BIT(pll->width) - 1;
div = 1 << fls(ctl);
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
parent_hw = clk_hw_get_parent(hw);
if (!parent_hw)
return -EINVAL;
*prate = clk_hw_round_rate(parent_hw, div * rate);
}
return DIV_ROUND_UP_ULL((u64)*prate, div);
}

6
drivers/clk/qcom/clk-rcg.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Copyright (c) 2013, 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@ -414,6 +414,8 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index);
if (!p)
return -EINVAL;
if (clk_flags & CLK_SET_RATE_PARENT) {
rate = rate * f->pre_div;
if (f->n) {
@ -465,6 +467,8 @@ static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
if (!p)
return -EINVAL;
req->best_parent_rate = clk_hw_round_rate(p, req->rate);
req->rate = req->best_parent_rate;

8
drivers/clk/qcom/clk-rcg2.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@ -821,6 +821,8 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
/* Force the correct parent */
req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
if (!req->best_parent_hw)
return -EINVAL;
req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
if (req->best_parent_rate == 810000000)
@ -875,6 +877,8 @@ static int clk_byte_determine_rate(struct clk_hw *hw,
return -EINVAL;
req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
if (!p)
return -EINVAL;
req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
@ -1101,6 +1105,8 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
return -EINVAL;
xo = clk_hw_get_parent_by_index(hw, 0);
if (!xo)
return -EINVAL;
if (req->rate == clk_hw_get_rate(xo)) {
req->best_parent_hw = xo;
return 0;