From 09806860871c07a9946cab5ab3ecabf74bd7e994 Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 27 Mar 2019 15:46:41 -0700 Subject: [PATCH] clk: qcom: add null pointer checks for parent clocks Add null pointer checks for the parent clock pointers returned by clk_hw_get_parent() and clk_hw_get_parent_by_index() in several qcom clock drivers. Change-Id: I869c9e35b7ec083b34bcc70d18601aec64c3ac97 Signed-off-by: David Collins --- drivers/clk/qcom/clk-alpha-pll.c | 12 +++++++++--- drivers/clk/qcom/clk-rcg.c | 6 +++++- drivers/clk/qcom/clk-rcg2.c | 8 +++++++- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 0ea9e17b78f4..6b5fa0d8433c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2018-2019, The Linux Foundation. All rights reserved. */ #include @@ -1002,6 +1002,7 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + struct clk_hw *parent_hw; u32 ctl, div; regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); @@ -1010,8 +1011,13 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, ctl &= BIT(pll->width) - 1; div = 1 << fls(ctl); - if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) - *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + parent_hw = clk_hw_get_parent(hw); + if (!parent_hw) + return -EINVAL; + + *prate = clk_hw_round_rate(parent_hw, div * rate); + } return DIV_ROUND_UP_ULL((u64)*prate, div); } diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index a9d181d6be21..782380a7452d 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2019, The Linux Foundation. All rights reserved. */ #include @@ -414,6 +414,8 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, clk_flags = clk_hw_get_flags(hw); p = clk_hw_get_parent_by_index(hw, index); + if (!p) + return -EINVAL; if (clk_flags & CLK_SET_RATE_PARENT) { rate = rate * f->pre_div; if (f->n) { @@ -465,6 +467,8 @@ static int clk_rcg_bypass_determine_rate(struct clk_hw *hw, int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src); req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); + if (!p) + return -EINVAL; req->best_parent_rate = clk_hw_round_rate(p, req->rate); req->rate = req->best_parent_rate; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index a6aeb4434ae9..dd2e86ab9f2b 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. */ #include @@ -821,6 +821,8 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw, /* Force the correct parent */ req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); + if (!req->best_parent_hw) + return -EINVAL; req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); if (req->best_parent_rate == 810000000) @@ -875,6 +877,8 @@ static int clk_byte_determine_rate(struct clk_hw *hw, return -EINVAL; req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); + if (!p) + return -EINVAL; req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate); div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1; @@ -1101,6 +1105,8 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw, return -EINVAL; xo = clk_hw_get_parent_by_index(hw, 0); + if (!xo) + return -EINVAL; if (req->rate == clk_hw_get_rate(xo)) { req->best_parent_hw = xo; return 0;